Pyxis SPT Hep

Technical Marketing
Deep Submicron Division

Pyxis Self Paced Tutorial
with Generic Design Kit
J uly, 2013
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2013 Mentor Graphics Corp. Company Confidential
www.mentor.com
Pyxis Self Paced Turtorial
Contents
Tutorials
1. Pyxis_SPT_Stage_1_Data_Management
2. Pyxis_SPT_Stage_2_Design_Capture
3. Pyxis_SPT_Stage_3_Analog_Simulation
4. Pyxis_SPT_Stage_4_Mixed_Signal_Verification
5. Pyxis_SPT_Stage_5_Analysis_of_Layout_Parasitics
6. Pyxis_SPT_Stage_6_Layout_Viewing_and_Editing
7. Pyxis_SPT_Stage_7_Floorplanning_and_Assembly
8. Pyxis_SPT_Stage_8_Schematic_Driven_Layout
9. Pyxis_SPT_Stage_9_Automated_Layout
Quick Start Recipes
1. Pyxis_QSR_Setup_Hotkey_Example
2. Pyxis_QSR_Customizing_the_Pyxis_GUI
3. Pyxis_QSR_Register_Custom_Data_Type_and_Tool
Pyxis QSR April, 2013
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Tutorials
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Pyxis Design Environment
Physical Verification
DRC, LVS,
xRC
Schematic Design
Hierarchical Schematics
Design Verification
Mixed Signal
High Level Design and Verification
Floorplanning
and
Assembly
Physical Layout Implementation
Full-Custom
Layout
Automated
Layout
HDL Compilation and Registration
Analog
RF
Parasitic Modeling
Area Estimation
Design Configuration
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Stage 1: Design Data Management
DRC, LVS,
xRC
Design Capture
Design Verification
Mixed Signal
Floorplanning
and
Assembly
Full-Custom
Layout
Automated
Layout
HDL Compilation and Registration
Analog
RF
Parasitic Modeling
Area Estimation
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In this session, you will
See overview of Pyxis
Design Manager
Perform the following
tasks:
Open online
documentation
Navigate and open
design data
Create a new project
Copy hierarchical data
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Data Management Requirements for Custom ICs
Organized structure
Support language models
PROJECT ONE
Design Library
(Digital)
Design Library
(Analog)
Design Library
(Testbenches)
Design Library
(Stimuli)
PROJECT TWO
Design Library
(DSP)
Design Library
(ADC/DAC)
Design Library
(RF)
Design Library
(Simulations)
REFERENCE LIBRARIES
Technology
Design Kit
Standard Cell
Library
Pad Cell
Library
Analog Cell
Library
Hierarchy Management
Revision Control
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Pyxis Project Manager
Project Based Data
Management - intuitive
Windows style
navigation
LCV Style Data
Organization
Register 3
rd
Party Tools
and Data
API for Revision Control
Subversion 1.4.6
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Organized Structure
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Hierarchy Management
Updates design references upon rename
Design references automatically
corrected on copied set
Build Hierarchical Configurations and
Releases
Hierarchical Copy, Move, Delete
Multi-project Support
View Multiple Projects in One Session
Project Cloning
View and Sort by Data
Attributes
Object Type,
Description, Size,
Permissions, Date
Modified, Lock
Key Features
User and Site wide
Customization
Customize Toolbars,
Hotkeys, Menus
Register custom data
types
Register custom tools
Scripting
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Step 1: Open Pyxis_SPT Project Data
1. From the Pyxis_SPT directory, run
the ./open_Pyxis_SPT script
NOTES:
The Pyxis_SPT tarball will unpack into a
directory called Pyxis_SPT. There are two
script files:
setup_Pyxis_SPT will reset the
Pyxis_SPT project to the original state.
Only use this to initialize or reset your data
open_Pyxis_SPT will open the Pyxis_SPT
project as it was last saved
open_Pyxis_SPT will take two options:
-mysettings will use your current
tool home directory
-default will use default tool settings
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Step 2: Getting Help Users Manual
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1. In the Pyxis Project Navigator
window, select the pull-down
menu item
Help->Open Users Manual
NOTE:
Help in the form of documentation,
tutorials and live support is available at
all IC design stages when using Pyxis.
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Step 3: Viewing Object Attributes
The Pyxis Project Navigator has two
primary windows for viewing IC
design data the explorer pane on
the left and the view pane on the
right
1. In the Pyxis Project Navigator
window, position your mouse
over the column header and use
the RMB (Right Mouse Button)
pop-up menu to view object
types for the explorer pane and
the view pane as shown
NOTE:
Each object type has its own distinctive
icon.
1:RMB
Explorer Pane View Pane
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Step 4: Hierarchical Object Types
1. Select the GenericPLL Library under
the Pyxis_SPT project
2. Examine the object types shown in
both the explorer and view panes
NOTES:
Pyxis Hierarchical Objects include:
Project A design project.
Library - A design library within a project that
contains IC design data. This is generally
where new designs are created.
External Library A reference library
containing IC design data. This is generally
static.
Logic Library - A reference library containing
only logic (process independent) data.
Technology Library - A technology design kit
with one or more technology configurations that
specify the symbols, parameterized devices,
rule decks and simulations.
Category A container within a Library
containing IC design data.
Component Set A virtual grouping of cells.
Cell A piece of a hierarchical IC design
containing Schematic, Symbol, Layout and other
relevant views.
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Step 5: Design View Types
1. Select the cell Pyxis_SPT/
GenericPLL/ charge_pump_ub
2. Examine the view types
shown in the view panes
3. Double Click on the Schematic
view type to open the schematic
NOTE:
Shown are generally the most
common IC Design view types.
Additional view types can be managed
in Pyxis, including custom views that
require custom tools.
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Step 6: Opening a Schematic
1. Briefly examine the
charge_pump_ub
schematic in Pyxis
Schematic before closing
the window
NOTE:
There are 4 tutorials in the
Pyxis SPT covering the Pyxis
Schematic editor on the
topics of Design Capture,
Mixed Signal Verification,
Analog Simulation and
Analysis of Post-Layout
Parastics.
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Step 7: Opening a Layout
1. Double Click on the Layout
view type to open the
charge_pump_ub_layout view
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Step 8: Opening a Layout
1. Briefly examine the
charge_pump_ub_layout in
Pyxis Layout before closing
the window
NOTES:
There are 4 tutorials in the Pyxis
SPT covering the Pyxis Layout
editor on the topics of Layout
Editing and Viewing,
Floorplanning and Assembly,
Schematic Driven Layout and
Layout Automation. Additionally,
you may want to view the
tutorial on Analysis of Post-
Layout Parastics.
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Step 9: View Message and Transcript Areas
1. In the Pyxis Project
Manager, click on the
Transcript Area tab to display
the detailed transcript log
2. Examine the Transcript
Area window
3. Repeat for the Message
Area window
NOTES:
The Message Area displays key
messages to the user regarding
tool commands while the
Transcript Area window provides a
detailed log of the commands
executed and the results.
The Transcript Area and Message
Area windows can be collapsed
and expanded, pinned at the
bottom or top of the Pyxis
window, or detached as a
separate window.
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Step 10: Create a New Project
1. Select the Pyxis_SPT project
2. Click on the New Project
icon in the toolbar on the left
hand side
3. Append the Project path with
MyProject to specify the name
of the new project
4. Enable the Derive Settings
from Existing Project option
and OK the New Project form
NOTES:
The new project will have the same
Technology Library and Configuration
(settings) as the Existing Project as
specified in step 1.
A Technology Library can have
multiple Configurations - this
addresses the need for process
variants
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Step 11: Specify Reference Libraries
1. OK the Manage
External/Logic Libraries
form to use the default
reference libraries from
the original project
NOTE:
Reference Libraries can be
changed on a selected project
or external library using the
pull-down menu item Edit->
External/Logic Libraries
command.
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Step 12: Create Design Library
1. Click on the New
Library icon in the toolbar
on the left hand side
2. Enter MyLibrary as the
new library name and OK
the form
NOTE:
Multiple projects can be viewed
inside of the Project Navigator
even when they are attached
to different technology libraries
or technology configurations.
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Step 13: Copy Design Object
1. In Project Navigator select
the Pyxis_SPT/ GenericPLL/
FreqSynth cell and select the
popup menu item: RMB (Right
Mouse Button)-> Copy
NOTE:
The Pyxis Project Navigator window
supports common hotkeys for
copying and moving data
Control+c Copy
Control+x Cut
Control+v - Paste
Control+Shift+v Paste Special for
special options like hierarchical copy.
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Step 14: Paste Design Hierarchy (Follow references)
1. Select the newly created
MyLibrary library
2. With you mouse
hovering of the MyLibrary
library, select the popup
menu item: RMB->Paste
Special menu
3. In the Copy Object form,
enable the Follow
references option, then OK
the form
NOTE:
If you do not want to change
the name of the copied object,
you can leave the Name field
blank.
2:RMB
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Step 15: Check References
1. Examine the results of the
copy
You should see the copied cell
FreqSynth, as well as a new
library under your project named
GenericPLL. This contains the
leafs of the FreqSynth design.
2. Select the FreqSynth cell
under MyLibrary
3. Click on the Check
References icon
NOTE:
Pyxis Design Manager preserves
the data hierarchy structure of
copied hierarchical data.
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Step 16: Examine Copied Design References
1. Examine the hierarchical references of
the newly copied FreqSynth design in the
Change/Fix References form before
clicking on the Cancel button to close the
form
You will see references to leaf cells that have
been copied into the GenericPLL library under
the MyProject project. You should also see
references to external libraries, logic libraries
and the technology library generic13.
NOTE:
The Change/Fix References form helps us to
see what references are in the selected objects
and to quickly change or fix them.
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Step 17: Select and Cut Leaf Cells
1. Select the MyProject/
GenericPLL library in the
explorer pane
2. Select one of the cells in
the view pane,
3. Enter the hotkey Control-
A to select all of the cells
under the MyProject/
GenericPLL library
4. Select the pop-up menu
item: RMB->Cut
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3: Control-a
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Step 18: Create New Category for Leaf Cells
1. Select the MyLibrary
library
2. Click on the New
Category icon
3. In the New Category form,
specify the object name to
be PLL_Leafs
NOTE:
Like directories in a file system,
categories can be created inside
of libraries and inside of other
categories
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Step 19: Paste Leaf Cells into New Category
1. Select the newly created
PLL_Leafs category
item: RMB-> Paste
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Step 20: Check Design References
The references to the moved data
will be updated automatically by
Pyxis. We can verify this by
looking at the Check References
form again
References icon
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Step 21: Verify Updated Design References
1. Examine the hierarchical references of
the updated FreqSynth design in the
Change/Fix References form before
clicking on the Cancel button to close the
form
You will see references to leaf cells are now
updated to point to the new location in the
MyProjects/MyLibrary/PLL_Leafs category
This concludes the Design Data Management
tutorial. Please feel free to explore this data
further or move on to the next stage in the
Pyxis_SPT.
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Summary
Pyxis Project Manager provides:
Intuitive and structured design organization
Support for all major IC design formats including the Schematic,
Symbol, and Layout
Interactive data management on individual components or full
design hierarchies
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Stage 2: Design Capture
DRC, LVS,
xRC
Transistor Level
Schematics
Design Verification
Mixed Signal
Floorplanning
and
Assembly
Full-Custom
Layout
Automated
Layout
Block-Level and HDL Modeling
Analog
RF
Parasitic Modeling
Area Estimation
Design Capture
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In This Session, you will
See a quick overview of Pyxis Schematic
Perform the following tasks:
Create a new schematic
Instantiate transistors
Use object editor with cycle selection toolbar
Generate a new symbol
Instantiate the new symbol into a schematic
Perform a transient simulation
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Pyxis Schematic
Single environment for
Design capture
Interactive simulation
setup
Simulation and analysis of
digital, analog, and/or RF
Display DCOP data to
schematic
Back Annotate
Post layout spice & DSPF
Interactive parasitic
debugging
Language modeling
Verilog, VHDL
Verilog-AMS, VHDL-AMS
SPICE, VerilogA
Hierarchical Model Selector
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Edit Object
Technology rule driven device parameter
editor dialog box tied to q hotkey
Also available as a dockable, direct edits
without extra clicks to Apply
Edit multiple devices at once or use Selection
Toolbar to cycle selected objects
Available for existing instances or during add
instance
Same editor for both Pyxis Schematic and
Layout
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Frames
Create CASE/IF/FOR Frames
to configure your design based
on the design stage (for
example pre-layout, post-layout,
LVS)
Implicit Pins
Configure a symbols
connectivity with properties
enables better support for
multiple power supplies
Function Blocks
Create more consolidated and
readable designs using
Function Blocks to define
design hierarchy
Advanced Constructions
Single-bit adder
schematic
8-bit adder schematic
8-bit adder function block
N-bit counter using FOR frame and standard cells with
implicit pins
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Pyxis Schematic User Interface
All Pyxis Session Windows provide Pull-Down and Pop-Up Menus as
well as moveable and detachable Toolbars, Palettes and Area
Windows
Customizable by user or site-wide
Menubar
Palette
Right Mouse Button
Pop-Up Menu
Toolbar
Area Windows
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Pyxis Schematic Hotkeys
All Pyxis Session Windows provide hotkeys
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Pyxis Schematic Strokes
All Pyxis Session Windows provide Strokes
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Pyxis SPT HEP, 2013
If your project is already open, you
can skip this step
1. From the Pyxis_SPT directory,
source the open_Pyxis_SPT script
NOTES:
directory called Pyxis_SPT. There are
two script files:
Only use this to initialize or reset your
data
open_Pyxis_SPT will open the
Pyxis_SPT project as it was last saved
tool home directory
-default will use default tool
settings
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Step 2: Create New Library
1. Select the Pyxis_SPT project
2. Click on the New Library icon
in the Project Navigator toolbar
3. Specify the library name to be
MyLib and OK the New Library
dialog
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Step 3: Create New Schematic
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1. Select the newly create
MyLib library
2. Click on the New
Schematic icon in the Project
Navigator toolbar
3. Specify the new Cell name
to be buffer (leave the
Schematic name as
schematic) and OK the New
Schematic dialog
NOTE:
This will open Pyxis Schematic
see next slide.
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Step 4: Instantiate a Device Symbol
1
1. Click on the Instance
icon in the Edit toolbar
2. In the File Browser,
select the symbols
category under the
generic13 technology
library
3. Select the nmos device
and OK the dialog
NOTE:
You can also use the hotkey i
to add an instance.
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Step 5: Place NMOS Instance
(Prior to placing device in
canvas)
1. Show the Add Instance
dialog by typing q in the
schematic canvas
2. Change the Width
property to 0.6u
(Hit the TAB key to register
the change in the dialog,
Dont hit Apply or OK)
3. Place the NMOS device in
the schematic canvas
NOTES:
When adding instances, you
dont need to click on the Apply
button to save changes the
placement click performs the
apply.
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Step 6: Copy NMOS Instance and Edit
1. Select the NMOS instance
2. Enter the hotkey c for
copy
3. Place the copy to the
right of the first placement
4. Type q to open the Edit
Object dialog
The focus will be on the Width
property which is the most often
edited property.
5. Enter 1.8u and type
return
NOTES:
Use the mouse wheel to zoom in
and zoom out. You can also use
diagonal MMB strokes to zoom to
an area.
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In mid-command zooming and
panning can be performed by
doing a MMB stroke or using
your mouse wheel.
Take a moment to become
familiar with zooming and
panning using MMB
(Middle Mouse Button)
strokes and if available,
your middle mouse scroll
wheel before moving to
the next step
NOTES:
Pyxis Layout recognizes inputs
from the mouse scroll wheel on
all of its major forms.
Shift +
Control +
Zoom-In Zoom-Out
Pan Horizontal
Pan Vertical
Pyxis SPT J anuary, 2013
Zooming and Panning with Middle Mouse Wheel
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Step 7: Browse for PMOS Device
1. Type i to open the
Add Instance File
Browser
2. Select the pmos
device as shown and
click OK
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Step 8: Place PMOS Devices
1.Place the M3 pmos
instance as shown
2.Use the same sequence
you did for the nmos to
copy the pmos
3.Use the q hotkey to edit
the width of the second
pmos to be 6u
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Step 9: Select All Devices
1. Hold down the shift
key and select all four
devices (if they arent
already selected)
NOTE:
The Status toolbar indicates
how many total objects are
selected.
1:Shift-LMB
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1:Shift-LMB 1:Shift-LMB
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Step 10: Change Common Property
1. Type q to bring of the
Edit Object dialog
2. Hit the tab key once to
set the focus to the Length
property value and then
enter 0.14u
3. Hit the Enter key to
apply the changes and take
down the Edit Object form
NOTE:
All the length properties on the
instances will be changed
together.
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3: Enter
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Step 11: Cycle Selection
1. Click on the Select and
Center icon in the Selection
toolbar
2. Click on the Cycle Next
icon in the Selection toolbar
to view the individual
property settings of each
device in the selection set
NOTE: Cycle selection has 3
viewing modes:
Select
Select and Zoom
Select and Center
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Step 12: Reset Selection
1. Click on the Reset Cycle
icon in the Selection
toolbar to select and
center the original
selection set
2. Click on an empty part
of the schematic canvas to
unselect everything
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Step 13: Add Wires
1. Click on the Zoom Out
(2x) icon
2. Click on the Add Wire
icon or type w to add
wires
3. Draw the wires as shown
Add Wire Tips:
-The add wire command
remains active until you hit the
escape key
-Use hotkey f to flip the wire
corner
vs
-Use x hotkey to toggle
orthogonal wire routing
-Use Backspace to delete the
last segment if you make a
mistake
NOTE:
Mouse wheel zooms in/out
Hotkey w starts Add Wire.
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Step 15: Add Net Names
1. Click in open space to
unselect everything
2. Hold the Shift key and
select the four nets shown
(segments highlight red
when you hover over them)
3. Type l to label the nets
4. Enter these names:
a. vdd_imp (return)
b. Ain (return)
c. Zout (return)
d. vss_imp (return)
NOTE:
When Multiple nets are selected,
the naming order is determined
by the top most net, then the
left most net.
4c
4a
4d
4b
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Step 16: Add Ports
1. Expand the add ports
icon and select Add Port
In...
2. Add a Port In to the Ain
net
3. Repeat steps 1 and 2 to
add a Port Out to the Zout
net
4. Click on the Check and
Save icon or enter the
hotkey Control-x to check
for errors and then save the
schematic
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NOTE:
If there are errors, a report
window will appear. You can
select object names or handles
in the text to find the object.
When done, close the report
window using the red X icon.
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Step 17: Create Symbol
1. Select the pull-down
menu item Add->Generate
Symbol
2. In the Generate Symbol
dialog, click on the Choose
Shape button
3. In the Choose a Symbol
Shape dialog, specify the
shape to be Buffer then OK
4. Click on the Choose
Implicit Pins button
5. Enable the two entries in
the Set Implicit Pins dialog
then OK all the forms
NOTE:
To be an implicit pin candidate, a
net needs to be named and not
attached to a port.
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Step 18: Check and Save Symbol
1. With the symbol canvas
active, click on the Check
and Save icon
2. Observe the Transcript
Area and Message Area for
Check and Save warnings
and errors
3. Close the buffer symbol
by clicking on the red X
icon in its tab
NOTE:
If there are errors in the
design, a report window is
generated.
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Step 19: Open Existing Schematic
1. Click on the Browse
icon to open an existing
schematic
2. Select the schematic
view under the Pyxis_SPT
/ GenericPLL / Simulations
/ comparator /
tb_comparator cell
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Step 20: Open Down to a Schematic
1. Use the MMB (Middle
Mouse Button) down
stroke to descend into the
comparator_lc cell
NOTE:
You can also select the
instance and use the hotkey
Shift-e or select the pull-
down menu item Context-
>Open Down.
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Step 21: Instantiate Buffer Symbol
1. Type i to add an
instance
2. Browse for the new buffer
component (under the Pyxis_SPT
/ MyLib / buffer cell ) and click
OK
3. Type q and notice the
properties vdd_imp and
vss_imp
You can change these to the
name of a net at the level the
symbol is placed to configure the
inherited connection. This allows
control of the power and ground
to the devices on the buffer.
4. Place the instance at the
output as shown
NOTE:
The FSout wire will automatically
open when the buffer symbol is
placed.
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Step 22: Check and Save
1. Check and Save the
updated comparator_lc
schematic
There will be two warnings in
the log file indicating that
implicit connections exist within
the schematic.
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1. Click on the Enter
Simulation Mode icon
2. OK the Entering
Simulation Mode dialog
with the default settings
NOTE:
The transient design viewpoint
configuration is already setup
for a transient simulation.
Step 23: Enter Simulation Mode
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Step 24: Run Simulation
1. Click on the Run
Simulator icon
The simulation Log window will
appear showing information on
the simulation run.
2. After the Simulation is
completed, select the
minus, plus and fsout nets
3. Click on the Cross Probe
Selected Items toolbar icon
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Step 26: View Waveforms
1. Examine the simulation wave
form results
This concludes the Design Capture
tutorial. Please feel free to continue
exploring this material or move on to
the next tutorial.
NOTE:
Initially, the waveforms are selected,
clicking on an empty space will
unselect the waveforms to show you
the view to the left.
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Summary
Pyxis Schematic enables users to quickly create and
simulate schematics and supports:
Fast device placement with streamlined call-back support
Multiple device editing
Cycle selection
Change common properties on multiple instances
Add wires, net names and ports
Symbol generation
Implicit Pins enable designs with multiple powers and grounds
Analog and Mixed-Signal simulation environments
Pyxis SPT HEP, 2013
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DRC, LVS,
xRC
Transistor Level
Schematics
Design Verification
Mixed Signal
Floorplanning
and
Assembly
Full-Custom
Layout
Automated
Layout
Analog
RF
Parasitic Modeling
Area Estimation
Design Capture
Stage 3: Analog Simulation
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This tutorial stage provides examples of analog simulation techniques
using Pyxis Schematic. These examples include:
An introduction to Baselines, Configurations, and States <link>
Creating a User Baseline <link>
Creating a new configuration for VCO testing <link>
Creating a new state for VCO optimum bias setup <link>
Creating a new state for VCO frequency measurement <link>
Creating a new state for VCO phase noise measurement <link>
Creating a new state for VCO Process/Voltage/Temperature corner verification <link>
Creating a new configuration for comparator testing and hysteresis measurement <link>
Creating a new configuration for op amp testing and phase margin measurement <link>
Creating a new state for Monte Carlo op amp phase margin measurement <link>
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All the examples demonstrated in stage 3 assume that:
The user has installed the Pyxis Self Paced Tutorial. Refer to Stage 1 of this tutorial.
The environment variable $SPT_HOME has been set to the location of the Pyxis Self Paced Tutorial
installation.
The environment variable $AMPLE_PATH has been set to the location of the userware directory. In
this tutorial, the userware directory is located at $SPT_HOME/ic_reflibs/tech_libs/userware.
The user has invoked Pyxis Project Navigator. Refer to Stage 1 of this tutorial.
RMB = click the right mouse button
LMB = click the left mouse button
MMB = click the middle mouse button
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Typical hotkeys used in Schematic Mode:
f view all
i add instance
s enter Simulation Mode
w add wire
x add EZwavecross-probe
Typical hotkeys used in Simulation Mode:
a open Setup Simulation Analysis panel
F open Setup Simulation Forces panel
g open Setup Simulation form
l open Setup Simulation Libraries panel
p open Setup Simulation Params/Sweep panel
r run simulation
s setup environment
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New Concept
Baselines Configurations
and States
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Baselines Configurations and States
During the current Unsaved Session [A], the user edits various simulation settings [D].
Simulation settings may include analysis types, definitions, and parameters. The
aggregation of simulation settings is known as the Design Configuration [B]. The
simulation settings contained within the Design Configuration directly control the operation
of the SimMode Functionality (software) [C].
The Unsaved Session is located within volatile memory. Therefore, Pyxis Schematic
provides the ability to save a snapshot of the current Design Configuration [B]. This
snapshot is known as a state [E].
A
E
B
D
C
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A state [C] is a snapshot of the Design Configuration [A] at time t
n
. Where t
n
is the
moment the user invokes the Save State function. The state includes information such as:
analysis types, force definitions, measurement definitions, sweep parameters, PVT corner
parameters, and initial conditions [D]. Every state has a state_name [B]. This allows the
user to take multiple snapshots at different points in time.
Note: A state does not include simulation results. It only includes the simulation settings.
B
A
D
C
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A state [C] can also return the Design Configuration [A] to a previous time t
n
.
Whenever the user invokes the Load State function, the selected state
snapshot overwrites the current Design Configuration simulation settings [B].
The combination of Save State and Load State functions allow the user to:
Explore new simulation settings, then return to a known good state.
Define initial conditions and return to that state.
Define re-usable stimuli and measurement setups.
B
C
A
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An aggregation of state snapshots [A] is known as a configuration [B]. A configuration is
analogous to a photo album (a collection of snapshots). A configuration always includes 1 or more
state snapshots. Note: Do not confuse the term configuration (an aggregation of states) with the
term Design Configuration (simulation settings in the Unsaved Session).
Whenever the user loads a state [A] from a configuration [B], the selected state snapshot
overwrites the current simulation settings in the Design Configuration.
The user selects the type of simulator (Eldo
, ADMS, ADiT) that is used during the Unsaved

Session. A configuration always includes the Simulator Selection at t
0
[D] when the configuration
was created. The Simulator Selection at t
0
is the default simulator whenever the user opens a
configuration. The user may choose to override the default Simulator Selection.
Every configuration has a confiiguration_name [C]. This allows the user to have different setups
for different types of simulators. Multiple configurations also allow the user to define re-usable
stimuli and measurement settings for different designs. Configurations are stored in the Design
Configuration Database [E].
D
B
A
C
E
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Every configuration includes a special state snapshot, named default [C]. Default is
different than the other state snapshots. This is because default is not created by the Save
State function. Instead, the default snapshot [B] is automatically created whenever the
user exits Simulation Mode at time t
exit
[A].
In the context of Pyxis Schematic, it is more accurate to think of the default state as the
Design Configuration state when the user exited Simulation Mode.
C
B
A
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Whenever the user invokes the Enter Simulation Mode function [B], the Design
Configuration is initially undefined [A]. Normally, the user selects an existing
configuration from the Design Configuration Database [D]. This causes the
configurations default state @ t
exit
[C] to be automatically loaded into the
Design Configuration [A].
The end result is that the Design Configuration returns to the previous state
when the user exited Simulation Mode.
D
A
C
B
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B
D
A
The baseline is analogous to a staging area, where the initial Design Configuration [D] will
be assembled. When the user creates a new configuration at time t
0
[A], a sequence of
automatic steps occur. First, the simulation settings contained within the Default Baseline
file [B] are automatically loaded [C] into the Design Configuration [D].
The Default Baseline file [B] contains a collection of AMPLE functions that define
simulation settings such as: analysis types, measurements, and parameters. The Default
Baseline file is supplied by Mentor Graphics and is not accessible to the user.
C
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Next, if the Kit Baseline file exists [A], the simulation settings contained within the Kit
Baseline file are automatically loaded [B] into the Design Configuration [D]. Note that the
Kit Baseline settings can override some (or all) of the Default Baseline settings [C]. If the
Kit Baseline file does not exist, then the Design Configuration remains unchanged.
The Kit Baseline file contains a collection of AMPLE functions that define simulation
settings specific to the Process Design Kit (PDK). The Kit Baseline file is supplied by the
PDK vendor and is usually not accessible to the user.
A
B
D C
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Next, if the User Baseline exists [A], the simulation settings contained within the User Baseline are
automatically loaded [B] into the Design Configuration [D]. Note that the User Baseline settings [D]
can override some (or all) of the Default Baseline [C] and Kit Baseline settings [E]. If the User
Baseline does not exist, then the Design Configuration remains unchanged.
The User Baseline contains user defined AMPLE functions that define simulation settings specific to
the user. The User Baseline AMPLE functions are added to the daic_sim_mgr.ample file using a text
editor.
A
B
E C D
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The entire sequence appears to be instantaneous to the user. The user requests a new
configuration [A]; and the Design Configuration [C] is initialized to a pre-defined state. This pre-
defined state can be customized by the user through the User Baseline [B].
C
A
B
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This is an example of how baselines, configurations,
and states are used in a typical design environment.
The user enters Simulation Mode, requests a new
configuration, and selects a simulator (Eldo, ADMS,
ADiT) [A]. The simulator selection will be the default
simulator whenever the new configuration is opened.
However, the user can override this selection.
The Default, Kit, and User Baselines [B] sequentially
initialize the Design Configuration [C]. The Design
Configuration is now ready for simulation.
The user modifies the simulation settings [D]. This
changes the simulation settings created at t
0
[C].
The user runs simulations and views the results.
The user exits Simulation Mode at t
1
. The new
configuration [E] requested at t
0
is created in the
Design Configuration Database. The Simulator
Selection at t
0
[F] is added to the new configuration.
A snapshot of the Design Configuration, named
default [G], is added to the new configuration.
C
F
B
D
G
E
A
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When the user exits Simulation Mode, the Design
Configuration becomes undefined [B].
At time t
2
, the user enters Simulation Mode once
more [E]. The user selects the existing
configuration [D]. This causes the default state
snapshot [G] to be automatically loaded into the
Design Configuration [F]. At this time, the user may
also choose to override the Simulator Selection at t
0
stored within the configuration [C].
The Design Configuration now contains the
Simulation Settings at t
1
[F]. The end result is that
the simulation settings return to the state when the
user exited Simulation Mode [A]. To the user, it
appears that exiting Simulation Mode has no affect
on the simulation settings.
B
D
E
G
F
A
C
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The user continues to modify the simulation settings
and run simulations. This changes the simulation
settings restored at t
2
[C].
At time t
3
, the user decides that the current Design
Configuration [B] should be re-usable. The user
invokes the Save State function [A]. A snapshot of
the current Design Configuration is saved as a new
state [E] in the configuration [D]. The user assigns a
name to the new snapshot (bias_setup in this
example). The configuration now contains 2 states:
bias_setup [E] and default [F].
settings that were saved at t
3
[I].
At time t
4
, the user decides to return to a previous
Design Configuration. The user invokes the Load
State function [G] and selects the bias_setup state
snapshot [J ] in the configuration . The simulation
settings contained in the bias_setup snapshot are
loaded into the current Design Configuration [H].
C
A
E
F
B
D
I
G
J
H
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setup restored at t
4
[A].
At time t
5
, the user exits Simulation Mode [B]. This
automatically overwrites the default state snapshot
[C]. The default state now represents the Design
Configuration at t
5
.
A
B
C
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Summary
The following concepts were demonstrated in this section:
A state is a snapshot of the Design Configuration in the Unsaved Session. The state contains the
simulation settings at a point in time. States do not contain simulation results; they only contain the
simulation settings.
Multiple state snapshots can be created and named by the user. A state snapshot can be re-loaded into
the Design Configuration at some point in the future. State snapshots are typically used to return to
known good simulation settings; and to define re-usable stimuli and measurement setups.
A configuration is a collection of state snapshots and the user simulator selection (Eldo, ADMS, ADiT).
Other settings, such as model selections and back annotation properties are also stored within the
configuration. These other settings are beyond the scope of this tutorial.
Multiple configurations can be created and named by the user. Configurations are typically used to setup
the environment for the simulator (Eldo, ADMS, ADiT); and to define re-usable stimuli and
measurement setups for various types of circuits.
Every configuration contains a state snapshot named default. The default snapshot is automatically
taken whenever the user exits Simulation Mode. When the user enters Simulation Mode and selects an
existing configuration; the default state automatically returns the Design Configuration to its previous
settings.
When the user creates a new configuration; the Design Configuration is initialized by the baseline. The
baseline is a composite of the Default Baseline, Kit Baseline, and User Baseline AMPLE functions. The
baseline ensures that all new Design Configurations have consistent initial simulation settings. The User
Baseline can be customized by the user.
87
Example
Create A User Baseline
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Create The User Baseline
In the previous section <link>, we learned that the baseline is used to initialize the Design
Configuration [E] whenever the user creates a new configuration [A].
We learned that the baseline is a composite of 3 independent baselines: the Default Baseline [B], Kit
Baseline [C], and User Baseline [D]. The User Baseline is the only baseline that can be modified by
the user. The User Baseline simulation settings can overwrite any (or all) settings from the Default
Baseline and Kit Baseline.
We learned that the User Baseline is a collection of user defined AMPLE functions added to the
daic_sim_mgr.ample file.
A
B C
D
E
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Task: Create the User Baseline.
1. Open a Linux
terminal and create

directory $SPT_HOME/ ic_reflibs /
tech_libs / userware / da_ic.
2. Set the $AMPLE_PATH environment
variable to $SPT_HOME/ ic_reflibs /
tech_libs / userware .
3. Create a new file using a text editor.
Copy the code shown on the left, and
paste it into the file.
4. Save the file in the $AMPLE_PATH /da_ic
directory and name the file
daic_sim_mgr.ample .
5. Close the file and text editor.
The User Baseline now exists inside the
daic_sim_mgr.ample file.
// Start of User Baseline //
//********* Eldo specific function **********//
function $eldo_user_baseline(), INDIRECT
{
// Eldo simulator settings
$simulator_args("-x64", @true); // use 64bit
$netlister_args("-ground_nodes", ["GROUND"]);
$option(@convergence, @gmin, 1e-12);
// $option(@output, @stat, "1"); // report run-time
statistics
// general simulation environment settings
$temp(27);
$enable_probe_all(@V); // save all voltages
}
//********* ADMS specific function **********//
function $adms_user_baseline(), INDIRECT
{
$eldo_user_baseline(); // re-use the Eldo baseline setup
// ADMS simulator settings
// Note: not used in this SPT.
//$converter_hook("defmodel_0");
//$converter_hook("defmodel_1");
// general simulation environment settings
$temp(85);
}
// End of User Baseline //
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The functions used to create the User Baseline
are standard AMPLE functions. A description of
available AMPLE functions can be found in the
Pyxis Schematic Reference Manual For The
Pyxis Custom Design Platform, v10.2. Refer to
the Function Dictionary chapter.
Lines 5-6,16 specify that:
IF the user selects the Eldo simulator in the New
Configuration form, THEN the enclosed AMPLE
functions are applied to the Design
Configuration.
Lines 8-11 define Eldo specific arguments and
options.
Lines 14-15 define general simulation settings.
Typically, the User Baseline includes many more
settings; this example only has 2.
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Lines 20-21,31 specify that:
IF the user selects the ADMS simulator in the
New Configuration form, THEN the enclosed
AMPLE functions are applied to the Design
Configuration.
Simulator specific baseline definitions often
duplicate the same general simulation settings.
The user may choose to duplicate these settings
in each Eldo, ADMS, and ADiT baseline
definition. However, there is an easier method.
Line 22 invokes the $eldo_user_baseline
function (lines 5-16) from within the
$adms_user_baseline function. Note: This must
precede the other ADMS baseline definitions.
Now, when the ADMS simulator is selected for a
new configuration, the Eldo simulation settings
are first applied to the Design Configuration.
Then the remaining ADMS simulation settings
are applied.
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Lines 26-27 define ADMS specific arguments.
Note that these lines are commented out,
because they are not used in this tutorial.
Line 30 defines that ADMS simulations use a
temperature value of 85C. This overrides the
Eldo temperature value of 27Cthat had been
set by line 22.
This example is complete.
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Summary
The following concepts were demonstrated in this section:
The User Baseline is created by adding AMPLE functions to the daic_sim_mgr.ample file.
This file is saved in the $AMPLE_PATH / da_ic directory.
The available AMPLE commands are documented in the Pyxis Schematic Reference
Manual For The Pyxis Custom Design Platform, v10.2, Function Dictionary chapter.
A unique User Baseline may be defined for each type of simulator the user may select
(Eldo, ADMS, ADiT).
Typically, a simulator specific baseline definition contains simulator specific arguments and
options; followed by general purpose (simulator agnostic) simulation settings.
Simulator specific baselines can be invoked within other simulator specific baselines. This
allows the user to avoid duplicating the general purpose simulation settings.
94
Example: Create A New Configuration
VCO Test
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Create A New Configuration: VCO Test
In this example, we will demonstrate how to create a new configuration, named vco_test. This
configuration will contain state snapshots. These snapshots allow the user to initialize the
Design Configuration for various re-usable VCO (Voltage Controlled Oscillator) tests.
We begin by requesting a new configuration and selecting a simulator [C]. This will initialize the
Design Configuration with the contents of the baseline [B]. Next, we will edit the Design
Configuration to add parameters, and define stimuli [A].
Finally, we will exit Simulation Mode [D]. This will automatically create the vco_test
configuration [F] and store a snapshot of the current simulation settings as the default state [E].
C
B
A
D
E
F
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The figure on the left shows an overview of
the tasks performed in this example.
Creating the vco_test configuration requires
7 tasks:
1. Request a new configuration and select
a simulator type.
2. Edit the netlister settings.
3. Select model languages.
4. Add global parameters.
5. Define stimuli on nets.
Continued on next page.
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Overview continued
6. Copy transcript text to script template
file (optional).
7. Exit Simulation Mode.
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Task 1: Request a new configuration
and select a simulator type.
1. In the Project Navigator window,
navigate to the GenericPLL /
Simulations / vco / sim_vco
directory [D].
2. Double LMB the schematic folder [A].
This will invoke Pyxis Schematic [C]
and open the sim_vco schematic [E].
The particular buttons displayed in the
toolbar [F] indicate that Pyxis Schematic is
currently in Schematic Mode.
3. Optional: minimize the Project
Navigator window [B].
D
A
C
B
E
F
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Task 1: continued
4. In the Pyxis Schematic window, LMB the
Enter Simulation Mode
*
button [G]. This
will open the Entering Simulation Mode
form [A].
5. LMB the New Design Configuration button
[B]. This will open the New Design
Configuration form [D].
6. Enter the name of the new configuration
in the Name field [C]. In this example, the
configuration is named vco_test. The
vco_test configuration will include various
VCO simulation settings.
7. LMB the Eldo radio button [E]. This selects
the default simulator associated with the
vco_test configuration.
8. LMB the OK button [F]. This closes the
New Design Configuration form [D].
A
B
D
C
F
G
E
* Hotkey = s
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Task 1: continued
9. The vco_test configuration is now
displayed in the Design Configuration list
[B].
10. LMB the OK button [C]. This closes the
Entering Simulation Mode form [A]. The
baseline settings are automatically loaded
into the Design Configuration.
At this point, Pyxis Schematic is in Simulation
Mode; and the Design Configuration has been
initialized. Note that the toolbar changes to
Simulation Mode buttons [D].
Task 1 is complete.
B
C
A
D
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Task 2: Setup the simulation
environment.
1. LMB the Setup Environment
*
button
[A]. This will open the Setup
Environment form [C].
2. LMB the Netlister Panel [D]. This will
display the Netlister Argument
Switches [B].
3. LMB the global argument switch [E].
This switch defines the global nets.
4. Enter the names of the global nets in
the Value field [F]. In this example, the
vdd_diff and vss_diff nets are defined
as global simulation nets.
5. LMB the OK button [G]. This applies
the simulation environment settings to
the Design Configuration and closes
the Setup Environment form [C].
At this point, the simulation environment is
defined. Task 2 is complete.
A
C
D
E
F
B
G
* Hotkey = s
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Task 3: Select model languages.
1. LMB the Hierarchy Navigator button [E].
This will open the Hierarchy Navigator
panel [A]. Note that the prescaler instance
is currently using Verilog
language
models [C], and the vco instance is using
Verilog
-A language models. In this

example, we will use schematic models.
2. LMB the prescaler instance name [B] to
select it. Shift-LMB the vco instance name
[F] to add it to the selection.
3. RMB to display the cascading menu. LMB
the Change Model menu button [D] to
display the next cascading menu. LMB the
SCHEMATICmenu button [G].
E
A
C
B
F
D
G
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Task 3: continued
4. Note that the language model for both
instances is now SCHEMATIC[B].
5. Note that both schematic instances are
now SCHEMATIC[C, D].
6. Optional: close the Hierarchy Navigator
panel [A].
At this point, all the VCO simulation models
use the schematic. Task 3 is complete.
B
A
C
D
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Task 4: Add global parameters.
1. LMB the Setup Simulation
*
button [B].
This will open the Setup Simulation
form [A].
2. LMB the Params/Sweeps panel [C].
This panel is used to define various
simulation parameters, sweep
parameter ranges, and Monte Carlo
runs.
Note that the nominal Temperature
parameter [D] is currently defined as
27 degrees. This initial value was set by
the User Baseline line 14. Refer to
example Create The User Baseline.
<link>
B
A
C
D
* Hotkey = g
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Task 4: continued
3. LMB the Global radio button [A]. This
sets the scope of the simulation
parameters we will define in the
following steps.
4. LMB the Parameter field [B]. Enter the
positive supply voltage name VDD. LMB
the Value field [C]. Enter the parameter
value of 1. LMB the Add button [E].
Note that the summary table [D] shows
that the VDDglobal parameter has a
nominal value of 1.
5. LMB the Parameter field [B]. Enter the
negative supply voltage name VSS.
LMB the Value field [C]. Enter the
parameter value of 0. LMB the Add
button [E]. Note that the summary
table [D] shows that the VSS global
parameter has a nominal value of 0.
A
B C
E
D
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Task 4: continued
6. LMB the Parameter field [A]. Enter the
control voltage name CNTRL. LMB the
Value field [B]. Enter the parameter
value of 0.5. LMB the Add button [D].
Note that the summary table [C] shows
that the CNTRL global parameter has a
nominal value of 0.5.
VCO bias current name IBIAS_VCO. LMB
the Value field [B]. Enter the parameter
value of -800u. LMB the Add button [D].
Note that the summary table [C] shows
that the IBIAS_VCO global parameter
has a nominal value of -800u.
prescaler bias current name IBIAS_PRE.
LMB the Value field [B]. Enter the
parameter value of -1.5m. LMB the Add
button [D]. Note that the summary table
[C] shows that the IBIAS_PRE global
parameter has a nominal value of
-1.5m.
B
D
A
Task 4 is complete.
C
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Task 5: Define stimuli.
1. LMB the Forces panel [B]. This panel is
used to define stimuli sources for target
nets in the Pyxis Schematic window
[A].
Tip: Position the Setup Simulation form
as shown [C]. This will allow you to
easily switch between the two displays
as you select nets.
B
C
A
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Task 5: continued
2. In the Pyxis Schematic window, LMB
the vctrl_vco net [A]. Note that the net
name is displayed in the Selection from
Schematic list [B].
3. LMB the DC source in the Source Type
list [C]. Enter the string{CNTRL}into
the Magnitude (V/A) field [D].
4. Verify that GROUNDis selected in the
Reference field [E]. Verify that the
Voltage radio button is selected [F].
5. LMB the Add button [G]. The source
definition is now displayed in the
summary table [H].
At this point, the vctrl_vco net will be
driven by a DC voltage source referenced to
GROUND. The magnitude of the voltage
source is specified by the CNTRL parameter
defined in Task 4: step 6. <link>
A
B
C
D
E
F
G
H
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Task 5: continued
the PDbar net [A]. Note that the net
name is displayed in the Selection from
Schematic list [B].
list [C]. Enter the string{VDD}into the
Magnitude (V/A) field [D].
Reference field [E]. Verify that the
Voltage radio button is selected [F].
9. LMB the Add button [G]. The source
summary table [H].
At this point, the PDbar net will be driven
by a DC voltage source referenced to
source is specified by the VDD parameter
B
C
F
G
H
A
D
E
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Task 5: continued
the ibias_vco net [E]. Shift-LMB the
vdd_diff net [A]. Note that both net
names are displayed in the Selection
from Schematic list [B].
list [C]. Enter the string{IBIAS_VCO}
into the Magnitude (V/A) field [D].
12. LMB the VDD_DIFF signal [G] in the
Selection from Schematic list [B]. LMB
the Fill from Signals button [H]. Note
that /vdd_diff is now displayed in the
Reference field [I].
13. LMB the Current radio button [J ].
14. LMB the IBIAS_VCO signal [F] in the
Selection from Schematic list [B].
15. LMB the Add button [K]. The source
summary table [L].
G
C
I
L
D
A
E
B
H
J
K
F
At this point, the ibias_vco net is driven by a DC current
source referenced to vdd_diff. The magnitude of the
current source is specified by the IBIAS_VCO parameter
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Task 5: continued
the ibias_pre net [E]. Shift-LMB the
vdd_diff net [A]. Note that both net
from Schematic list [B].
list [C]. Enter the string{IBIAS_PRE}
into the Magnitude (V/A) field [D].
18. LMB the VDD_DIFF signal [G] in the
Selection from Schematic list [B]. LMB
the Fill from Signals button [H]. Note
that /vdd_diff is now displayed in the
Reference field [I].
19. Verify that the Current radio button [J ]
is selected.
20. LMB the IBIAS_PRE signal [F] in the
Selection from Schematic list [B].
21. LMB the Add button [K]. The source
summary table [L].
G
C
I
L
D
A
E
B
H J
K
F
At this point, the ibias_pre net is driven by a DC current
source referenced to vdd_diff. The magnitude of the
current source is specified by the IBIAS_PRE parameter
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Task 5: continued
22. In the Pyxis Schematic window, LMB-
drag to select both vdd_diff and
vss_diff nets [A]. Note that the net
from Schematic list [C].
list [D]. Enter the string{VDD}into the
Magnitude (V/A) field [E].
24. Select GROUNDin the Reference list
[G]. LMB the Voltage radio button [H].
25. LMB the VDD_DIFF signal [B] in the
Selection from Schematic list [C].
26. LMB the Add button [I]. The source
summary table [F].
D
H
F
E
G
At this point, the vdd_diff net is driven by a DC voltage
source referenced to GROUND. The magnitude of the
voltage source is specified by the VDD parameter defined
in Task 4: step 4. <link>
A
C
B
I
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Task 5: continued
27. LMB the VSS_DIFF signal name [A] in
the Selection from Schematic list [B].
list [C]. Enter the string{VSS}into the
Magnitude (V/A) field [D].
Reference field [F]. Verify that the
Voltage radio button [G] is selected.
30. LMB the Add button [H]. The source
summary table [E].
At this point, the vss_diff net is driven by a
DC voltage source referenced to GROUND.
The magnitude of the voltage source is
specified by the VSS parameter defined in
Task 4: step 5. <link>
C
G
E
D
F
B
H
A
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Task 5: continued
31. Verify that the summary table [A]
appears as shown.
32. LMB the Apply button [B]. This will
apply all the parameter and stimuli
definitions defined in Task 4 and Task 5
to the Design Configuration.
Note that the source definitions
[C, D, E] now appear next to their
associated nets in the Pyxis Schematic
window.
33. Minimize the Setup Simulation form
(optional).
At this point, the VCO simulation
parameters and sources are defined.
Task 5 is complete.
A
B
C
D
E
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Task 6: Copy transcript text to script
template file (optional).
IF the Transcript Area is not currently
visible at the bottom of the Pyxis Schematic
window [A], THEN:
1. LMB the Setup [B] cascade pull-down
menu.
2. LMB the Windows [C] cascade menu
item.
3. LMB the Transcript Area [D] menu
item.
The Transcript Area should now be
displayed at the bottom of the Pyxis
Schematic window [A].
B
C
D
A
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Task 6: continued
4. Create a new template file using a text
editor. The file will contain AMPLE
commands. Therefore, the file
extension must be ample. In this
tutorial, the new file is named
script_templates.ample [B].
5. Copy blocks of useful commands in the
Transcript Area [A], and paste them
into the script_templates.ample file
[B].
6. Create a directory $SPT_HOME/scripts.
Save the script_templates.ample file in
the scripts directory.
At this point, blocks of AMPLE commands
have been saved in a template file. These
commands can be used to re-create the
steps performed in Tasks 2-5.
Task 6 is complete.
A
B
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Task 7: Exit Simulation Mode.
1. LMB the Exit Simulation Mode
button [E]. When the Query window is
displayed, LMB the Yes button [C]. This
will cause an automatic sequence of
events to occur:
The vco_test configuration will be
created in the Design Configuration
Database.
A snapshot of the Design Configuration
will be saved as state default.
The Setup Simulation form will close.
The design viewpoint [A] is replaced by
the schematic [B].
The side toolbar menu changes from
simulation buttons to schematic
buttons [D].
Task 7 is complete. This example is
complete.
E
C
D
A
B
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Summary
The following concepts were demonstrated in this example:
A new configuration named vco_test was created using the New Design Configuration form.
Netlister global arguments were defined using the Setup Environment form.
Simulation language models were specified using the Hierarchy panel.
Global parameters were defined using the Params/Sweeps panel.
Net driving sources were defined using the Forces panel.
AMPLE commands were copied from the Transcript Area and pasted into a script template file.
A state snapshot named default was automatically saved when the user exited Simulation Mode.
119
Example: Create A New State
Optimum VCO Bias
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Create A New State: Optimum VCO Bias
In this example, we will demonstrate how to create a new state snapshot, named
bias_setup. This snapshot will allow the user to initialize the Design Configuration at the
optimum VCO bias point at any time in the future.
We begin by selecting the vco_test configuration [D]. This will automatically load the default
state [E] into the Design Configuration . This restores the parameter and source definitions
to their previous settings at t
exit
[A].
Next, we run an Eldo simulation while sweeping the vdd_diff and ibias_vco parameters [B].
The optimum parameter values are determined from the simulation results.
Finally, we set the vdd_diff and ibias_vco parameters to their optimal values [C]. Then we
save [F] the current Design Configuration as a new state, named bias_setup [G].
E
A
B
C
F
D
G
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Optimizing the bias settings requires 8
tasks:
1. Load an existing configuration.
2. Run an initial DC operating point
simulation. Evaluate the results.
3. Modify the simulation settings to use
sweep parameters.
4. Run a DC sweep simulation and
evaluate the results using EZwave.
Determine the optimum bias voltage
and current values.
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Overview continued
the optimum bias voltage and current
values.
6. Save the simulation settings as a new
state, named bias_setup.
file (optional).
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Task 1: Load an existing
configuration.
IF the sim_vco schematic is currently
closed, THEN do steps 1, 2, and 3.
directory [D].
This will invoke Pyxis Schematic and
open the sim_vco schematic [C].
D
A
C
B
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Task 1: continued
4. LMB the Enter Simulation Mode
*
button [E].
This will open the Entering Simulation Mode
form [A].
5. LMB select the vco_test configuration [B] that
was created in the previous example.
Note that the default simulator is Eldo [C]. This
simulator selection was made when the vco_test
configuration was created. <link>The user may
choose to override the default simulator selection
by LMB one of the Simulator type [D] radio
buttons. We will continue to use the Eldo
simulator in this example.
6. LMB the OK button [F]. This will close the
default state snapshot will be loaded into the
Design Configuration.
At this point, the simulation settings have been
restored to the time the user previously exited
the vco_test configuration.
Task 1 is complete.
E
A
B C
D
F
* Hotkey = s
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VCO Design Constraints.
The circuit designer specifies the following
constraints for this VCO design:
The pbias voltage [B] must be 500 mV
to 600 mV in order for the VCO to
oscillate.
The nbias voltage [D] must be 600 mV
to 700 mV in order for the VCO to
oscillate.
The pbias [B] and nbias [D] voltages
are sensitive to changes in vdd_diff
voltage [A]. The acceptable range of
vdd_diff voltage is 1.0 V to 1.4 V.
The pbias [B] and nbias [D] voltages
are determined by the current on the
Ibias_vco pin [C]. The acceptable
range of Ibias_vco current is -800 uA to
-1.5 mA.
A
B
C
D
The figure shown above is for reference purposes.
It is not displayed in the Pyxis Schematic GUI at this time.
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Task 2: Run an initial DC operating
point simulation.
1. LMB the Setup Simulation button [A].
form [E].
2. LMB the Analysis Simulation Panel [B].
3. Verify that OP [C] is the only analysis
type checked in the Analysis Selector
list. Verify that Enable DCOP [D] is
checked. If any changes are made,
then LMB the Apply button.
4. Optional: minimize the Simulation
Setup form [E].
At this point, we have verified that the
simulator is setup to run a DC operating
point analysis.
5. LMB the Run Simulator
*
button [F].
This will start the DC operating point
analysis.
B
A
C
D
E
F
* Hotkey = r
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Task 2: continued
When the simulation is complete, the Log
tab [E] will be displayed at the bottom of
the Pyxis Schematic window.
7. LMB the Log tab [E]. This will open the
Log Area [A].
8. Scroll the Log Area to verify that the
simulation terminated normally [B].
9. Scroll the Log Area to verify that there
are no fatal errors [D].
10. Optional: hide the Log Area [C].
D
E
B
A
C
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Task 2: continued
To inspect the voltages on the pbias and
nbias nets; we must descend a level of
hierarchy into the VCO schematic.
11. In the Pyxis Schematic window, double
LMB
*
the VCO instance [A]. This will
open a new tab containing the VCO
schematic [B].
A
B
* Stroke = select + MMB downward stroke
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Task 2: continued
12. Zoom in on the left side of the VCO
schematic [A]. The vco_bias block is
the source of the pbias and nbias nets.
13. LMB select the pbias net [B]. Shift-LMB
the nbias net [E] to add to the
selection.
14. LMB the DCOP/Transient button [C] to
display the cascading menu. LMB the
Add Monitors On Selection button [D].
The pbias and nbias nets will un-select.
Note: The new monitors might or might not
appear in the schematic window. This is
normal behavior. As we will see in the next
slide; the monitors have been added to the
nets.
A
E
B
D
C
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Task 2: continued
15. Pan and zoom along the pbias and
nbias nets until you locate the monitors
[A, C]. In this example, the monitors
are attached near DIFF_BUFFER3 [B].
16. Examine the pbias voltage [A]. Using
the existing simulation settings, the
pbias voltage is 383.18 mV. This does
not meet the 500 mV to 600 mV design
constraint.
17. Examine the nbias voltage [C]. Using
the existing simulation settings, the
nbias voltage is 560.14 mV. This does
not meet the 600 mV to 700 mV design
constraint.
Task 2 is complete.
In the next task, the simulation settings will
be modified to meet the VCO design
constraints.
B
A
C
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Task 3: Modify the simulation settings
to use swept parameters.
We will use a nested parameter sweep of
ibias_vco and vdd_diff to determine the
optimum bias voltage and current.
1. LMB the Setup Simulation button [A].
form [B].
2. LMB the Analysis [C] Simulation Panel.
3. LMB check the DC [D] Analysis Selector
checkbox.
4. Select Source (Force) [E] in the first
level Sweep Type pull-down list.
5. LMB the cross-hair button [G]. This will
open the Force Selection form [F].
6. LMB the FORCE__ibias_vco instance
[H] entry. LMB the OK button [I]. This
will close the Force Selection form [F].
B
A
D
C
E
G
F
H
I
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Task 3: continued
Note that the FORCE__ibias_vco instance
name appears in the first sweep level field
[A].
7. Enter the value -800u in the Start
field [B]. This is the upper ibias_vco
design constraint.
8. Enter the value -1.5m in the Stop
field [C]. This is the lower ibias_vco
design constraint.
9. Enter the value -100u in the Step
field [D].
At this point, the DC current source driving
the ibias_vco net is specified to sweep from
-800 uA to -1.5 mA in steps of -100 uA.
This will cover the entire range of valid
ibias_vco design constraint values. The
sweep will include 8 current points.
A B C D
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Task 3: continued
10. Select Source (Force) [A] in the second
level Sweep Type pull-down list.
11. LMB the cross-hair button [C]. This will
open the Force Selection form [B].
12. LMB the FORCE__vdd_diff instance [D]
entry. LMB the OK button [E]. This will
close the Force Selection form [B].
B
A
D
C
E
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Task 3: continued
Note that the FORCE__vdd_diff instance
name appears in the second sweep level
field [A].
13. Enter the value 1.0 in the Start
field [B]. This is the lower vdd_diff
design constraint.
14. Enter the value 1.4 in the Stop
field [C]. This is the upper vdd_diff
design constraint.
15. Enter the value 0.2 in the Step
field [D].
16. LMB the Apply button [E]. This applies
the simulation settings to the Design
Configuration.
At this point, the DC voltage source driving
the vdd_diff net is specified to sweep from
1.0 V to 1.4 V in steps of 0.2 V. This will
cover the entire range of valid vdd_diff
design constraint values in 3 voltage curves.
Task 3 is complete.
A B C D
E
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Task 4: Run a sweep simulation and
determine optimum values.
*
button [A].
This will start the DC sweep analysis.
When the simulation is complete, the
Log tab [E] will be displayed at the
bottom of the Pyxis Schematic window.
Log Area [B].
simulation terminated normally [C].
5. Optional: hide the Log Area.
* Hotkey = r
B
A
E
C
D
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Task 4: continued
6. LMB the /VCO1 vco tab [A]. This will
display the VCO schematic. Zoom in on
the left side of the VCO schematic [B].
7. LMB select the pbias net [C]. Type the
x hotkey to add an EZwave cross-
probe. This will also open the EZwave
window [D].
B
A
C
D
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Task 4: continued
The simulation results show 3 curves
[E, F, G]. Each curve represents a step of
the force_vdd_diff sweep. You can display
the parameter value by hovering the cursor
over a curve.
The red
*
curve [E] corresponds to
FORCE_vdd_diff =1.4 V.
The green curve [F] corresponds to
The blue curve [G] corresponds to
The vertical axis [B] corresponds to the
voltage on the pbias net (the cross-probe).
The horizontal axis [H] represents the
sweep of the FORCE_ibias_vco parameter.
B
E
F
G
Tip: To change the color, visibility, and properties of a curve:
1. LMB select the curve.
2. RMB to display the pop-up menu [A].
3. LMB the Properties item [C] to display the
Waveform Properties form [D].
H
A
C
D
* Note: The colors shown on your display are
determined by your preference settings and
previous simulation runs. Therefore, the
colors on your display may be different than
the colors shown in the figure.
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Task 4: continued
8. LMB the Cursor [A] pull-down menu.
LMB the Add Horizontal Cursor item
[B]. This will add a horizontal cursor to
the Wave Window. Drag the cursor to
the maximum pbias voltage [D] design
constraint (600 mV).
9. LMB the Cursor [A] pull-down menu.
LMB the Add Horizontal Cursor item
[B]. This will add a 2
nd
horizontal cursor
to the Wave Window. Drag the cursor
to the minimum pbias voltage [E]
design constraint (500 mV).
Note that the vdd_diff 1.20 V curve [C] is
the only curve that intersects the pbias
voltage design constraint of 500 to 600 mV.
Therefore, the optimum value of vdd_diff is
1.2 V.
The other two curves cannot be considered,
because they do not meet the design
constraints. Optional: hide the 1.0 V and
1.4 V curves.
C
A
D
B
E
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Task 4: continued
10. In the /VCO1 VCO schematic [A], LMB
select the nbias net [B]. Type the x
hotkey to add an EZwave cross-probe.
This will also add a new set of curves
[C, D, E] to the EZwave window.
The red
*
curve [C] corresponds to
The green curve [D] corresponds to
The blue curve [E] corresponds to
The vertical axis [F] corresponds to the
voltage on the nbias net (the cross-probe).
Since we already know the optimum
vdd_diff value is 1.2 V, the red curve [C]
and blue curve [E] may be hidden to reduce
clutter.
A
C
B
F
D
E
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Task 4: continued
11. LMB select the vdd_diff 1.2 V curve
[D]. RMB to open the pop-up menu
[C].
12. LMB the Add Horizontal Cursor item
[E]. LMB-drag the cursor to the
maximum nbias voltage [A] design
13. LMB select the vdd_diff 1.2 V curve
[D]. RMB to open the pop-up menu
[C].
14. LMB the Add Horizontal Cursor item
[E]. LMB-drag the cursor to the
minimum nbias voltage [B] design
B
C
D
A
E
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Task 4: continued
15. LMB the Add Cursor button [A]. LMB-
drag the cursor [B] to the right, until
both pbias and nbias voltages meet
their design constraints. At this point,
the pbias voltage is 500 mV [C] and the
nbias voltage is 616 mV.
Note that the ibias_vco value [E] is
-1.32 mA. This is the ibias_vco lower limit.
16. LMB-drag the cursor [B] to the right,
until either pbias or nbias voltages
violate their design constraints. At this
point, the pbias voltage is 522 mV and
the nbias voltage is 600 mV [D].
Note that the ibias_vco value [F] is
-1.19 mA. This is the ibias_vco upper limit.
C
B
A
D
F
E
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Task 4: continued
The pbias and nbias voltage design
constraints can only be satisfied
simultaneously if the value of ibias_vco is
between -1.32 mA and -1.19 mA. We will
select an ibias_vco value of -1.25 mA in the
center of this range.
We have now determined that the optimum
VCO bias point is:
vdd_diff = 1.20 V [B, C]
ibias_vco = -1.25 mA [E]
At the optimum bias point, the pbias
voltage [A] is 512 mV, and the nbias
voltage [D] is 607 mV. Both design
constraints are met.
17. Optional: minimize the EZwave window.
Task 4 is complete.
E
C
B
D
A
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Task 5: Set the simulation settings to
the optimum bias values.
In the previous task, we determined that
the optimum value of vdd_diff is 1.20 V;
and the optimum value of ibias_vco is
-1.25 mA. <link>In this task, we will set
the simulation settings to these values.
1. Restore the Setup Simulation form [B].
2. In the Analysis panel [C], LMB
un-check the Enable DC checkbox [A].
The DC Analysis Selector [D] will be
disabled.
3. LMB the Params/Sweeps panel [E].
B
A
C
D
E
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Task 5: continued
4. LMB the row containing the IBIAS_VCO
parameter [E]. Note that the selected
parameter name is displayed in the
Parameter field [A].
5. Enter the optimum IBIAS_VCOvalue of
-1.25m in the Value field [B].
6. LMB the Update button [C]. Note that
the new IBIAS_VCOvalue is displayed
in the IBIAS_VCOrow [D].
E
D
C
A B
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Task 5: continued
7. LMB the row containing the VDD
parameter [E]. Note that the selected
parameter name is displayed in the
Parameter field [A].
8. Enter the optimum VDD value of 1.2 in
the Value field [B].
9. LMB the Update button [C]. Note that
the new VDD value is displayed in the
VDD row [D].
10. LMB the Apply button [F]. This will
apply the optimum bias settings to the
11. Optional: hide the Setup Simulation
form.
The Design Configuration is now set at the
optimum bias point.
Task 5 is complete.
E
D
C
F
A B
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Task 6: Save the simulation settings
as a new state.
In the previous task, we set the VDDand
IBIAS_VCOparameters to their optimum
values. In this task, we will save the
simulation settings as a new state in the
the File pull-down menu [A].
2. LMB select the Save State item [B].
This will open the Save State form [C].
3. Enter the name of the new state into
the Name field [D]. In this example,
the new state is named bias_setup.
4. LMB the OK button [E]. This will take a
snapshot of the current simulation
settings and save it within the vco_test
configuration.
Whenever the user loads the bias_setup
state, the VCO will return to its optimum
bias settings. Task 6 is complete.
A
D
B
E
C
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1. Open the script_templates.ample file in
the $SPT_HOME/scripts directory.
[B].
3. Save the script_templates.ample file.
have been saved in the template file. These
Task 7 is complete.
A
B
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button [D]. This will cause an
automatic sequence of events to occur:
saved in the Design Configuration
Database. The vco_test configuration
contains the new bias_setup state and
the default state.
the schematic [B].
buttons [C].
complete.
D
C
A
B
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Summary
An existing configuration named vco_test was opened using the Entering Simulation form. The
default state was automatically loaded, restoring the previous simulation settings.
A DC operating point simulation was run. Monitors were added to determine the voltage values of
the pbias and nbias nets.
The simulation settings were changed to sweep parameters using the Analysis panel.
A sweep DC simulation was run. Optimum parameter values were graphically determined using
EZwave cross-probes.
Optimal parameter values were defined using the Params/Sweeps panel.
The Design Configuration with the optimal parameter settings was saved as a new state using the
Save State form.
A state snapshot automatically over-wrote the existing default state when the user exited Simulation
Mode.
150
Frequency Measurement
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Create A New State: Frequency Measurement
In the previous example, we learned how to save test bench stimuli definitions as a state
snapshot. In this example we will demonstrate how to save test bench measurement
definitions as a new state snapshot. This snapshot will allow the user to measure the VCO
frequency at any time in the future.
We begin by selecting the vco_test configuration [D] and loading the bias_setup state [E].
This restores the vdd_diff and ibias_vco test bench stimuli to their optimal values [A].
Next, we re-define the vctrl_vco constant parameter as a sweep parameter [B]. Then, we
define a frequency measurement for the CLK1P output [C].
Finally, we save [F] the current Design Configuration as a new state, named freq_meas [G].
D
E
A C
F
G
B
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Creating the freq_meas state requires 11
tasks:
1. Load the existing vco_test
configuration.
2. Load the existing bias_setup state.
sweep parameters.
4. Modify the simulation settings for
transient analysis.
5. Define the frequency measurement.
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Overview continued
6. Set initial conditions.
7. Run a transient simulation.
8. Examine the simulation results using
the AMS Results Browser.
9. Save the current simulation settings as
a new state.
file (optional).
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configuration.
directory [D].
D
A
C
B
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Task 1: continued
*
button [E].
form [A].
5. LMB select the vco_test configuration [B].
configuration was created. The user may choose
to override the default simulator selection by LMB
one of the Simulator type [D] radio buttons. We
will continue to use the Eldo simulator in this
example.
default state snapshot contained within the
vco_test configuration will be loaded into the
Task 1 is complete.
E
A
B C
D
F
* Hotkey = s
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Task 2: Load an existing state.
1. LMB the File pull-down menu [A].
2. LMB the Load State item [D]. This will open
the Load State form [C].
3. LMB select the bias_setup state [B] from the
Available States list.
4. Verify that all the check-boxes are checked in
the What to load [E] area.
Load State form [C]. The bias_setup
simulation settings will be applied to the
Design Configuration in the Unsaved Session.
restored to the optimum VCO bias values.
Task 2 is complete.
B
C
A
D
E
F
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Task 3: Modify simulation settings to
sweep a parameter.
1. LMB the Setup Simulation button
*
[A].
form [D].
2. LMB the Params/Sweeps Simulation
Panel [C].
Note that the VDDparameter value [E] is
1.2. This is the optimal value loaded from
the bias_setup state.
Note that the IBIAS_VCOparameter value
[F] is -1.25m. This is the optimal value
loaded from the bias_setup state.
Note that 6 Forces are currently defined
[B]. These definitions were loaded from the
bias_setup state.
* Hotkey = g
A
D
B
C
E
F
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Task 3: continued
To measure the VCO output frequency
across a range of settings; we will sweep
the CNTRL parameter from 50% to 80%
VDDand record the simulation results.
3. LMB select the row containing the
CNTRL parameter [H].
4. LMB check the Sweeps Enabled
checkbox [B]. LMB the Range radio
button [A]. This will display sweep
parameter fields [C, D, E, F].
5. LMB select the Increment value in the
Range drop-down list [C]. This defines
the sweep parameter to increment by a
fixed amount for each simulation step.
6. Enter the value {VDD/2}in the Start
field [D]. Enter the value {VDD*0.8}in
the Stop field [E]. Enter the value
{VDD/20}in the Increment by field [F].
7. LMB the Update button [G].
Task 3 is complete.
H
B
A
G
C D E F
At this point, the CNTRL parameter is no longer a constant
value of 0.5; it is now a sweep of values. The sweep
starts at 50% VDDand increments by 5% VDDeach
simulation step. The sweep stops at 80% VDD.
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Task 4: Modify simulation settings to
use transient analysis.
1. LMB the Analysis Simulation Panel [A].
2. Verify that the DC Analysis Selector
checkbox [B] is not checked.
3. LMB check the TRAN Analysis Selector
checkbox [C]. Verify that the Enable
TRAN checkbox [D] is checked.
4. Enter the value 100n into the Stop
Time field [E]. This will end the
transient simulation at 100 nSec.
At this point, the simulator is configured to
run a transient simulation for 100 nSec.
Task 4 is complete.
E
C
A
B
D
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Task 5: Define the frequency
measurement.
select the CLK1P output net [A].
2. In the Setup Simulation form, LMB
select the Measures Simulation Panel
[B].
Note that the CLK1P net name is displayed
in the Selection from Schematic list [C].
B
A
C
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Task 5: continued
3. LMB select the TRAN value in the
Analysis drop-down list [A]. This limits
the measurement to transient analyses.
4. LMB select the Wfreq value in the
Function drop-down list [B]. This
specifies that the function applied to
the measurement will be frequency
calculation.
5. LMB select the Voltage value in the
Measure drop-down list [C]. This
specifies that voltage on the CLK1P net
will be measured.
6. Enter the value 20n into the start field
[D]. This specifies that the
measurement will start 20 nSec after
the transient simulation begins. The
VCO output should be stable by this
time.
D
C
A
B
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Task 5: continued
7. Enter the text END into the end field
[B]. This Eldo keyword specifies that
the measurement will stop when the
transient simulation stops.
8. Optional: enter the text
WFREQ__TRAN___CLK1P into the
Label field [A]. This specifies the name
of the CLK1P frequency measurement.
9. LMB the Add button [C]. This will add
the CLK1P frequency measurement to
the table of measurements [D].
10. LMB the Apply button [E]. This applies
the sweep parameter definitions,
transient analysis settings, and
measurement definition to the Design
Configuration in the Unsaved Session.
11. Optional: hide the Simulation Setup
form.
Task 5 is complete.
E
B
C
D
A
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Task 6: Set initial conditions.
For the VCO to oscillate correctly, the phase
of the CLK1P and CLK1Mnets must be
initialized.
select the CLK1P net [C].
2. LMB the Set Initial Condition button
[A]. This will open the Set Initial
Condition form [B].
3. LMB select the Hold Node Voltage
Throughout DCOP (.IC) radio button
[D].
4. Enter the value 0 into the Voltage value
field [E].
5. LMB the OK button [F]. The Set Initial
Condition form [B] will close. The
CLK1P initial condition will be applied to
the Design Configuration.
At this point, the CLK1P net will be held at
0 Volts throughout the DCOP calculation.
E
B
D
C
A
F
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Task 6: continued
6. LMB select the CLK1Mnet [C].
7. LMB the Set Initial Condition button
[A]. This will open the Set Initial
Condition form [B].
8. LMB select the Hold Node Voltage
Throughout DCOP (.IC) radio button
[D].
9. Enter the value of 1 into the Voltage
value field [E].
10. LMB the OK button [F]. The Set Initial
Condition form [B] will close. The
CLK1M initial condition will be applied
to the Design Configuration.
At this point, the CLK1Mnet will be held at
1 Volt throughout the DCOP calculation.
Note that the CLK1P and CLK1Mnets each
have initial condition markers [G].
Task 6 is complete.
E
B
D
A
F
C
G
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Task 7: Run a transient simulation.
*
button [A].
This will start the transient analysis.
Log tab [E] will be displayed at the
Log Area [B].
Task 7 is complete.
* Hotkey = r
E
D
A
C
B
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Task 8: Examine the simulation
results.
In the previous example, we examined the
simulation results by adding cross probes to
the output signals. Then we observed the
simulation results graphically using EZwave.
However, in this example we added
measurements to the output signals (see
Task 5). <link>This allows the simulation
results to be observed numerically.
1. LMB the Show Simulator Measurement
Results button [D]. This will open the
AMS Results Browser [A].
Note that the CNTRL parameter [B] sweeps
from 600 mV (50% VDD) to 960 mV
(80% VDD). The CNTRL parameter causes
the measured CLK1P frequency [C] to vary
from 1.36 GHz to 1.57 GHz.
2. Optional: hide
*
the AMS Results
Browser.
Task 8 is complete.
A
D
B C
* Tip: It is preferable to hide the AMS Results Browser, instead of
closing it. The browser automatically updates after every simulation
run. Leaving the browser open and hidden allows the user to easily
monitor multiple runs.
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as a new state.
The current simulation settings define a
sweep stimulus and frequency
measurement. We will save the simulation
settings as a new state in the vco_test
configuration.
1. LMB the File pull-down menu [A]. LMB
select the Save State item [B]. This will
open the Save State form [D].
the Name field [C]. In this example, the
new state is named freq_meas.
configuration.
Whenever the user loads the freq_meas
state, a sweep stimulus and frequency
measurement will be applied to the VCO.
Task 9 is complete.
A
B
D
E
C
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[B].
Task 10 is complete.
A
B
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contains the new freq_meas state, the
existing bias_setup state, and the
default state.
the schematic [B].
buttons [C].
complete.
D
C
A
B
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Summary
An existing state named bias_setup was loaded using the Load State form. This restored the
optimumvdd_diff and ibias_vco values.
The simulation settings were changed to sweep the CNTRL parameter using the Params/Sweep
panel.
The simulator was configured for transient analysis using the Analysis panel.
Initial conditions on the VCO output nets were defined using the Set Initial Conditions form.
A frequency measurement was defined for the CLK1P net using the Measures panel.
A transient simulation was run for each sweep CNTRL value. A table of CNTRL vs. CLK1P frequency
was examined using the AMS Results Browser.
The Design Configuration with the CNTRL sweep, transient simulation settings, and the CLK1P
measurement definition was saved as a new state using the Save State form.
A state snapshot over-wrote the existing default state when the user exited Simulation Mode.
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Phase Noise Measurement
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Create A New State: Phase Noise Measurement
In this example we will demonstrate how to measure the output phase noise spectrum of a VCO.
The simulation settings will be saved as a new state that will allow the user to measure phase noise
at any time in the future.
We begin by selecting the vco_test configuration [A] and loading the bias_setup state [C]. This
restores the vdd_diff, vctrl_vco, and ibias_vco test bench stimuli to their optimal values [B].
Next, we define a differential phase noise measurement across the CLK1P and CLK1Moutputs [E].
Finally, we save [D] the current Design Configuration as a new state, named phnoise_meas [F].
A
C
D
F
B
E
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Creating the phnoise_meas state requires
10 tasks:
configuration.
2. Load the existing bias_setup state.
steady state oscillator analysis.
4. Define the phase noise measurement.
5. Run a steady state simulation.
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Overview continued
EZwave.
a new state.
file (optional).
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configuration.
directory [D].
D
A
C
B
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Task 1: continued
*
button [E].
form [A].
configuration was created. The user may choose
to override the default simulator selection by LMB
one of the Simulator type [D] radio buttons. We
will continue to use the Eldo simulator in this
example.
Task 1 is complete.
E
A
B C
D
F
* Hotkey = s
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2. LMB the Load State item [B]. This will open
the Load State form [D].
3. LMB select the bias_setup state [C] from the
the What to load area [E].
Load State form [D]. The bias_setup
simulation settings will be applied to the
Design Configuration in the Unsaved Session.
restored to the optimum VCO bias values.
Task 2 is complete.
C
D
A
B
E
F
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Task 3: Modify simulation settings for
SST (steady state) and OSC analysis.
*
[A].
form [D].
Panel [C].
Note that the VDDparameter value [E] is
1.2. This is the optimal valued loaded from
the bias_setup state.
Note that the CNTRL parameter value [F] is
0.5. This is the valued loaded from the
bias_setup state.
Note that the IBIAS_VCOparameter value
[G] is -1.25m. This is the optimal valued
loaded from the bias_setup state.
Note that 6 Forces are currently defined
[B]. These definitions were loaded from the
bias_setup state.
* Hotkey = g
A
D
B
C
F
G
E
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Task 3: continued
3. LMB the Analysis Simulation Panel [A].
4. Verify that the DC [B] and TRAN [C]
Analysis Selector checkboxes are not
checked.
5. LMB check the OSCAnalysis Selector
checkbox [F]. Verify that the SST
checkbox [E] is checked. Verify that the
Enable OSC checkbox [D] is checked.
In the previous example, we determined
that the VCO oscillates at approximately 1.3
GHz when the vctrl_vco value is 0.5 V.
<link>
6. Enter the value 1.3e9 into the Fund
OSC Frequency (Hz) field [G]. This will
set the steady state simulation
fundamental frequency to 1.3 GHz.
7. Enter the value 10 into the
# Harmonics field [H]. This will
calculate the first 10 harmonic results.
C
A
B
D
F
E
G H
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Task 3: continued
8. LMB the Vprobe Net 1 crosshairs button
[B]. The Select Object pop-up [F] and
crosshairs [G] will be displayed in the
Pyxis Schematic window.
select the CLK1P net [E]. The Select
Object pop-up [F] will close. Verify that
the net name /CLK1P is displayed in
the Vprobe Net 1: field [A].
10. LMB the Vprobe Net 2 crosshairs button
[D]. The Select Object pop-up [F] and
crosshairs [G] will be displayed in the
Pyxis Schematic window.
select the CLK1Mnet [E]. The Select
Object pop-up [F] will close. Verify that
the net name /CLK1Mis displayed in
the Vprobe Net 2: field [C].
At this point, a differential probe is defined
for the VCO output. Task 3 is complete.
F
A
B
C
D
E
G
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Task 4: Define the phase noise
measurement.
1. LMB check the SSTNOISE Analysis
Selector checkbox [F]. Verify that
Enable SSTNOISE [A] is checked.
2. LMB the Output 1 crosshairs button
[C]. The Select Object pop-up [H] and
crosshairs [I] will be displayed.
select the CLK1P net [G]. Verify that
the net name /CLK1P is displayed in
the Output 1: field [B].
4. LMB the Output 2 crosshairs button [E].
The Select Object pop-up [H] and
crosshairs [I] will be displayed.
select the CLK1Mnet [G]. Verify that
the net name /CLK1Mis displayed in
the Output 2: field [D]. At this point, a
differential measurement is defined
across the VCO output.
F
B
A
H
G
I
D
C
E
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Task 4: continued
6. The phase noise around the
fundamental frequency is more
pronounced, so we will concentrate on
this region of the noise spectrum. Enter
the value of1 into the Input Harmonic
Index field [A]. Enter the value of 1
into the SST Harmonic Index field [B].
7. LMB check the Plot dB Phase Noise
checkbox [D]. This will plot the phase
noise results in dB.
8. In the x-axis pull-down list, LMB select
FREQ_SPECTRUM[C]. This will
configure the plot to display the
frequency spectrum on the x axis.
A B
C
D
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Task 4: continued
9. Enter the value 1 into the Start Freq
field [A]. This will configure the phase
noise measurement to begin 1 Hz
above the fundamental frequency.
10. Enter the value 100meg into the Stop
Freq field [B]. This will configure the
phase noise measurement to end 100
MHz above the fundamental frequency.
11. LMB select pts/decade [C] in the pull-
down list. Enter the value 1 into the
points field [D]. This will configure the
phase noise measurement to 1 point
per decade from Start Freq to
Stop Freq.
B A C D
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Task 4: continued
12. LMB the Add button [A]. This will add
the phase noise measurement
definition to the summary table [B].
13. LMB the Apply button [C]. The steady
state analysis settings (Task 3) and the
phase noise measurement definitions
(Task 4) are applied to the Design
Task 4 is complete.
C
B
A
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Task 5: Run a steady state oscillator
simulation.
*
button [A].
This will start the steady state oscillator
analysis. When the simulation is
complete, the Log tab [E] will be
Schematic window.
Log Area [B].
Task 5 is complete.
* Hotkey = r
D
B
A
C
E
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Task 6: Examine the simulation results
using EZwave.
1. LMB the Plot Results From Latest Run
button [D]. This will open the EZwave
window[C].
2. In the EZwave window, LMB the File
drop-down menu [A]. LMB select the
Open menu item [B]. This will display
the Open form [E].
3. LMB select the sim_vco_vco_test.swd
results [F]. Note that
sim_vco_vco_test.swd is displayed in
the File Name field [G].
4. LMB the Open button [H].
C
D
A
B
E
F
G
H
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Task 6: continued
5. A Wave window [A] will open showing
the phase noise beginning at the
fundamental frequency plus 1Hz to 100
MHz.
6. LMB the Add Cursor button [B]. LMB-
slide the cursor to the right to view the
phase noise value in dB vs. frequency.
Tip: You can use the tab and shift-tab keys
to jump the cursor from one measurement
result to the next.
Note that the phase noise is 103 dB at the
fundamental frequency + 1 Hz [C].
Note that the phase noise is -125 dB at the
fundamental frequency + 100 MHz [D].
Task 6 is complete.
A
C
D
B
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using the AMS Results Browser.
the View Netlist Log button [B]. In the
cascading menu, LMB select the View
Complete Log item [A]. This will open
the AMS Results Browser [D].
The AMS Results Browser displays a
complete summary of the steady state
simulation. This information is contained
within the sim_vco_vco_test.chi file [C].
2. In the Table of Contents pane [E], LMB
the Steady-state phase noise analysis
entry [F]. This will skip to the start of
the Eldo Steady-State Phase Noise
Analysis section [H].
Note: You can display any one of the 9
phase noise measurements by LMB one of
the frequency entries [G]. In this example,
we skip directly to the fundamental
frequency + 1 Hz measurement results [I].
A
E
B
D
C
I
F
H
G
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Task 7: continued
3. In the AMS Results Browser, ctrl-f to
open the Search form [B].
4. Enter the string TOTAL OUTPUT NOISE
in the Find field [A]. LMB the Find
button [C]. This will skip to the first
instance of the TOTAL OUTPUT NOISE
AND CONTRIBUTION FROM DEVICES
results [D].
This is a list of all devices sorted by the
amount of phase noise they contribute to
the total phase noise. The first instance of
TOTAL OUTPUT NOISE corresponds to
f
0
+1Hz. If you search again, the second
instance corresponds to f
0
+10Hz (etc).
The f
0
+1Hz results show that the total
phase noise is 2.15E+10 [F]. This
corresponds to 103 db in the EZwave plot.
20% of the total phase noise [G] is
generated by X_VCO1 [E] at 4.32E+9 [G]
(96 dB).
D
B
C
G
A
F
E
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Task 7: continued
5. ctrl-f to open the Search form [B].
6. Enter the string CONTRIBUTION FROM
THE in the Find field [A]. LMB the Find
button [D]. This will skip to the first
instance of the CONTRIBUTION FROM
THE HARMONICS results [C].
This is a list of the phase noise contributed
by each harmonic. The negative harmonic
results [E] are a mirror image of the
positive harmonic results [G]. The first
instance of CONTRIBUTION FROM THE
corresponds to f
0
+1Hz. If you search again,
the second instance corresponds to
f
0
+10Hz (etc).
The f
0
+1Hz results show that the
fundamental frequency generates 2.15E+10
[H] phase noise. This corresponds to 103
db in the EZwave plot. The second
harmonic [E] generates the next largest
phase noise at 9.55E+1 [F] (20 dB).
C
B
A
D
F
E
G
H
Task 7 is complete. You may minimize the
AMS Results Browser if you wish.
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as a new state.
The current simulation settings define a
phase noise measurement. We will save the
simulation settings as a new state in the
configuration.
new state is named phnoise_meas.
configuration.
Whenever the user loads the phnoise_meas
state, a phase noise measurement is
applied to the VCO.
Task 8 is complete.
A
B
D
E
C
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[B].
Task 9 is complete.
A
B
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contains the new phnoise_meas state,
and the existing freq_meas,
bias_setup, and default states.
the schematic [B].
buttons [C].
complete.
D
C
A
B
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Summary
An existing state named bias_setup was loaded using the Load State form. This restored the
optimumvdd_diff and ibias_vco values.
The simulator was configured for steady state analysis using the Analysis panel. Simulations were
defined for the fundamental frequency f
0
+1 Hz to f
0
+100MHz.
A phase noise measurement was defined for the differential CLK1P and CLK1Mnets using the
Analysis panel.
A steady state simulation was run and phase noise measurements were recorded from f
0
+1 Hz to
f
0
+100MHz.
The phase noise results were examined as a dB plot using EZwave.
The phase noise results were examined as a log file using the AMS Results Browser.
The Design Configuration with the steady state simulation and phase noise measurement definitions
was saved as a new state using the Save State form.
A state snapshot over-wrote the existing default state, when the user exited Simulation Mode.
195
PVT Corner Verification
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Create A New State: PVT Corner Verification
In this example we will demonstrate how to setup corner specifications to run multiple PVT
simulations. The simulation settings will be saved as a new state that will allow the user to verify
PVT corner functionality at any time in the future.
We begin by selecting the vco_test configuration [A] and loading the freq_meas state [C]. This
restores the vdd_diff, vctrl_vco, and ibias_vco test bench stimuli to their previous values [B]. The
output frequency measurement definition is also restored.
Next, we re-define vctrl_vco as a constant. Then we define vdd_diff and temperature as sweep
parameters [E].
Finally, we save [D] the current Design Configuration as a new state, named pvt_setup [F].
A
C
D
F
B E
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Creating the pvt_setup state requires 11
tasks:
configuration.
2. Load the existing freq_meas state.
3. Select the library models.
4. Define the parameter sweeps.
5. Generate the PVT corner permutations.
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Overview continued
6. Run the PVT corner simulations.
EZwave.
a new state.
file (optional).
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configuration.
directory [D].
D
A
C
B
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Task 1: continued
*
button [E].
form [A].
Note that the default simulator is Eldo [C].
This simulator selection was made when the
vco_test configuration was created. The user
may choose to override the default simulator
selection by LMB one of the Simulator type
[D] radio buttons. We will continue to use the
Eldo simulator in this example.
restored to the last time the user exited the
vco_test configuration. Task 1 is complete.
E
A
B C
D
F
* Hotkey = s
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2. LMB the Load State item [B]. This will open
the Load State form [D].
3. LMB select the freq_meas state [C] from the
the What to load area [E].
Load State form [D]. The freq_meas
simulation settings will be loaded into the
restored to the previous frequency measurement
state values. Task 2 is complete.
C
D
A
B
E
F
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Task 3: Select Library Models.
*
[A].
form [D].
2. LMB the Libraries Panel [B].
If the Typical Model Scenario [C] is already
checked, then skip steps 3 and 4.
3. LMB select the Typical Model Scenario
[C].
4. LMB the Apply button [E]. This will
assign the Typical [C] device models to
the Design Configuration in the
Unsaved Session.
Task 3 is complete.
Note: The model variants displayed in the
Model Scenario table are specific to this
tutorial. Model variants are usually defined
by the Kit Baseline. Refer to the Baselines,
Configurations, and States section of this
tutorial. <link>
* Hotkey = g
E
B
C
A
D
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Task 4: Define the PVT parameter
sweeps.
Panel [C].
2. LMB select the CNTRL parameter
row [F].
Note that the CNTRL parameter is currently
defined as a sweep (the Sweep checkbox
[G] and the Sweeps Enabled checkbox [D]
are checked). This definition was loaded
from the freq_meas state.
3. LMB un-check the Sweep checkbox [G].
This will re-define the CNTRL
parameter [A] as a constant with a
value of 0.5 [B]. Note that the Sweeps
Enabled checkbox [D] is now un-
checked.
4. LMB the Update button [E]. This will
refresh the new CNTRL definition in the
parameter table.
F
C
D
A
B
E
G
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Task 4: continued
5. LMB select the VDD parameter row [F].
Note that the VDD parameter [A] is
currently defined as a constant value of 1.2
[B]. The Sweep checkbox [H] and the
Sweeps Enabled checkbox [C] are un-
checked. This definition was loaded from
the freq_meas state.
checkbox [C].
7. LMB select the List radio button [D].
Enter the string
*
0.8, 1.0, 1.2 into the
List field [E]. This will re-define the
VDDparameter as a sweep with 3
discrete values.
8. LMB the Update button [G]. This will
refresh the new VDD definition in the
parameter table. Note that the Sweep
checkbox [H] is now checked.
F
A
C
B
D
E
G
H
* Note: The list delimiters may be commas or spaces.
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Task 4: continued
9. LMB select the Temperature parameter
row [H].
Note that the Temperature parameter [B] is
currently defined as a constant value of
27.0 [E]. The Sweep checkbox [G] and the
Sweeps Enabled checkbox [A] are un-
checked. This definition was loaded from
the freq_meas state.
checkbox [A].
11. LMB select the List radio button [C].
Enter the string
*
-25, 27, 80 into the
List field [D]. This will re-define the
Temperature parameter as a sweep
with 3 discrete values. LMB the Update
button [F].
12. LMB the Apply button [I]. This will
apply all parameter definitions to the
Design Configuration in the Unsaved
Session. Task 4 is complete.
B
A
D
E
C
F
G
I
H
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Task 5: Generate the PVT
permutations.
1. LMB the Corners Simulation Panel [C].
2. LMB check the Enable Corner Analysis
checkbox [A]. This will populate the
Model Scenario and Parameter lists.
3. LMB check the Model Scenario Fast,
Slow, and Typical checkboxes [B].
These three process models will define
the PVT corner permutations.
4. LMB check the Parameter list
Temperature [D] and Global VDD[F]
checkboxes
*
. These sweep parameters
will define the PVT corner
permutations.
Note that the CNTRL parameter [E] is
marked as <invalid for corners>. This is
because CNTRL is currently defined as a
constant; so it can not be used to generate
PVT corner permutations.
B
E
A
C
D
F
* Tip: If Temperature [D] and VDD[F] are not displayed in the
Parameter list, then the Apply button was probably not
clicked in Task-4 step 12. <link>
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Task 5: continued
5. Optional: each PVT corner is numbered
1, 2, etc. You may add a descriptive
text prefix to each corner to provide
meaning. Enter a text string into the
Corners Prefix field [B]. In this example
we use the string tutorial_pvt_corner.
6. LMB the Generate Corner Group button
[C]. This will generate 27 PVT corner
permutations
*
[D]. Expand the Corner
Group name [A] to display the
individual PVT corner permutations [E].
7. Optional: you may add a descriptive
text to the Corner Group to provide
Description field [F]. In this example
we use the string pvt_setup_definition.
LMB the Update button [G].
8. LMB the Apply button [H]. This will
assign the PVT corner definitions to the
E
B
C
D
G
A
F
H
* {Slow, Typical, Fast}
process
x {0.8, 1.0, 1.2}
vdd
x {-25, 27, 80}
temp
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Task 6: Run the PVT corner
simulations.
*
button [A].
This will simulate all 27 PVT corners.
The simulation might require a few
minutes to complete. When all
simulations are complete, the Log tab
[D] will be displayed at the bottom of
2. LMB the Log tab [D]. This will open the
Log Area [B].
are no fatal errors [C].
Task 6 is complete.
* Hotkey = r
A
D
B
C
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the Show Simulator Measurement
Results button [J ]. This will open the
The AMS Results Browser displays a
summary of all 27 PVT corner simulations.
The Run column [B] displays the PVT
corner permutation numbers. The reflib
column [C] displays the process library
model parameters. The PARAM VDD column
[D] displays the VDDparameter values. The
TEMPERATURE column [E] displays the
temperature parameter values. The
WFREQ__TRAN___CLK1P column [F]
displays measured CLK1P frequency results.
From previous examples, we know that the
VCO oscillates at approximately 1.3 GHz
<link>. The PVT results show some normal
results [I], some excessively low results [H]
and some excessively high results [G].
J
A
B C D E F
I
H
G
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Task 7: continued
We can use the sorting feature of the AMS
Results Browser to determine if there are
correlations between the sweep parameters
and the results.
2. In the AMS Results Browser, LMB the
reflibs column title [A]. This will sort
the simulation results into 3 groups.
The first group represents the fast library
models [B]. There are 3 low results, 4
normal results, and 2 high results. No
strong correlation.
The second group represents the slow
library models [C]. There are 6 low results,
1 normal result, and 2 high results. There
appears to be a correlation between slow
process and excessively low or high results.
The third group represents the typical
library models [D]. There are 5 low results,
3 normal results, and 1 high result. No
strong correlation is evident.
B
A
C
D
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Task 7: continued
PARAM VDD column title [A]. This will
sort the simulation results into 3
groups.
The first group represents a VDDvalue of
0.8 V [B]. There are 9 low results, 0 normal
results, and 0 high results. There appears
to be a strong correlation between low VDD
voltage and excessively low results.
The second group represents a VDDvalue
of 1.0 V [C]. There are 5 low results, 1
normal result, and 3 high results. There
appears to be a correlation between
medium VDDvoltage and excessively low or
high results.
The third group represents a VDDvalue of
1.2 V [D]. There are 0 low results, 7 normal
results, and 2 high results. There appears
to be a correlation between high VDD
voltage and normal results.
B
A
C
D
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Task 7: continued
TEMPERATURE column title [A]. This
will sort the simulation results into 3
groups.
The first group represents a temperature
value of -25 degrees [B]. There are 5 low
results, 2 normal results, and 2 high results.
No strong correlation is evident.
The second group represents a temperature
value of 27 degrees [C]. There are 5 low
results, 2 normal results, and 2 high results.
No strong correlation is evident.
The third group represents a temperature
value of 80 degrees [D]. There are 4 low
results, 4 normal results, and 1 high result.
There is a weak correlation between higher
temperatures and low results.
It appears that there are more functional
failures when VDDis less than 1.2 V and/or
the process is slow. Task 7 is complete.
B
A
C
D
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using EZwave.
the Plot Results From Latest Run button
[D]. This will open the EZwave window
[A].
2. In the Waveform List, LMB expand the
sim_vco_vco_test database tree [B].
LMB select the TRAN folder [C].
3. In the TRAN available results [E], LMB
expand the V(CLK1P) waveform group
[F]. This will display a list of all 27 PVT
corner permutation results.
C
B
E
F
D
A
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Task 8: continued
4. <cntrl>-LMB select the seven corner
permutations corresponding to
VDD = 1.2 V [A, B, C, F, G, H, I]. These
waveforms represent normal results.
Tip: Hover the cursor over an individual
result [I] to display the sweep parameter
values [J ] for that specific permutation.
5. RMB to display the Selected Waveforms
pop-up [D]. LMB the Plot (Stacked)
menu item [E]. This will display all
seven corner permutations in the Wave
window.
A
J
B
C
F
G
H
I
D
E
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Task 8: continued
The figure on the left shows the results for
corner permutations with VDD= 1.2 V.
The VCO oscillates at approximately
1.3 GHz. The CLK1P output swings from
approximately 0.3 V to 1.0 V.
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Task 8: continued
pull-down menu [A]. LMB select the
Newitem [B]. This will open a new
Wave window [C].
7. LMB select the V(CLK1P)_10
permutation [D]. <shift>-LMB select
the V(CLK1P)_17 permutation [G].
These eight waveforms represent failed
results using the Slowlibrary models.
8. RMB to display the Selected Waveforms
pop-up [E]. LMB the Plot (Stacked)
menu item [F]. This will display all
eight corner permutations in the new
Wave window [C].
E
C
B
D
G
F
A
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Task 8: continued
The figure on the left shows the various
failure modes for the corner permutations
using the Slowmodel library.
Task 8 is complete.
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as a new state.
The current simulation settings define a set
of PVT corner simulation settings. We will
save the settings as a new state in the
new state is named pvt_setup.
configuration.
Whenever the user loads the pvt_setup
state, PVT simulation settings will be
applied to the VCO. Task 9 is complete.
A
B
D
E
C
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[B].
Task 10 is complete.
A
B
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contains the new pvt_setup state, and
the existing freq_meas, bias_setup,
phnoise_meas , and default states.
the schematic [B].
buttons [C].
complete.
D
C
A
B
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Summary
An existing state named freq_meas was loaded using the Load State form. This restored the vdd_diff
value, ibias_vco value, and the output frequency measurement definition.
Corner case process library models were selected using the Libraries panel.
Corner case sweep parameters were defined as discrete lists using the Params/Sweeps panel.
PVT corner permutations were defined and generated using the Corners panel.
27 PVT corner permutation simulations were run automatically.
PVT corner permutation results were examined using the AMS Results Browser. Possible parameter
correlations were investigated using the browsers sort feature.
Selected PVT corner permutation results were examined as plots using EZwave.
The Design Configuration with parameter and PVT corner permutation definitions was saved as a
new state using the Save State form.
A snapshot of the Design Configuration over-wrote the existing default state when the user exited
Simulation Mode.
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Comparator Test
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Create A New Configuration: Comparator Test
In previous examples we created a collection of setups specifically for VCO testing. Then saved the
setups as states within a configuration named vco_test. The vco_test configuration represents a test
suite for VCO designs. In this example, we will create a test suite for comparator designs, named
comp_test. The test setups will be saved as states within the comp_test configuration.
We begin by adding hysteresis to an existing comparator test bed schematic [B]. Then we enter
Simulation Mode and request a new configuration [E]. This will initialize the Design Configuration with
the contents of the baselines [C]. Next, we will edit the Design Configuration to add parameters, and
define stimuli [A]. Then, we will measure the simulated hysteresis results.
Finally, we will exit Simulation Mode [D]. This will automatically create the comp_test configuration [G]
and store a snapshot of the current simulation settings as the default state [F].
B
E
C
A
D
G
F
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Creating the comp_test configuration
requires 10 tasks:
1. Edit the existing comparator test bench
schematic.
a simulator type.
3. Define the test bench stimuli.
4. Define the DC analysis sweep.
5. Define the stimuli parameters.
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Overview continued
6. Generate the ascending / descending
simulation permutations.
7. Optional: copy transcript text to
template file.
8. Run the ascending / descending
simulations.
EZwave.
10. Exit Simulation Mode and automatically
save the simulation settings as the
default state.
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Task 1: Edit comparator test bed
schematic.
1. In the Project Navigator window [A],
Simulations / comparator /
tb_comparator directory [C, D, F, H].
2. Double LMB the schematic folder [B].
open the tb_comparator test bench
schematic [E].
3. LMB the View All button
*
[G] to display
the entire schematic.
Navigator window.
C
B
A
D
F
H
E
G
* Hotkey = f
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Task 1: continued
the Add Instance button
*
[A]. This will
open the File Browser form [C].
6. LMB the Browse Location Map button
[D]. Note that the Look in: field [B]
now displays the text Location Map.
7. Double LMB the $MGC_IC_DEVICE_LIB
directory [E]. The File Browser will
display a list of pre-defined Mentor
Graphics device cells.
* Hotkey = i
A
C
D
B
E
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Task 1: continued
8. In the File Browser form, LMB select
the ideal_resistor cell [A]. Note that the
text ideal_resistor is displayed in the
File name field [B].
9. LMB the OK button [C]. This will close
the File Browser form, and prepare the
ideal_resistor symbol to be placed.
A
C
B
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Task 1: continued
Note that the Enter Point pop-up [C] opens
to prompt the user for a location in the
workspace.
Tip: Type the r character on the keyboard
to rotate the resistors.
10. LMB place the first resistor at the
location shown [A].
11. LMB place the second resistor at the
location shown [B].
12. Type the <esc>character on the
keyboard to terminate resistor
placement. This will also close the
Enter Point pop-up [C].
A B
C
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Task 1: continued
13. LMB the Add Wire button
*
[A]. This will
open the ADD WI pop-up [F] to prompt
the user for the location of the wire
start/end points.
14. Add the four wires as shown
[B, C, D, E]. LMB the start point; then
LMB the end point.
15. Type the <esc>character on the
keyboard to terminate wire placement.
This will also close the ADD WI pop-up
[F].
B
A
C
D E
F
* Hotkey = w
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Task 1: continued
16. LMB select the net shown [B].
17. LMB the Set Net Name button [A]. This
will open the ADDPRTH pop-up [C].
18. Enter the net name GROUNDinto the
Property Value field [D].
19. LMB the At Location button [E]. Move
the cursor to the location shown [B]
and LMB to place the net name.
20. LMB the OK button [F]. This will close
the ADDPRTH pop-up [C].
F
A
B
C D E
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Task 1: continued
21. LMB select the Check/Save button [A].
The Transcript Area [B] displays the
results of the schematic check.
22. Verify that there are no errors in the
schematic check results [C].
At this point, the comparator test bench
schematic with hysteresis has been saved.
We can now simulate the design.
Task 1 is complete.
B
A
C
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Task 2: Request a new configuration and
select a simulator type.
*
button [G]. This
form [A].
configuration is named comp_test. The
comp_test configuration will include
various comparator hysteresis simulation
settings and definitions.
comp_test configuration.
B
D
C
F
G
E
* Hotkey = s
A
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Task 2: continued
6. The comp_test configuration is now
[B].
7. LMB the OK button [C]. This closes the
baseline settings will be automatically
loaded into the Design Configuration.
At this point, the Design Configuration has
been initialized and Pyxis Schematic is in
Simulation Mode. Task 2 is complete.
B
C
A
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Task 3: Define test bench stimuli.
the Setup Simulation button
*
[A]. This
will open the Setup Simulation form
[C].
2. LMB the Forces panel [B]. This panel is
used to define stimuli sources for
schematic target nets.
Tip: Position the Setup Simulation form
as shown [C]. This will allow you to
easily switch between the two displays
as you select target nets.
B
C
A
* Hotkey = g
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Task 3: continued
select the vdd net [A]. <shift>-LMB
select the minus net [B]. <shift>-LMB
select the vss net [C].
Note that all three net names are displayed
in the Selection from Schematic list [D].
D
A
B
C
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Task 3: continued
4. In the Selection from Schematic list,
LMB select the MINUS net [A].
5. LMB the DC item [B] in the Source Type
list. Enter the value 0 into the
Magnitude (V/A) field [C].
Reference field [D]. Verify that the
Voltage radio button is selected [E].
7. LMB the Add button [F]. The source
summary table [G].
At this point, the MINUS net will be driven
by a DC voltage source referenced to
source is 0 Volts. This is a nominal value;
we will change the source to a sweep
parameter in the following tasks.
G
D
A
C
E
F
B
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Task 3: continued
LMB select the VDD net [A].
list. Enter the value 1.2 into the
summary table [G].
At this point, the VDD net will be driven by
a DC voltage source referenced to
source is 1.2 Volts.
G
D
A
C
E
F
B
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Task 3: continued
LMB select the VSS net [A].
list. Enter the value -1.2 into the
summary table [G].
At this point, the VSS net will be driven by a
-1.2 Volts.
apply all the stimuli force definitions to
the Design Configuration in the
Unsaved Session. Task 3 is complete.
G
D
A
C
E
F
B
H
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Task 4: Define the DC analysis sweep.
1. LMB the Analysis panel [A].
2. LMB check the DC Analysis Selector
checkbox [B]. This will also check the
Enable DC checkbox [C].
3. Select Source (Force) [D] from the
Sweep Type list.
4. LMB the crosshairs button [E]. This will
open the Force Selection form [G].
5. LMB select the row containing the
/minus signal [F].
6. LMB the OK button [H]. This will close
the Force Selection form [G] and will
allow the /minus signal forcing function
to be defined.
C
F
D
B
A
E
G
H
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Task 4: continued
Note that FORCE__minus is now displayed
in the force name field [A].
7. LMB the Start field [B]. Enter the text
{DC_START} into the Start field.
8. LMB the Stop field [C]. Enter the text
{DC_STOP} into the Stop field.
9. LMB the Step field [D]. Enter the text
{DC_STEP} into the Step field.
At this point, the /minus net will be driven
by the FORCE__minus function. The
FORCE__minus function is defined as a
linear DC sweep that starts at a
parameterized value of {DC_START} and
ends at a parameterized value of
{DC_STOP}. Each step in the sweep is
defined by the parameterized value of
{DC_STEP}.
Task 4 is complete.
A
B C D
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Task 5: Define the stimuli parameters.
An ascending/descending sweep is used to
test the hysteresis response of a circuit. We
will define this type of sweep for the test
bed minus signal.
If we connect a repetitious stimuli to the
minus input, a transient simulation would
be required. This would produce a
V
out
vs. time plot.
However, in this example, we wish to
produce a transfer function plot
(V
in
vs. V
out
). The transfer function requires
a DC simulation. Therefore, the stimuli will
be defined as a set of DC parameter
sweeps.
The stimuli consists of two DC sweeps: an ascending
sweep from -1.2 V to 1.2 V, and a descending sweep
from 1.2 V to -1.2 V. Each sweep is defined by a
(DC_START,DC_STOP) parameter pair.
Note that there are two different DC_START parameter
values: -1.2 V for the ascending sweep, and 1.2 V for the
descending sweep. There are also two different DC_STOP
parameter values: 1.2 V for the ascending sweep, and
-1.2 V for the descending sweep.
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Task 5: continued
1. LMB the Params/Sweeps panel [C].
2. Enter the text DC_START into the
Parameter name field [A]. Enter a
nominal value of -1.2 into the Value
field [B].
checkbox [D].
4. Verify that the List radio button is
selected [E]. Enter the text
*
-1.2, 1.2
into the List field [F].
5. LMB the Add button [G].
Note that the DC_START parameter is
added to the summary table [H].
Note that the DC_START parameter is
defined as a list of two values: -1.2 and 1.2
[I].
H
C
A B
D
E
F
G
I
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Task 5: continued
6. Enter the text DC_STOP into the
nominal value of 1.2 into the Value field
[B].
checkbox [C].
8. Verify that the List radio button is
selected [D]. Enter the text
*
1.2, -1.2
into the List field [E].
9. LMB the Add button [F].
Note that the DC_STOP parameter is added
to the summary table [G].
Note that the DC_STOP parameter is
defined as a list of two values: 1.2 and -1.2
[H].
G
A B
C
D
E
F
H
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Task 5: continued
10. Enter the text DC_STEP into the
nominal value of 0.01 into the Value
field [B].
11. LMB the Add button [C].
Note that the DC_STEP parameter is added
to the summary table [D].
Note that the DC_STEP parameter is
defined as a constant value of 0.01 [E].
D
A B
C
E
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Task 5: continued
12. LMB the APPLY button [A]. This will
apply the current stimuli and parameter
definitions to the Design Configuration.
Task 5 is complete.
If we run a simulation using the parameter
sweeps as they are currently defined, then
we would get the odd looking waveform
shown on the left. This happens because
the DC_START and DC_STOP parameters
have two values each. All parameter
permutations would be run; including the
unwanted cases of:
DC_START = DC_STOP = -1.2 V and
DC_START = DC_STOP = 1.2 V
In the next task, we will eliminate the two
unwanted cases by using corner cases to
control the sweep values.
A
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Task 6: Generate the ascending /
descending simulation permutations.
1. LMB the Corners Simulation Panel [B].
2. LMB check the Enable Corner Analysis
checkbox [A]. This will populate the
Parameter list.
3. LMB check the Parameter list Global
checkbox
*
[C]. These parameters will
define the corner permutations.
5. Optional: each corner is numbered 1,
2, etc. You may add a descriptive
text prefix to each corner to provide
Corners Prefix field [D]. In this example
we use the string DC_sweep.
6. LMB the Generate Corner Group button
[E]. This will generate 4 corner
permutations [H]. Expand the Corner
Group name [F] to display the
individual corner permutations [G].
* Tip: If DC_STOP and DC_START are not displayed in the
Parameter list, then the Apply button was probably not
clicked in Task-5 step 12. <link>
B
A
G
C
D
E
H F
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Task 6: continued
7. LMB un-check the two checkboxes [A]
corresponding to:
DC_STOP = DC_START = 1.2
DC_STOP = DC_START = -1.2
These two sweep permutations will be
excluded from the simulation. Note that
the Total Corners is now 2 [C].
8. Optional: you may add descriptive text
to the Corner Group to provide
Description field [D]. In this example
we use the string
ascending_descending_sweep. LMB the
Update button [E]. Note that the
description is now displayed in the
summary table [B].
9. LMB the Apply button [F]. This will
apply the ascending / descending
corner definitions to the Design
Task 6 is complete.
F
A
E
D
B
C
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If the Transcript Area is not currently visible
at the bottom of the Pyxis Schematic
window [A], then do steps 1-3.
menu.
item.
item.
B
C
D
A
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Task 7: continued
[B].
Task 7 is complete.
A
B
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Task 8: Run the ascending /
descending corner simulations.
*
button [A].
This will simulate the ascending and
descending corners. When the
simulations are complete, the Log area
[B] will be displayed at the bottom of
Task 8 is complete.
* Hotkey = r
A
B
C
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using EZwave.
1. In the Pyxis Schematic window [A],
LMB select the fsout net [B]. Type the
hotkey x. This will add an EZwave
cross-probe to the fsout net and
automatically open the EZwave window
[C].
B
A
C
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Task 9: continued
2. In the DC (Wave:1) window [A], hover
the cursor over the left curve. A pop-up
will display showing the DC_START and
DC_STOP values [C]. This curve
corresponds to the descending corner
results.
3. Hover the cursor over the right curve. A
pop-up will display showing the
DC_START and DC_STOP values [D].
This curve corresponds to the
ascending corner results.
Note that the horizontal axis [E] represents
V
in
(minus net) stimulus values.
Note that the vertical axis [B] represents
V
out
(fsout net) response values.
The simulation results shows a hysteresis of
roughly 0.55 V with slight asymmetry.
Task 9 is complete.
C
A
D
E
B
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The comp_test configuration will be
Database.
the schematic [B].
buttons [C].
complete.
D
A
B
C
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Summary
An existing comparator test bench schematic was modified to add hysteresis to the circuit.
A new configuration named comp_test was created using the New Design Configuration form.
Global parameters were defined using the Params/Sweeps panel.
A net stimulus source was defined using the Forces panel.
The simulation was configured as a DC analysis using the Analysis panel. DC analysis allows the
transfer function to be plotted.
Ascending/descending stimuli were defined as a set of DC sweeps using the Params/Sweeps panel.
Some undesirable permutations were eliminated using the Corners panel.
A DC analysis was run and the results displayed using an EZwave cross-probe.
A state snapshot was automatically saved as the default state when the user exited Simulation
Mode.
256
Op Amp Test
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Create A New Configuration: Op Amp Test
In previous examples we created a collection of DC setups specifically for VCO or comparator testing.
Then saved the setups as states within a configuration. The configurations represent a test suite for
VCO or comparator designs. In this example, we will create a test suite for op amp designs, named
opamp_test. The AC test setups will be saved as states within the opamp_test configuration.
We begin by entering Simulation Mode and selecting a default simulator [B]. This will initialize the
Design Configuration with the contents of the baselines [C]. Next, we will edit the Design Configuration
to define stimuli and measurements [A].
Finally, we will save the Design Configuration as a new state named pm_meas [D]. This will create the
opamp_test configuration [F] and store a snapshot of the current simulation settings as the pm_meas
state [E].
B
A
C
E
F
D
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Creating the opamp_test configuration
requires 10 tasks:
a simulator type.
2. Setup the AC analysis.
3. Define the test bench stimuli.
4. Define the phase margin measurement.
5. Run the AC simulation.
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Overview continued
EZwave.
a new state.
9. Optional: copy transcript text to a
template file.
default state.
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Task 1: Request a new configuration
and select a simulator type.
navigate to the MixedSims / opamp
directory [B, F].
2. Double LMB the schematic folder [C].
open the opamp schematic [E].
*
[D] to display
Navigator window.
* Hotkey = f
B
A
C
E
D
F
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Task 1: continued
*
button [G]. This
form [A].
configuration is named opamp_test. The
opamp_test configuration will include
various op amp simulation settings.
opamp_test configuration.
B
G
* Hotkey = s
A
C
E
F
D
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Task 1: continued
10. The opamp_test configuration is now
[B].
11. LMB the OK button [C]. This will close the
baseline settings will be automatically
copied into the Design Configuration.
At this point, the Design Configuration has
been initialized and Pyxis Schematic is in
Simulation Mode.
Task 1 is complete.
B
A
C
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Task 2: Setup the AC analysis.
*
[A]. This
will open the Setup Simulation form.
2. LMB the Analysis panel [D].
3. LMB check the AC Analysis Selector [E].
Verify that the Enable ACcheckbox is
checked [B].
4. LMB the Start Freq field [F]. Enter the
value 100 into the Start Freq field.
5. LMB the Stop Freq field [G]. Enter the
value 100meg into the Stop Freq field.
6. Verify that pts/decade is selected in the
frequency scale field [H]. Verify that
the value 10 is entered the frequency
points field [C].
Task 2 is complete.
* Hotkey = g
B
A
E
D
F G
H
C
At this point, the AC analysis will run from 100 Hz to
10 MHz, and generate 10 results per decade of
frequency.
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Task 3: Define test bench stimuli.
In this task we will assign an AC source to
the op amp IP input. We will assign a DC
source to the IMand VPB inputs. Then we
will assign a DC source to the VDDand VSS
power inputs.
1. LMB the Forces panel [F].
select the IP net [D]. Shift-LMB select
the IM, VPB, VDD, and VSS nets
[C, A, B, E]. Note that these 5 nets are
now displayed in the Selection From
Schematic list [G].
A
B
F
C D
E
G
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Task 3: continued
LMB select the IP net [A]. In the
Source Type list, LMB the AC item [B].
DC Magnitude (V/A) field [C]. Enter the
value 1 into the AC Magnitude (V/A)
field [D]. Enter the value 0 into the
AC Phase (degrees) field [E].
Reference field [G]. Verify that the
Voltage radio button is selected [H].
summary table [F].
At this point, the IP net will be driven by a
AC voltage source referenced to GROUND.
1 Volt. The DC offset is 0 Volts, and the
phase shift is 0 degrees.
D
F
C
B
A
I
E
G
H
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Task 3: continued
LMB select the IM net [A]. In the
Source Type list, LMB the AC item [B].
DC Magnitude (V/A) field [C]. Enter the
value 0 into the AC Magnitude (V/A)
field [D]. Enter the value 0 into the
AC Phase (degrees) field [E].
Reference field [G]. Verify that the
Voltage radio button is selected [H].
summary table [F].
At this point, the IM net will be driven by a
AC voltage source referenced to GROUND.
0 Volts. The DC offset is 0 Volts, and the
phase shift is 0 degrees.
D
F
C
B
A
I
E
G H
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Task 3: continued
LMB select the VPB net [A].
13. In the Source Type list, LMB the DC
item [B]. Enter the value 0.6 into the
summary table [G].
At this point, the VPB net will be driven by a
0.6 Volts.
G
A
C
F
D
E
B
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Task 3: continued
LMB select the VDD net [A].
item [B]. Enter the value 1.0 into the
summary table [G].
At this point, the VDD net will be driven by
a DC voltage source referenced to
source is 1.0 Volts.
G
D
A
C
E
F
B
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Task 3: continued
LMB select the VSS net [A].
item [B]. Enter the value 0 into the
summary table [G].
At this point, the VSS net will be driven by a
0 Volts.
Task 3 is complete.
G
A
C
D
F
B
E
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Task 4: Define the phase margin
measurement.
1. LMB the Measures panel [B].
select the OP net [A]. Note that the OP
net is now displayed in the Selection
From Schematic list [C].
A
C
B
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Task 4: continued
3. LMB the Label field [A]. Enter the text
Phase_Margin into the Label field. This
defines the name of the measurement.
4. LMB select AC in the Analysis drop-
down list [B]. LMB select Xycond in the
Function drop-down list [C]. LMB select
Voltage in the Measure drop-down list
[D]. LMB select Phase in the Modifier
drop-down list [E]. This defines an AC
phase voltage measurement.
5. LMB the max field [F]. Enter the text
END into the max field. LMB the min
field [G]. Enter the text START into the
min field. START and ENDare Eldo
keywords. The measurement will start
at the beginning of the simulation, and
stop at the end of simulation.
B
A
G
F
C
D
E
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Task 4: continued
The definition of phase margin is the phase
shift in degrees when the magnitude falls
below 0 dB. We will define a condition to
record the phase measurement at this
single point.
6. LMB the condition field [A]. Enter the
text VDB(OP)<0.0 into the condition
field. This defines measurement to be
recorded when the voltage on the OP
net falls below 0.0 dB for the first time.
7. LMB the Add button [B]. The
measurement definition is now
displayed in the summary table [C].
8. LMB the Apply button [D]. This applies
all the force and measurement
definitions to the Design Configuration
in the Unsaved Session.
Task 4 is complete.
A
B
D
C
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Task 5: Run an AC simulation.
*
button [A].
This will sweep the frequency of the
stimulus on the IP net and record the
phase margin point on the OP net.
Log area [B] will be displayed at the
Task 5 is complete.
* Hotkey = r
A
B
C
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the Show Simulator Measurement
Results button [B]. This will open the
Note that the results show the name of the
measurement, PHASE_MARGIN [D], that
we previously defined in Task 4. <link>
The measured value of the phase margin is
-131.206 degrees [C].
2. Optional: minimize the AMS Results
Browser.
Task 6 is complete.
B
C
A
D
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using EZwave.
select the OP net [A]. Type the x
hotkey. This will add an EZwave cross-
probe to the OP net and automatically
open the EZwave window [B].
A
B
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Task 7: continued
2. In the EZwave window [B], LMB the
Add Cursor button [A]. LMB-drag the
cursor [C] to the right; until it
intersects the Magnitude curve near 0
dB [D].
Note that the corresponding Phase curve
value is -131.2003 degrees [E]. This
matches the results reported by the AMS
Results Browser.
Note that the 0 dB point corresponds to an
IP input frequency of 13.6387 MHz [F].
Task 7 is complete.
F
C
E
D
B
A
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as a new state.
2. LMB select the Save State item [B].
This will open the Save State form [C].
the Name field [D]. In this example,
the new state is named pm_meas.
settings and save it within the
Whenever the user loads the pm_meas
state, the op amp will be configured to run
a phase margin analysis.
Task 8 is complete.
A
D
B
E
C
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If the Transcript Area is not currently visible
at the bottom of the Pyxis Schematic
window [A], then do steps 1-3:
menu.
item.
item.
B
C
D
A
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Task 9: continued
[B].
Task 9 is complete.
A
B
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The opamp_test configuration will be
Database.
the schematic [B].
buttons [C].
complete.
D
A
B
C
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Summary
A new configuration named opamp_test was created using the New Design Configuration form.
The simulation was configured as an AC analysis using the Analysis panel.
A net stimulus source was defined using the Forces panel.
A phase margin measurement was defined using the Measures panel.
An AC analysis was run and the numeric results displayed using the AMS Results Browser.
Graphic simulation results were displayed using an EZwave cross-probe.
The Design Configuration including the stimuli and measurement definitions was saved as a new
state using the Save State form.
Mode.
282
Monte Carlo Analysis
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Create A New State: Monte Carlo Analysis
In the previous example, we created a test suite specifically for op amps, named opamp_test. In this
example, we will load one of the states from opamp_test and use it as the basis for multiple Monte
Carlo simulations.
We begin by entering Simulation Mode and selecting the opamp_test configuration [D]. This will
initialize the Design Configuration with the previous simulation settings. Next, we will load the
pm_meas state [E] from the opamp_test configuration. This will configure the Design Configuration
with phase margin stimuli and measurement definitions [A].
Next, we will change the library models to their equivalent statistical versions [B].
Finally, we will run multiple Monte Carlo simulations and record the phase margin results [C].
D
B
C
E
A
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Creating the new default state requires 8
tasks:
1. Open the existing opamp_test
configuration.
2. Load the existing pm_meas state.
3. Select a statistical library.
4. Define the Monte Carlo analysis
parameters.
5. Run the Monte Carlo simulations.
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Overview continued
EZwave.
default state.
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Task 1: Open existing configuration.
navigate to the MixedSims / opamp
directory [B, F].
2. Double LMB the schematic folder [C].
open the opamp schematic [E].
*
[D] to display
Navigator window.
* Hotkey = f
B
A
C
E
D
F
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Task 1: continued
5. In the Pyxis Schematic window [A], LMB
the Enter Simulation Mode
*
button [F].
This will open the Entering Simulation
Mode form [B].
6. LMB select the existing opamp_test state
[C]. Note that the default simulator for
opamp_test is Eldo [D].
The user can override the default simulator
selection by LMB one of the Simulation type
radio buttons [E]. However, in this example,
we will continue to use the Eldo simulator.
7. LMB the OK button [G]. This will close the
Entering Simulation Mode form [B]. The
Design Configuration will be initialized with
the default state settings of the
At this point, the Design Configuration is
initialized and Pyxis Schematic is in Simulation
Mode.
Task 1 is complete.
F
* Hotkey = s
E
B
D
A
C
G
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2. LMB select the Load State item [B].
This will open the Load State form [C].
3. LMB select the pm_meas state [D].
4. LMB the What to load - Select All
button [E].
5. LMB the OK button [F]. This will copy
all the stimuli and measurement
definitions from the pm_meas state
into the Design Configuration in the
Unsaved Session.
At this point, the Design Configuration is
configured to run a single phase margin
analysis.
Task 2 is complete.
A
D
B
F
C
E
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Task 3: Select a statistical library.
*
[F]. This
will open the Setup Simulation form
[A].
Note that the stimuli [D] and measurement
[E] definitions were loaded from the
existing pm_meas state.
2. LMB the Libraries panel [B].
Note that the Typical model scenario [C] is
currently selected. The Typical model
scenario is not statistical. We need to select
one of the statistical model scenarios for
Monte Carlo analysis. In this example
Process Design Kit, the statistical model
scenarios begin with the string MC (aka.
Monte Carlo).
3. LMB select the MC MOS / Typical [G]
model scenario.
Task 3 is complete.
B
F
A
D
E
C
G
* Hotkey = g
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Task 4: Define the Monte Carlo
analysis parameters.
1. LMB the Monte Carlo panel [F].
2. LMB check the Enable MC Analysis
check-box [A].
3. Verify that the value in the
Num of Runs: field [B] is 200.
4. Verify that the Reference Output
Voltage radio button [D] is selected.
5. LMB-select Phase from the drop-down
Modifier list [C].
6. Enter the output net name OP into the
Net 1 field [E].
7. LMB-select 2 (accurate) from the drop-
down Sensitivity list [G].
apply the Monte Carlo definitions to the
At this point, the analysis is defined as 200 Monte Carlo
runs. The OP net output voltage phase will be recorded
as the result of each run. The post-simulation
sensitivity analysis is optimized for accuracy, not speed.
D
C
F
B
E
G
A
H
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Task 5: Run an AC simulation.
*
button [A].
This will execute 200 Monte Carlo runs
and record the phase margin point on
the OP net. When the simulation is
complete, the Log area [B] will be
Schematic window.
Task 5 is complete.
* Hotkey = r
A
B
C
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the log button [C]. In the cascading
menu, LMB-select the View Complete
Log item [A]. This will open the AMS
Results Browser [B].
2. In the AMS Results Browser [B], scroll
down to the bottom of the Table of
Contents [D]. LMB-select the Extract
distribution item [E].
3. Re-size the AMS Results Browser
window [B] as needed. D
A
C
B
E
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Task 6: continued
In the previous example using the Typical
model scenario, we measured a phase
margin of -131.206 degrees. <link>
In this example using the Monte Carlo MOS
/ Typical model scenario, we measure a
nominal phase margin of -131.2055
degrees [A]. This matches the results from
the previous example. We also see that
there is a 28.5% standard deviation [B]
from the nominal value.
These same results are shown in the
histogram [C]. Note that there are two
outlier results in the histogram [D, E].
A
C
B
D
E
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Task 6: continued
4. Scroll down a few lines to the section
labeled Estimation of Sensitivity [A].
These results show that the variable
PM(DXW.PMOS.10.XW) [B] is the primary
contributor to phase margin variation at
24.93%.
5. Optional: minimize the AMS Results
Browser.
Task 6 is complete.
A
B
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using EZwave.
1. In the Pyxis Schematic window,
LMB the Plot Results From Latest Run
button [B]. This will open the EZwave
window [A].
B
A
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Task 7: continued
menu [A]. LMB-select the Open item
[B] from the cascading menu. This will
display the Open form [D].
3. LMB-select the swd file [C].
4. LMB the Open button [G]. This will
display the Wave:1 window in the
workspace [E].
Note that 3 curves are plotted [F] that
represent the phase voltage on the OP net.
The green
*
VP(OP) curve corresponds to
the nominal voltage results. The yellow
VP(OP)_H curve corresponds to the high
voltage results. The blue VP(OP)_L curve
corresponds to the low voltage results.
A
D
B
C
G
E
F
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Task 7: continued
5. In the EZwave window, LMB the Add
Cursor button [A]. From the previous
example, we determined that the 0 dB
crossover point corresponds to an input
frequency of 13.6387 MHz. <link>
LMB-drag the cursor to the right; until
it reaches 13.6387 MHz [B].
Tip: To display the area of interest, RMB an
axis [D, E]. Then manually override the Axis
Range in the Properties form.
Note that the green
*
nominal curve value is
-131.2003 degrees [C]. This matches the
results from the previous example. The low
and high results are -139.6471 degrees and
-144.1478 degrees respectively.
B E
A
D
C
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Task 7: continued
6. In the EZwave window, LMB select the
EXT item [B] in the Waveform List. This
will display the extracted results list
[C].
7. In the extracted results list [C], LMB-
drag the HIST(PHASE_MARGIN) item
[D] to an empty spot in the workspace
[E]. This will open a new Wave
window [A] containing a histogram of
the phase margin measurements.
Note the histogram matches the ASCII
histogram in the Complete Log [F]. <link>
Task 7 is complete.
E
C
B
D
A
F
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the schematic [B].
buttons [C].
Note: In this example we saved the Monte
Carlo simulation settings as the default
state. This state may be over-written the
next time the opamp_test configuration is
exited. To save the Monte Carlo settings
permanently, we would typically invoke
Save State before we exit Simulation Mode.
complete.
D
A
B
C
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Summary
An existing configuration named opamp_test was opened using the Entering Simulation form.
An existing state named pm_meas was copied into the Design Configuration using the Load State
form.
The simulation models were changed to Monte Carlo statistical models using the Libraries panel.
Monte Carlo analysis and measurement parameters were defined using the Monte Carlo panel.
Multiple Monte Carlo runs were executed and the results recorded.
The distribution and sensitivity results from the Monte Carlo runs were displayed as text using the
AMS Results Browser.
The distribution results from the Monte Carlo runs were displayed graphically using EZwave.
Mode.
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DRC, LVS,
xRC
Transistor Level
Schematics
Design Verification
Mixed Signal
Floorplanning
and
Assembly
Full-Custom
Layout
Automated
Layout
Analog
RF
Parasitic Modeling
Area Estimation
Schematic Design
Transistor Level
Schematics
Stage 4: Mixed Signal Verification
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In this Session, You Will
Take a brief tour of Mixed Signal Design Verification in Pyxis
Perform the Following Exercises Using Pyxis:
Setup Verilog AMS models
Compile models Verilog AMS models are available within the Questa ADMS
installation
Register models to symbols
Map pins and properties
Perform Mixed Signal Simulation using VerilogAMS Models
Initialize Simulation
View Simulation Results
Setup a Design Configuration
Change Simulation Models
Modify Properties on Symbols
Rerun Simulation and View Results
Define A2D and D2A Converters for Automatic Insertion
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This tutorial is based on the Generalized Mixed Signal PLL
Contains both Analog and Digital Components
Differential VCO runs from 600MHz to 1.2GHz
Prescaler halves VCO frequency and converts differential signals to
single-ended
Digital M and N-Dividers to control output frequency - F
O
= F
R
(N/M)
Frequency Synthesizer Circuit
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Abstraction, a key in Functional Verification
abstraction is the key to verifying large systems, ITRS 1999
Use abstraction - validate at different levels of abstraction to
improve (verification) performance, Dr. Walden C. Rhines, Scalable
Verification, DAC 2003 Special Event
The Bicycle Race Lyonel Feininger, 1912
National Gallery of Art, Washington
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Mentor Graphics Products
Technologies
Mixed-Signal Simulator - Questa ADMS
HDL System
Analog
Behavioral
Modeling
SPICE
Fast-SPICE
RF
D
i
g
i
t
a
l
VHDL
Verilog SystemC
SystemVerilog
A
M
S
VHDL-AMS
Verilog-AMS
T
r
a
n
s
i
s
t
o
r
Eldo
ADiT
Eldo RF
Mixed-Signal SoC
Functional Verification
Digital Logic
AMS IP
Analog
Embedded Memory
Power Management & AMS
RF Front-end
Quest a ADMS
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Questa ADMS - Flexible/ Scalable Architecture
Industry-standard modeling languages
Single kernel architecture - No Partition required
User-friendly design re-configuration mechanisms
Verilog-AMS
Verilog
Verilog
System Verilog
SPICE
Verilog SPICE
VHDL-AMS
SPICE
C/C++
C/C++
Verilog System C
MATLAB
C/C++
C/C++
SPICE VHDL-AMS
VHDL
Verilog-AMS
SPICE VHDL-AMS VHDL Verilog Verilog-AMS E System Verilog
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Online Examples
Verilog-AMS PLL Example available inside of Questa ADMS
Users Manual
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Where to Look for Modeling Help
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Supports language based
design
Model compilation
Handles all necessary
naming and mapping
of compiled libraries
Model registration
Automatic symbol
generation
Pin and property
mapping
Supports QuestaADMS
and QuestaSim tools
suites
The Pyxis Language Interface
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can skip this step
NOTES:
two script files:
data
tool home directory
settings
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Step 2: Open Language Interface
2:RMB
1. In the Project Navigator
window, select the Pyxis_SPT
project
2. Select the popup menu
item: RMB->Open->Language
Interface
NOTE:
This will launch the Pyxis Interface
Window which enables you to
compile HDL models and register
them to symbols in your design
hierarchy.
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Step 3: Compile all models in Pyxis_SPT
2
1. In the Pyxis Language
Interface window, select the
Pyxis_SPT project
2. Click on the Compile icon in
the Language Model RC
toolbar
3. With your mouse hovering
over the Pyxis_SPT project,
select the popup menu item:
RMB-> Filter Hierarchy->
Show Compiled Libraries
If you do not see a compiled
library for AMS-12.1 or AMS-
12.2, youll need to stop this
tutorial and verify that you
have AMS 12.1 or 12.2 setup
correctly
1
3:RMB
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Step 4: Register new model for filter
Interface window, expand
the GenericPLL library.
2. Expand the filter cell,
then double click on the
flt_butter_low VerilogAMS
model to open it in a
Notepad text editor
3. With the flt_butter_low
model selected, select the
pop-up menu item:
RMB->Register Model
2
3:RMB
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Step 5: Register model Select Symbol
1
2
1. In the Register Model from
Source dialog box, click on the
Browse icon next to Symbol: text
field
2. Navigate to and select the
$PYXIS_SPT/GenericPLL/filter/filter
symbol
3. Click OK on the Symbol
Navigator dialog box but do not
close the Register Model from
Source dialog box yet
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Step 6: Register Model Map the Pins
1. In the Register Model
from Source dialog box, click
on the Map Pins button
2. Specify that the vdd_diff
and vss_diff pins are left
open
3. Map ain of the model to
LFIN of the symbol by using
Control-LMB to select ain
and LFIN together, then click
on the Map button to create
the association
4. Map aout of the model to
LFOUT of the symbol and OK
the Map Pins dialog box
NOTE:
This makes it possible to register
models to a symbol without
modifying symbol pins or model
port names.
1
3
4
4
3
4
2
3
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Step 7: Register Model Map the Properties
1. In the Register Model from
Source dialog box, click on
the Map Properties button
2. Map the following
properties
Model Symbol
N f_order
fc f_cutoff
K Kf
3. Click OK the Map Properties
and Register Model dialog
boxes to finish the registration
2
2
2
3
1
3
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Step 8: Check Language Model
Interface window, select
the filter symbol under the
filter cell
Language Models icon in
the Language Model RC
toolbar
3. Click on the Open
Command Log icon in the
Language Model RC toolbar
4. Verify that there are no
errors listed in the
command log and the
Message Area window says
Selected objects pass
check, then close the Pyxis
Language Interface session
window
3
2
4
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Step 9: Open tb_FreqSynth Design Config
1. Click on the Message Area tab in
the Project Navigator window
navigate to the tb_FreqSynth cell
3. Double click on the QuestaADMS
4. With your mouse hovering over
the QuestaADMS Design
Configuration, select the popup-
menu item: RMB->Open->
Schematic Editor
NOTE:
Design Configurations encapsulate the
schematic, netlist, model selections, and
simulation setup. They are used to drive
downstream tools like Pyxis Layout SDL,
Eldo or Calibre LVS. This Design
Configuration is configured specifically for
a high-level HDL Questa ADMS simulation
1
2
3
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Step 10: Run Mixed Signal Simulation
1. Click on the Message
Area tab in the Pyxis
Schematic window
2. Start the QuestaADMS
simulation by clicking on
the Run Simulator icon
NOTES:
This will automatically netlist
your design and begin the
Questa ADMS simulation. A
simulation Log window will
appear see the next step.
The simulation may take several
minutes depending on your
machine.
2
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Step 11: View Simulation Log Window
1. Stretch the Simulation
Log window by dragging
the stretch handle on the
splitter bar so you can see
the simulation log from
Questa ADMS
2. Return the Simulation
Log Window size to show
about four or five lines for
the rest of the tutorial
NOTES:
You can resize the Simulation
Log Window at any time.
Pyxis session windows can be
easily customized by each
individual user. Window
customizations are
automatically saved and
reloaded whenever the user
reopens the window.
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Step 12: Open Waveform Results in EZwave
1. Click on the Message
Area tab in the Pyxis
Schematic window
2. Click on the Plot Results
from Latest Run icon
3. In the EZwave waveform
viewer, select the pull-down
menu item: Edit->Options
4. Select Automatic Reload
5. Enable the Replace
Previous Result option and
OK the EZwave Display
Preferences dialog box
NOTE:
With the Replace Previous
Result option enabled, EZwave
will overwrite plotted waveforms
with waveforms from new
simulation data.
1
2
3
5
4
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Step 13: Load Saved Waveform Database
1
2
1. In the EZwave waveform
viewer, click on the Open
icon
2. Select the saved
waveform database
FreqSynthSignals.swd by
double clicking on it
3. Resize the EZwave
window to view all of the
signals
NOTE:
The Save Waveform Database
contains preloaded signals and
measurements to be plotted. In
this example, were plotting the
frequency measurement of the
FreqSynth clock output.
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Step 14: Setup EZwave Options
1. Click on the Add
Cursor icon
2. Drag the cursor to
see the output
frequency and control
voltage
NOTE:
You can also use F5 to
add cursors.
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2
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Step 15: Change Input Stimulus
1. Select the
FREQSYNTH_STIMULUS1
instance
2. Select the popup menu item
RMB->Change Model->
VERLOG
(FreqSynth_Stimulus_ModFreq)
3. Run a new QuestaADMS
simulation by clicking on the
Run Simulator icon
NOTE:
You will see the new VIEW
property name and new value
highlighted in red to show that its
value is different in the
configuration than what it is in the
schematic.
2: RMB
1
3
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Step 16: Rerun Simulation/ Highlight tb_FreqSynth
While the simulation is running, we
can view the Mixed Signal Design
Partitions
1. Select the pull-down menu
item View -> Highlight
Objects ->All
2. You can also pause or stop
the simulation and view the
results so far
NOTE:
You will see an EZwave Confirm
dialog box appear. You may click
on the Continue button to load
new results, as well as refresh the
wave form window at any point
during the simulation. The steps
outlined in this tutorial, however,
assume the simulation is finished
before clicking on the Continue
button.
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2
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Step 17: Descend into FREQSYNTH1 Instance
The Mixed Signal Design
Partitions show what pieces of
the design are Digital (blue),
Analog (red), or Mixed-Signal
(yellow)
1. Descend into the
FREQSYNTH1 instance using
the Middle Mouse Button
down stroke (or use the
pull-down menu File->Open
Down)
2. Highlight the partitions
using the pull-down menu
item View -> Highlight
Objects ->All
1: MMB
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Step 18: Highlighted FreqSynth Partitions
NOTE:
The charge_pump_ub and
vco blocks are shown as
analog even though they are
being modeled by a Verilog
AMS model.
1. When your simulation is
done, click on the Continue
button in the EZwave
Confirm dialog box
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Step 19: View New Simulation Results
Your simulation results will be
automatically reloaded (Click
on Continue in the EZwave-
Confirm dialog box)
1. Click on the View All
icon in the waveform
viewer
2. Add Cursors to see the
three frequency results
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Step 20: Select Model with Hierarchy Navigator
1. Click on the Hierarchy
Navigator icon
2. Select the FILTER1
instance in the Hierarchy
Navigator
item: RMB-> Change
Model-> VERILOG_A
(flt_butter_low_m1)
NOTES:
The Hierarchy Navigator allows
you to configure multiple
instances or components
throughout the entire design
hierarchy. It also allows you to
open and zoom to any instance
in the hierarchy by double
clicking.
2
1
3: RMB
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Step 21: Using the Edit Object dialog box
instance in Pyxis Schematic
2. Open the Edit Object
dialog box by typing the q
hotkey
3. Change the f_cutoff to
be 200K and the f_order to
be 3 and hit the Enter key
to apply the changes and
take down the Edit Object
dialog box
4. Rerun the Simulation
NOTE:
You will see the f_cutoff and
f_order property values turn
red. The red color indicates
that the property is added in the
Design Configuration and not on
the schematic. This is often
called an annotated property.
1
2: q
4
3
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Step 22: View the Updated Simulation Results
Your simulation results will be
automatically reloaded (click on
Continue in the EZwave
Confirm window)
1. Add Cursors to see the
three frequency results
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Step 23: Specify Transistor Level Schematic Models
1. In the Hierarchy
Navigator, hold down your
Control key and LMB click
select the
CHARGE_PUMP_UB1,
FILTER1, PRESCALER1 and
VCO1 instances
item: RMB-> Change
Model-> SCHEMATIC
NOTE:
The RMB popup menu in the
Hierarchy Navigator is context
sensitive and aware that each
of the selected instances can be
changed to a SCHEMATIC
model.
1
1
1
1
2: RMB
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Step 24: Highlight New Configuration
1.View the new design
partitions (see step 10
if necessary)
2. Click on the Setup
Parameters icon in the
Edit Toolbar
NOTE:
In the next step well define
bias currents for instances
defined as transistor level
schematics.
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1. Click on Params/Sweeps
under the Simulation Panels
on the left of the dialog box
2. Update the bias currents
for the analog blocks to:
400u for ibps_param
700u for ibvco_param
5u for ibcp_param
To perform the updates, do
the following steps for each
parameter:
1a. Select the parameter
1b. Enter the new
parameter value
1c. Click on the Update
button or press Enter
2c
Step 25: Specify Bias Currents
2a
2b
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1. Click on Analysis under
the Simulation Panels on
the left side of the dialog
box
2. Select Tran under the
Analysis Selector
3. Set the Max Time Step
(HMAX) to 50p
4. Click on Converters
under the Simulation
Panels on the left side of
the dialog box
Step 26: Set the Max Time Step (HMAX)
2
3
4
5
1
NOTE:
There is a Summary column
next to each Simulation
Panel that indicates the
current setup.
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Step 27: Define A2D Converter
1. Select Std_logic under the list
of models
2. Enter these parameter values
vth1 = 0.45
vth2 = 0.55
3. Click the Add button or simply
press Enter
4. The converter appears in the
list at the bottom
3
1
4
2
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Step 28: Define D2A Converter
1. Click the D2A radio button
2. Enter these parameter values
vhi = 0.95
vlo = 0.05
trise = 100p
tfall = 100p
3. Click the Add button or simply
press Enter
4. The converter appears in the
list at the bottom
5. Click the Apply button
6. We have completed our
simulation setup, close the
dialog box
3
1
4
2
2
2
2
5
6
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Step 29: Change Stimulus Model
1. Click on the
tb_FreqSynth tab
2. Select the
FREQSYNTH_STIMULUS1
instance
item: RMB->Change
Model-> VERILOG
(FreqSynth_Stimulus_Startup)
4. Rerun the simulation
NOTE:
You will notice that selecting an
instance in the Schematic
Window selects it in the
Hierarchy Window. It goes the
other way too.
2
4
1
3: RMB
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Step 30: View Updated Simulation Results
Your simulation results will
be automatically reloaded
(Click on Continue in the
EZwave Confirm window)
1. Use the EZwave browser
to plot V(clk1m), V(clk1p)
and V(clk1m,clk1p)
NOTES:
Because this is a reconfigured
simulation, the save waveform
database (swd) is no longer fully
valid. We can use the EZwave
browser, however, to plot the
waveforms.
This simulation configuration
takes between 5 to 10 minutes
to run depending on your
machine.
This concludes the Mixed Signal
Verification tutorial. Please feel
free to explore this data further
or move on to the next stage in
the Pyxis_SPT.
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Summary
Pyxis Schematic supports Mixed Signal verification by:
Providing the Pyxis Language Interface to ensure your models are
correctly compiled and registered
Allowing you to map model ports and parameters to symbol pins
and properties without making destabilizing edits
Assisting you to quickly and interactively configure designs and
view design partitions
Helping you configure and insert A2D and D2A converters
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Stage 5: Analysis of Layout Parastics
DRC, LVS,
xRC
Transistor Level
Schematics
Design Verification
Mixed Signal
Floorplanning
and
Assembly
Full-Custom
Layout
Automated
Layout
Analog
RF
Parasitic Modeling
Area Estimation
Design Capture
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Flow Overview
Tutorial
Parasitic extraction with Calibre Interactive PEX
Model registration for the EldoSpice netlist model
Simulation with Schematic and EldoSpice Model
Simulation with Schematic combined with DSPF
Debugging DSPF Parasitics using Calibre RVE
Technical Flow Summary
Agenda
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Gaps In Post-layout Flow Today Impact
Yield and Time To Market
Extraction
Extract
Parasitics
Design Environment
Select
Extracted
Spice in
Model
Selector
Simulation
GDS
Select
nets to
extract
Annotate
Parasitic to
Analog
Blocks
SPICE
Delay Calc
Calculate
Delays
SPEF
SDF
Verilog
Import
Spice
Annotate
Delays to
Digital
Blocks
Netlist
Design
Simulate
Waveform
Limited cross probing
between waveforms,
schematic and parasitics
Poor visibility of parasitic
impact of specific nets
Re-extract multiple
times for R/RC/RCC
analysis, and for
specific nets
Large netlist
slows/prevents
simulation
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Solution: Pyxis DSPF Flow
Accurate and Interactive Debugging
Pyxis
Layout /
Calibre
xRC
Extract
Parasitics
Pyxis Schematic
Questa
ADMS,
Eldo
GDS
Select
nets to
extract
Annotate
Parasitics
to Analog
Blocks
xDSPF
Delay Calc
Calculate
Delays
SPEF
SDF
Verilog
Annotate
Delays to
Digital
Blocks
Netlist
Design
Simulate
Waveform
Direct cross probing
between waveforms,
schematic and parasitics
Selectively turn on/off net
parasitics for easy debug
Extract once, re-
simulate multiple
times to perform
what-if analysis
Compact,
readable netlist
Browse detailed
net parasitics
Control degree of
back-annotation
(R/RC/RCC)
Pyxis DSPF Flow
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Overview of Tutorial
Extract
SPICE
Extract
xDSPF
Simulate
View
waveform
Simulate
View
waveform
& x-probe
to schem
Compare to
Spice accuracy
Debug:
Browse
detail net
parasitics,
do what-if
analysis,
resimulate
& identify
problem
Back-
annotate
RCC
Import
Spice
netlist
Simulate
Select
schematic
with no
parasitics
View
waveform
& x-probe
to layout
Compare to
schematic baseline
X-probe
from
waveform/
schem to
layout
and fix
problem
nets
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Flow Overview
Tutorial
Agenda
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can skip this step
NOTES:
two script files:
data
tool home directory
settings
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Step 2: Open opamp Layout
First youll need to open the
layout in read-only mode in
preparation to run Calibre
Interactive PEX.
1. Navigate to the
Pyxis_SPT / MixedSims /
opamp cell and open its
opamp layout view in
read-only mode using the
RMB (right mouse button)
popup menu
1: (RMB)
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Step 3: Launch Calibre Interactive PEX
1. In Pyxis Layout select
the pull-down menu item
Tools-> Run PEX
In the Calibre Interactive
PEX form:
2. Click on the Netlist tab
3. Enable the Export from
schematic viewer option
4. Click on the Outputs
button
1
2
3
4
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Step 4: Create Eldo Spice Netlist
2
3
5
4
6
7
In the Calibre Interactive PEX
form:
1. Specify the format to be
ELDO
2. Specify the File: name to be
opamp.pex.netlist_ELDO.spi
3. Click on the Nets tab
4. Enable the Specify Nets
option
5. Enable the Exclude: option
6. Specify to exclude VDD and
VSS
7. Click on Run PEX and OK the
Overwrite file forms to create a
new netlist and gds file
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Step 5: Create DSPF Spice Netlist
4
5
3
You should see the Calibre PEX
complete and produce an Eldo
netlist. We can create our DSPF
netlist as well.
1. Click on the Outputs
button
2. Click on the Netlist tab
3. Change the output
format to be DSPF
4. Specify the name of the
netlist to be
opamp.pex.netlist_DSPF
5. Click on Run PEX and OK
the Overwrite file forms
NOTE:
We recommend not using a .spi
or .ckt extension on your DSPF
file so it wont be confused with
a Spice format netlist.
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Step 6: View Netlists and Close Windows
You should have two netlist files
shown. Be sure to examine
these and to ensure one is in
Eldo spice format and one is in
DSPF format.
In the DSPF netlist, you will see
that each extracted net has
parasitic R, C and CC (coupled
C) associated with it. This is
what allows you to control the
degree of back-annotation and
simulation, as well as cross
probe parasitics in the last part
of this tutorial.
1. Close all of the netlist
files, Calibre PEX and Pyxis
Layout
NOTE:
This concludes the extraction
portion of this tutorial. Next
you will import your Eldo Spice
netlist using the Pyxis Language
Interface.
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Flow Overview
Tutorial
Agenda
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Step 7: Open Language Interface
1
2: (RMB)
1. Select the Pyxis SPT root
project object in your
Project Navigator window
2. With your mouse over
the Pyxis_SPT selection,
select the pop-up menu
item RMB-> Open->
Language Interface
NOTE:
This will launch the Language
Interface tool while allows you
to import Spice models and
register them to a symbol in
your design. The Language
Interface tool can also be used
to create or import HDL models,
compile them and register
compiled models to symbols in
your design
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Step 8: Import Calibre PEX Spice Model
1
2
3
In the Pyxis Language
Interface window:
1. Select the Pyxis_SPT /
MixedSims / opamp cell
menu item File-> Import->
Spice
3. In the Import Spice form,
click on the Browse icon to
specify the Spice Source
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Step 9: Browse to Model
1
2
6
In the SPICE Navigator form:
1. Click on the Browse Location Map icon
The Browse Location Map allows you to navigate
directly into soft-names defined in your projects
location map.
2. Double-click on the $PYXIS_SPT entry
3. Double-click on MixedSims (not shown)
4. Double-click on opamp (not shown)
5. Double-click on opamp.cal (not shown)
6. Select the opamp.pex.netlist_ELDO.spi
file and OK the SPICE Navigator form
NOTE:
The opamp.pex.netlist_ELDO.spi is recognized
as an mgc_spice object type because of the .spi
extension. This is why you see the mgc_spice
type icon, but not the .spi extension.
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Step 10: Specify EldoSPICE Type
1
2
1. Set the Spice Type to be
EldoSpice instead of SPICE
2. OK the Import Spice
form
NOTE:
Specifying the Spice Type to be
EldoSpice will cause the model
to be registered for use in Eldo
simulations. If you specify the
type to be SPICE, the Pyxis
Language Interface will register
the netlist for use in LVS
netlisting.
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Step 11: Check Model Registration
1. Select the opamp symbol
under the opamp cell
Language Models icon
3. Click on the Open
Command Log icon
4. If you see no errors,
close the Pyxis Language
Interface window and move
onto the next step
NOTE:
Check Language Models can be
used on the entire project to
check all of the registered HDL
and Spice language models to
ensure the registration is correct
and the HDL models are
properly compiled.
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Flow Overview
Tutorial
Agenda
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Step 12: Open Test_opampDesign Config
1
2
1. Select the Test_opamp
cell under the Pyxis_SPT /
MixedSims library
2. Select the SimMode
Design Config view
item: RMB-> Open->
Schematic Editor
NOTE:
A Design Config view is an
elaborated Design Configuration
of a schematic that can contain
additional properties,
annotations and simulation
setups. This one contains a
simple AC simulation setup for
the opamp design.
3: (RMB)
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Step 13: Run AC Simulation
1
1. Click on the Run
Simulator icon to create a
netlist and run an Eldo
simulation
NOTE:
You can find more detailed
examples on setting up
simulations in Pyxis Schematic in
Stage 4: Analog Simulation.
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Step 14: Cross-probe Output Waveform
1. After the simulation
completes, select the
output net of the OPAMP
OP.
2. Expand the Edit Toolbar
and click on the Cross
Probe Selected icon in the
Edit Toolbar
NOTE:
The Cross Probe Selected icon
will cross-probe the selected net
to Ezwave plotting it if it is not
already plotted. By default, AC,
DC and TRAN results are cross-
probed, but you can specify
which types of simulation runs
are cross-probed using the Cross
Probe Action window.
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2
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Step 15: View Results in EZwave
1. Examine the results in
the EZwave waveform
viewer
NOTE:
In this simulation, no routing
parastics are modeled. As
parastics are added using the
Eldo Spice model and the DSPF
mode, the cutoff frequency will
shift lower.
Pre-layout
schematic
simulation
Pre-layout
schematic
simulation
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Step 16: Setup EZwave to Keep Previous Results
1. In the EZWave window,
Select the pull-down menu
item Edit-> Options
2. Click on the Automatic
Reload switch
1
2
3. Specify the Keep
option with 6
Previous Result
This specifies to have
subsequent simulation
results overlay
automatically. This will
help us compare the
effects of different
levels of post-layout
extraction.
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Step 17: Change to Calibre PEX Spice Model
1. Click on the Hierarchy
Navigator icon to show the
Hierarchy Navigator
2. Select the OPAMP1
instance
the OPAMP1 instance use
your RMB to select the
popup menu item RMB->
Change Model->
ELDOSPICE(opamp)
NOTE:
The RMB popup menu in the
Hierarchy Navigator is
dynamically updated with the
models available for the selected
instances.
2
1
3 (RMB)
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Step 18: Rerun AC Simulation
1. Examine the opamp
instance in the schematic
You'll see an added
VIEW=ELDOSPICE=opamp.
The red color indicates that the
property is added on the Design
Configuration and it is either
different from the schematic
view or it is not on the
schematic view. This is often
called an annotated property.
The property name and value
are used be the netlister to
determine which model to
select. In this case it will netlist
with the newly registered
ELDOSPICE model.
2. Click on Run Simulation
The results will automatically
overlay in the EZwave waveform
viewer.
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Step 19: View Results in EZwave
1. Click on the Toggle Grid
Line Visibility to add grid
lines to the plot
the EZwave waveform
viewer
The results from the Eldo Spice
netlist show the cutoff frequency
shifting lower.
The Eldo Spice extracted netlist
flow gives accurate results, but
apart from creating and
registering multiple extraction
netlists with different levels of
extraction and different nets
excluded, it is difficult to debug
the affects of parastics on the
circuit performance. The next
steps will show how to use the
DSPF netlist to analyze and
debug your parastics.
1
Pre-layout
schematic
model
simulation
Pre-layout
schematic
model
simulation
Extracted Eldo
Spice RCC Model
Extracted Eldo
Spice RCC Model
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Flow Overview
Tutorial
Simulation with Schematic Combined with DSPF
Agenda
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Step 20: Add DSPF to Schematic Model
First you need to change your
OPAMP1 instance back to the
schematic model.
instance in the Hierarchical
Navigator
the OPAMP1 instance use
your RMB to select the
popup menu item RMB->
Change Model->
SCHEMATIC(schematic)
Next well add the extracted
DSPF netlist.
menu item Tools->
Parastics-> Add DSPF
1
2 (RMB)
3
4
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Step 21: Specify DSPF File and Options
1. Click on the Browse icon to Choose DSPF:
2. Navigate to and select $PYXIS_SPT (Remember to use the
Browse Location Map icon) / MixedSims / opamp / opamp.cal /
opamp.pex.netlist_DSPF
3. OK the Add DSPF form
1
2
3
NOTE:
The Add DSPF form allows you to specify the level
of the DSPF model (RCC, RC, CC, or C), whether to
use devices netlisted from the schematic or directly
from the DSPF file, as well as other options to fine-
tune your post-layout simulation.
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Step 22: Rerun Simulation
1. Examine the OPAMP1
2. Click on Run Simulation
NOTE:
The netlister will netlist the
OPAMP1 instance as a schematic
and an additional command is
added to the command file to
specify DSPF options and the
path to the DSPF netlist.
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2
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Step 23: View Simulation Results
the EZwave waveform
viewer
The results from the back-
annotated DSPF model should
closely match the Eldo Spice
Netlist results. But with DSPF,
you have the ability to view the
amount of parasitic capacitance
and resistance on each net using
Calibre RVE. Youll do this in the
next few steps.
Pre-layout
schematic
model
simulation
Pre-layout
schematic
model
simulation
Extracted Eldo
Spice RCC Model
Extracted Eldo
Spice RCC Model
Extracted DSPF
RCC Model
Extracted DSPF
RCC Model
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Flow Overview
Tutorial
Simulation with Schematic with DSPF netlist
Agenda
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Step 25: Show Parasitics with RVE
menu item Tools->
Parastics-> Show Parasitics
with RVE
If setup correctly, this will open
the layout in read-only mode in
Pyxis Layout and launch Calibre
RVE.
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Step 26: Highlight Net in Calibre RVE
In the Calibre RVE
window:
1. Select the Parastics
results
2. Examine the OPAMP
parastics results then select
the OP net
3. With your mouse
hovering over over the OP
net, select the popup menu
item RMB-> Highlight Net
NOTE:
This will highlight the OP net in
the Pyxis Layout window as well
as in Pyxis Schematic.
1
2
3 (RMB)
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Step 27: Highlight Net Results
1. Examine the highlighted
OP net in the Pyxis Layout
window and in Pyxis
Schematic
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Step 28: Intrinsic Parasitics with IRoute
While performing layout using
IRoute, you can view the intrinsic
capacitance on either the added
route or the entire net in real time
using the c hotkey to display the
capacitance
1. Click on the IRoute icon in
the Pyxis Layout window
2. OK the Layout Query form
to go into edit mode
3. With IRoute active, click
on the edge of the OP net
3. Enter the hotkey c twice
to display the intrinsic
capacitance for the entire net
NOTE:
The intrinsic capacitance is the
capacitance by area and
capacitance by perimeter to the
substrate. It is a rough but often
useful estimate.
1
2
3 4: c, c
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Step 29: Highlight diffn Net
How does the IRoute intrinsic capacitance
compare with the Calibre PEX extraction
results? This is an example of where the
intrinsic capacitance is higher than the
extracted results because OP is routed with
M3 stacked on M2. The intrinsic results
counts both the M2 and M3 capacitances to
the substrate without considering their
effects on each other.
Now we can look at internal nets and see
how their parasitics affect your circuit
performance.
In the Calibre RVE window under
the Parastics Results
1. Select the DIFFN net
2. With your mouse hovering over
over the DIFFN net, select the popup
menu item RMB-> Highlight Net
NOTE:
This will highlight the DIFFN net in the
Pyxis Layout window as well as in Pyxis
Schematic.
1
2 (RMB)
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Step 30: Toggle Net Parastics on DIFFN Net
You can see the effect of the
parastics on the DIFFN net by
rerunning the simulation without
any capacitance on that net
1. Select the DIFFN net
item Tools-> Parasitics->
Toggle Net Parasitics
3. Click on the Run Simulator
icon
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3
2
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Step 31: View Debug Results
You will see that the parastics on
the DIFFN net has a significant
impact on the circuit performance.
This concludes the Parasitic
Simulation and Debug tutorial.
Please feel free to continue
exploring this material or move on
to the next tutorial.
Pre-layout
schematic
model
simulation
Pre-layout
schematic
model
simulation
Extracted Eldo
Spice RCC Model
Extracted Eldo
Spice RCC Model
Extracted DSPF
RCC Model
Extracted DSPF
RCC Model
Extracted DSPF RCC
Model with parastics
on DIFFN net removed
Extracted DSPF RCC
Model with parastics
on DIFFN net removed
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Flow Overview
Tutorial
Simulation with Schematic with DSPF netlist
Agenda
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We have explored the powerful capabilities of the post-layout DSPF flow
With a single DSPF RCC extraction run, we can
simulate in any of three modes (RCC, RC, C)
without re-running extraction.
Cross-probe between waveforms, schematic and
layout to do parasitic debugging and layout ECO
Browse detailed parasitics for individual nets by
selecting the nets interactively on the schematic
Toggle parasitics on and off for specific nets to
test the impact on circuit functionality and
performance
Use the DSPF flow at block and chip level to
perform parasitic sign-off;
We verified that the post-layout DSPF flow
matches Spice accuracy very closely
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Stage 6 : Layout Viewing and Editing
DRC, LVS,
xRC
Transistor Level
Schematics
Design Verification
Mixed Signal
Floorplanning
and
Assembly
Full-Custom
Layout
Automated
Layout
Analog
RF
Parasitic Modeling
Area Estimation
Design Capture
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Stage 6: Layout Viewing and Editing
See an overview of Key Components in Pyxis Layout
Perform the following exercises using Pyxis Layout:
Perform detailed layout viewing
Get to learn the Pyxis Layout Layer Palette
Define a Layer Set
Fine Tune Layer and Context Brightness using Design
View Modifiers
Perform basic selection
Modify Your Select Filter and Cycle Through Multiple
Selections
Replace an Instance
Edit with Calibre RealTime
Move an instance with Calibre RealTime Run DRC on
Edit turned on
Delete routing and reroute with IRoute
Perform additional editing exercises
See how to setup Pyxis_SPT_Layout profile
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Key Components
The key Pyxis
Layout
components are:
a: Session Title
Bar
b: Menu Bar
c: Toolbar (one of
many)
d: Layer Palette
e: Palette Area
f: Message Area
g: Transcript Area
h: Layout Canvas
j: Tab
a
b
c
d
e
f g
h
i
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Toolbars
All Pyxis Session Windows provide detachable Toolbars (shown here detached)
Customize by user or site-wide either edit existing toolbars or create your own
Pop-up hint shows icon name
Also view icon with text or text only
(Use Setup->Toolbars->Icon, Text, Icon/ Text)
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Palette Area and Area Windows
Palette Area provides context sensitive editing
commands
Area Windows provide command log feedback to the
user
Message Area
Provides important information to the user regarding
commands and status
Transcript Area
Detailed command log and results
Area Windows
Palette Area
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Setup Preferences
All Pyxis Session Windows provide a single Setup Preferences
form enabling users to personalize their settings
Access using pull-down menu item MGC->Setup
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The Edit Object form
Similar Property Editing within Pyxis Layout and Pyxis Schematic
Edit multiple
objects with
common
properties
Automatic limit
and type
checking
Streamlined call-
back support
Invoke with
hotkey q
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Add <object> Options Form
Whenever you are adding an object path, rectangle, cell, array, device
you can bring up the options form using the q hotkey
Allows you to modify attribute and property values mid-command
q
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Hotkeys
Pyxis Hotkeys
(Selection based editing turned off)
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Strokes
All Pyxis Session Windows provide Strokes
Use MMB (Middle Mouse Button) to draw strokes
Draw ? with MMB to show available strokes
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Layer Palette
The Layer Palette enables
you to setup precise viewing
of your physical design
Easy to configure
Hotkey driven
(d loads current design layers)
User defined Layer Sets
Adjust Drawn Layer Order in
real time
Detailed information available in
the Pyxis Layout Users Manual
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Sign-off quality
DRC as you edit,
using standard
Calibre decks
No stream-out
required
Setup and Manage
DRC Checking
Recipes
Navigate and fix
errors in the
design tool
Real-time signoff DRC means better layout in less time
Pyxis Layout with Calibre RealTime Interface
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Drive Calibre RealTime with Calibre RealTime Toolbar
Use Setup->Preferences(Dockables)
or
Setup->Toolbars->Calibre Realtime
Getting started, look at
Calibre Options
Run Options
Run DRC
Run DRC on Edit (Toggles on and off)
Tooltips display Calibre DRC violations directly on layout canvas
Be sure to set Object info popup: set to Context only or Full Hierarchy in
Setup->Preferences(Behavior) form
Calibre RealTime Toolbar
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Configure Calibre Options and
create custom recipes
Calibre RealTime Options
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can skip this step
NOTES:
two script files:
data
tool home directory
settings
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Step 2: Open comparator_sb Layout
1. Navigate to the
Pyxis_SPT / GenericPLL /
comparator_sb cell and
open its layout view
NOTES:
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Step 3: Fit View and Show Layer Palette
1. Type f to fit the view
2. Click on the Layer
Palette tab to show the
Layer Palette
3. Review the Pyxis
Layout Layer Palette
Controls and Gadgets
description next slides
and use it as a reference
for the Pyxis SPT layout
modules
NOTE:
If you accidentally close the
Layer Palette, you can bring it
up again using the pull-down
menu item Setup-
>Preferences, then enabling
Layer Palette under the
Dockables section.
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Edit Mode
Use the pencil to see all layers
and modify User or Draw Order
indicates layer can be added
to loaded layer set
indicates layer can be
removed from loaded layer set
The Pyxis Layout Layer Palette Controls
Add/ Remove Gadgets
Add or remove layer
palette gadgets
User Order TAB
Shows loaded layer set in
user configurable order
Can quickly sort layers by
attribute header
Process Name
Displays the name
of the current loaded
process technology
Draw Order TAB:
Shows the current loaded
layer set in drawing priority
order
One or more layers can be
reordered in real-time when in
Edit Mode
Redraw Immediate
Toggle immediate redraw
upon layer change
Toggle Attributes on All Layers
Toggle Layer Attributes for
Selectable, Visible, Fill, Keep
Visible, and Blink
Attribute Headers
Add or Remove Layer Attribute
Headers with RMB popup menu
Sort layers with LMB click when User
Order TAB is active
Load / Save Layer Settings
Load layer settings from user
defined settings or directly
from the process
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The Pyxis Layout Layer Palette Gadgets
Layer Set
Select built-in and user defined layer sets
Create new and modify existing layer sets
Design View Modifiers
Modify layer brightness and context
contrast
Select Filter
Configure which object types are
selectable
Draw Overrides
Over-ride layer fill setting
Layer Attributes
Specify layer appearance attribute
Layer Appearance
Modify layer patterns and colors
Define new patterns and colors on the fly
Modify text colors and fonts
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Step 4: Keep CO Layer Visible
the layout canvas, enter
the hotkey Shift-f to view
all levels of data
2. Click in the K column
attribute box of the CO
layer
NOTE:
The K attribute is keeps the
layer visible regardless of the
zoom magnification. Besides
assisting in viewing physical
design details, this is enables
users to view small pins and on
a large design during the
floorplanning and assembly
phase.
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Step 5: View Single Design Layer
1. Hover your mouse over
the Layer Palette and type
the d hotkey
The layer palette accepts
hotkeys. You can see the
available hotkeys in the Dynamic
Status of the Status Line toolbar
for Pyxis Windows
2. Toggle the V attribute for
all layers
3. Click on the V column
attribute box for M1
NOTE:
You will still see system layers
showing the parameterized
device outlines and pin names.
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Step 6: Set System Layers Invisible
1. Click on the pencil to put
the Layer Palette into edit
mode
2. Enter the hotkey v twice
to set all layers including the
system layers invisible
3. Click on the V column
attribute box for M1
The layout window should show
you M1 without any system
layers.
4. Enter the hotkey v to set
all layers visible
3
2: v, v
1
4: v
NOTE:
Always return your system layers
to be visible after done viewing a
single layer.
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Step 7: Reorder Layer Drawing Priority
1. Zoom into a MOS gate
region so you can clearly see
the red POLY gate layer
crossing the gray OD layer
2. Click on the Draw Order
tap in the Layer Palette
3. In the Layer Palette, enter
the hotkey Control-f to
show the find bar
4. Enter the string OD and
click on the Find Layer button
until you see OD under
POLYG (or POL as shown)
5. Drag and drop OD on top
of POLYG and observe the
layout window
6. Return OD to the original
position and move to the
next step
4
2
3: Ctrl-f
5:LMB drag
and drop
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Step 8: Exit Edit Mode
Putting the Layer Palette into edit
mode allows you to add layers
displayed in your current layer set
by clicking on the green + and
remove layers by clicking on the
red x as well as reorder the
layers. When the User Order tab
is active you can reorder how
layers are displayed in the layer
palette. When the Draw Order
tab is active you can reorder the
layer drawing priority. You can
reorder multiple layers by
selecting them and dragging them
or by using the Cut and Paste
hotkeys (Control-x and Control-v).
You do not need to be in edit
mode to change layer colors and
fill patterns. This is covered in
the next two steps.
1. Close the Find Bar
2. Click on the green
checkmark to exit edit mode
in the layer palette
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Step 9: Set Layer Color, Line and Pattern
1. Make all layers except NW
layer invisible using the
technique shown in step 5
2. Zoom into the region
showing the NW layer
3. Setup the Layer Palette to
show Draw Overrides, Layer
Attributes, and Layer
Appearance
4. Set the divider to show the
three gadgets collapsed
using the drag and drop
stretch bar
5. Rearrange the gadgets so
Layer Attributes is on top,
Layer Appearance is in the
middle and Draw Overrides is
on the bottom
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Step 10: Set Layer Color, Line and Pattern
Specify Layer Attributes
1. Hover your mouse over the Layer
Attributes gadget
2. Select Normal to specify normal
viewing attributes
Specify Layer Pattern, Line Style
and Thickness, and Color
3. Hover your mouse over the Layer
Appearance gadget
4. Set the pattern to the triangle pattern
as shown
5. Click enable Fill
6. Select the red color
7. Click enable Line
8. Select the red color
9. Specify solid line
10. Set line width to 3
Specify Draw Override
11. Hover your mouse over the Draw
Overrides gadget
12. Select the X to override the stipple
with an X fill
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2
3
6,8
5 7
11
12
4
10 9
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Step 11: Load Saved Layer Settings
You will se the NW layers drawn
with a cross fill in shapes that are
simple rectangles.
1. Click on the Load Layer
Settings icon in the Layer
Palette
2. In the Load Layer Settings
form - Look in: field, enter
$HOME/mgc/profiles
3. Select
layer_settings.startup and
OK the Load Layer Settings
form
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2
3
NOTES:
When you click on the blue floppy
disk + in the Layer Palette, the
current layer attributes as well as
the Layer Palette gadget positions
are saved in $HOME/mgc/
profiles/layer_settings.startup
You can also select the Use
process-only option to load the
settings directly from the process.
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Step 12: Open Layer Set Gadget
You saw how to display all
layers by putting the Layer
Palette in edit mode. We can
also define a layer set comprise
of any selected layers using the
Layer Set gadget.
1. Setup the layout window
so only M1 is show (repeat
the technique outlined in
step 5)
2. Open the Layer Set
gadget in the Layer Palette
using the pull-down menu
as shown
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Step 13: Edit Layer Sets
1. Click on the Edit icon
(yellow pencil) in the
Layer Set gadget
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Step 14: Define all_layers Layer Set
1. Click on the Define Layer
Set icon
2. In the Layer Set Editor,
enter all_layers for the
Set Name and n for the
Set Alias
3. Select all Layers in the
Available Layers: area
(Use Shift-LMB or type
Control-a)
4. Click on the Add layer(s)
button and OK the form
NOTE:
This layer set shows all layers
including system layers. You
can use this set to turn off the
visibility of the system layers
remaining after step 5, but be
sure to make them visible
afterwards.
1
3: Control-a
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2
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Step 15: Finish Editing Layer Set
1. Click on the Done icon
(green check-mark) and
examine the loaded
all_layers layer set in
the layer palette
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Step 16: Open Design View Modifiers
1. Enter the hotkey v
when the mouse is over the
layer palette, (or click on
the V attribute to make the
loaded all_layers layer set
visible )
2. Open the Design View
Modifiers gadget in the
Layer Palette
3. Remove the Layer Set
and Select Filter gadgets
2
1: v
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Step 17: Change Layer Brightness
1. With your mouse
hovering over the Layer
Palette, select all layers
using by typing Control-a
2. Unselect the M2 design
layer in the Layer Palette
using Control-LMB
3. Adjust the Layer
Brightness of the selected
layers to 25% using the
gadget to accentuate M2
4. Return the brightness
to 100% for the next
Step
2: Control-LMB
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Step 18: Target Object for Selection
the buffer cell until you
see the shape targeted
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Step 19: Point Select Instance
1. Select the buffer cell
by clicking on it with your
left mouse button
2. Edit the cell in place by
typing the x hotkey
NOTES:
This will change the editing
context into the buf02 cell
You can also use your MMB
down stroke to edit the cell in
place. In Pyxis terminology,
this is called Set Context
Down
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2: x
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Step 20: Change Context Contrast
1. Verify in the title bar
that your top cell is
comparator_sb and your
current context is buf02
2. Adjust the Context
Contrast setting in the
section of the Layer
Palette and observe the
results
3. Return to the top
context by typing the
hotkey Shift-b or using
the up MMB stroke
NOTE:
The Design View Modifiers
gadget enables users to
control layer brightness and
context contrast to fine-tune
their display and debug layout
problems
2
1
3: Shift-b
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Step 21: Area Select
1. Select everything in
the using your left mouse
button to drag a selection
box
NOTE:
This will select everything
that is selectable according to
the select filter and each
layers selectability attributes
defined in the Layer Palette
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Step 22: Filter Selections using Selection Toolbar
1. Filter the selections to
be only Devices using the
Subselect pull-down menu
in the Selection Toolbar
2. Click on the Select and
Zoom icon in the Selection
Toolbar
3. Type q to bring up the
Edit Object form
NOTE:
Multiple objects will be loaded
into the Edit Object form.
Their common property and
attribute values will be shown
and where the values differ,
youll see <multiple values> in
the field.
1
2
3: q
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Step 23: Cycle Select through Selection Set
1. Click on the Cycle Next
icon in the Selection
toolbar to cycle through
the selection set
2. Click on
Cycle Previous
to go backwards and
Reset Cycle
to select the original set
3. Cancel the Edit Object
form and type the f
hotkey to view all in
preparation for the next
step
NOTES:
To assist in finding a selected
object, cycle selection has 3
display modes:
Select
Select and Zoom
Select and Center
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Step 24: Point Select Instance to Replace
1. Using your LMB (Left
Mouse Button) point
select the BUF021
instance
2. Type q to open the
Edit Object form
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2: q
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Step 25: Replace Instance
1. Click on the Replace
Cell icon of the Path
Value field
2. In the Replace Cell
form, Click on the
Browse icon
3. Navigate to and select
the GenericGates/ buf04/
buf04 layout
4. OK both all the forms
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3
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Step 26: Display Calibre RealTime Toolbar
menu item Setup->
Toolbars->
Calibre RealTime
NOTES:
When displayed, the Calibre
RealTime toolbar will
checkout a Calibre RealTime
license and start a Calibre
server session
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Step 27: Run Calibre RealTime
1. Click on the Run DRC
icon the initial results
should be clean
NOTES:
Calibre RealTime enables you
to perform layout steps and
get immediate feedback if
youve created DRC errors.
When you show the Calibre
RealTime toolbar, the Calibre
RealTime server is started
and awaits instruction from
Pyxis Layout. When DRC
verification checks are
performed, they are done
directly in memory without
the need to write data directly
to disk.
You can skip this step if you
do not have Calibre RealTime
installed.
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Step 28: Move and Align buf04 cell
1. Make sure the Run
DRC on Edit icon is active
and not grayed out
2. Select the buf04
instance
3. Type m for move,
then type c once to
constrain the move in the
x direction and v to
align the edge of buf04 to
the edge of the cell
4. When you see the
alignment markers LMB
click to finish the move
NOTE:
View operation specify
dynamic hotkeys in the Status
Line.
3 m for move
c to constrain in x
v to align to edge
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2
4
4
4
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Step 29: View Calibre RealTime Violation
1. Select the M1.S.1:2
violation in the
2. Click on the Highlight
Next icon
the DRC violation to see
the description in a
popup tip
NOTE:
If you dont see the popup
tip, youll need to set Object
info popup to Context Only or
Full Hierarchy in the Setup-
>Preferences(Behavior)
dialog.
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Step 30: Delete Routing
1. Select the M2 route
path to the A pin of the
buf04 instance
2. Holding the shift key
down, use your left
mouse button to area
select routing and vias
near the A and Y pins of
the buf04 instance
3. Type the delete key to
delete the selected
objects
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Step 31: Begin IRoute
1. Toggle the Run DRC on
Edit icon off
2. Click on the IRoute
icon and go to the next
step
NOTE:
Run DRC on Edit can be
quickly toggled on and off.
This allows users to perform
detailed routing without
intermediate errors getting in
the way.
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Step 32: Reroute with IRoute
While in IRoute, do the following steps
1. Hover mouse over thick M2 metal (M180) and LMB click on
metal
2. Bring the M2 route to the right above the A pin. You will
need to use 3 dynamic hotkeys:
The s dynamic hotkey slides the route
The 3 dynamic hotkey to go down on metal level
The v hotkey toggles the drop via type v until you see
Master path via style: Generator Subtype: default
When you see the alignment marker and the m2m1 via, LMB
click to define the point
3. Bring the route down in M1 and type shift-w to match the
with of the A pin, then finish the path by clicking on the A pin
4. Route from the FSout port to the left
5. Type 3 to go down and drop an m2m1 via and complete
the route
NOTES:
This may take a few attempts to complete for the beginner. Remember
that you can use the u hotkey to undo changes and try again.
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3
5
4
s
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Additional Viewing and Editing Exercises
1. Try the following hotkeys:
f to fit view to layout window
shift-f to view all levels
ctrl-f to view only top level
k to add a ruler
shift-k to kill all rulers
2. Try the following Add <Object> operations using hotkeys
p to add a path
r to add a rectangle
i to add an array (cell instance)
During each operation, try using the q dynamic hotkey to display the Add <Object> form
3. Try the following edit operations using hotkeys:
m to move a selected object
c to copy a selected object
s to stretch a path or an edit
During each operation, try using the v dynamic hotkey to align objects dynamically
During each operation, monitor the Status Line Toolbar to see the available dynamic hotkeys
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Saving Preferences to a Profile
Pyxis Session Windows (Layout, Schematic, Manager) can be
saved into profiles using Setup->Profiles->Save As
All profiles are kept in the $HOME/ mgc/ profiles directory
The profile loaded at the end of the last session is always loaded
in the new session
NOTE: Profiles are used in the Pyxis SPT to pre-configure the tool with $HOME mapped to a location
within the tutorial data
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Loading a Saved Profile
Multiple Profiles can be stored and loaded during a Pyxis session
using Setup->Profiles->Load
`
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Auto-Save Profile Option
Users can specify which if any settings to automatically save into
the profile
NOTE: In order to always return the GUI to a known state, all Pyxis_SPT profiles have
Auto-Save turned off
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Recreating the Pyxis_SPT_Layout Profile
This is a list of steps to create the Pyxis_SPT_Layout profile that was used by default in
this tutorial
1. Select the pull-down menu item Setup->Profiles->Restore Default
This returns the tool to the default or Classic setup
2. Select Setup->Preferences
2.1. In the Editing Section, turn off Selection-based editing
2.2. In the Editing Section, turn on Extend path ends on move
2.3. In the Editing Section, turn on Graphical Device Editing
2.4. In the Editing Section, consider turning off Mouse drag and drop
2.5. In the Behavior Section, turn on Target Object
2.6. In the Behavior Section, turn off Popup menu (RMB)
2.7. In the Behavior Section, set Object info popup: to Context only
3. Configure Toolbars and Windows using Setup->Preferences (Dockables Section)
3.1 Enable Transcript Area
3.2 Enable SDL Toolbar
4. Relocate the toolbars and windows to your liking
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Summary
Layout Viewing and Editing in Pyxis Layout
Fine Tune Your Layout Canvas
Setup Layer Sets for different phases or your design
Apply Design View Modifiers to brighten and dim Layers
Object Editor with Cycle Selection
Cycle and zoom to or center multiple selections
Apply changes to multiple objects
Perform Edits using Calibre RealTime with Run DRC on Edit
Customize your layout session to meet your needs
Pin, undock or collapse toolbars, palettes and area windows
Save and load user defined profiles
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Stage 7: Floorplanning and Assembly
DRC, LVS,
xRC
Transistor Level
Schematics
Design Verification
Mixed Signal
Floorplanning
and
Assembly
Full-Custom
Layout
Automated
Layout
Analog
RF
Parasitic Modeling
Area Estimation
Design Capture
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See a brief overview the
floorplanning and assembly
capabilities in Pyxis Assemble
Perform the Following Tasks
using Pyxis Assemble
Perform Area Estimation on
Hierarchical Design
Customize Shapes while
Constrained to Block Area
PerformAutoplace Pins
Setup Left/Right,
Top/Bottom Metal
Placements and Place Pins
on All Blocks
Setup and perform iterative
top-level routing using IRoute
and ARoute
Perform Calibre DRC and LVS
at the floor-planning stage
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Floorplanning with Pyxis Assemble
Automatic area estimation
of the full hierarchy based
on transistor level
schematic
Interactively define block
boundaries with real-time
feedback on area
attributes
Automatically place pins
on all or selected blocks
Optimizes pin placement
for shortest route
Constrains pins on layer,
direction, pitch according
to your chip assembly
methodology
View and Manage Design Hierarchy
Cross select blocks to schematic and layout
Flatten or create hierarchy
Display and select unplaced block pins
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Automated Routing with ARoute
Fast and Interactive
Customize Block Level
Automatic Routing
Solution and Reuse as
Blocks are implemented
Routing Control
Setup keep-in / keep out
regions
Route selected nets or
entire chip
Flexible blockage control
Constraint-driven
Layer directions
Cost per unit length
Variable width/spacing
Auto shielding
Productivity Features
Batch routing
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Interactive single signal or
bus routing
Constraint-driven
widths, layer/net spacing,
shielding
On-the-fly visual feedback
R/C/length
Push blocking vias and jog
blocking metal routes
Correct-by-construction
ensures DRC and LVS correct
results
Symmetric/mirrored
IRoute Options Window
Interactive Routing in IRoute
DRC correct route jogs
Interactive bus routing
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Supports inline and turn
constraints with automatic via
selection and via rotation in IRoute
and ARoute
Rules enforce multi cut vias
Supports adjacent cuts of 3 & 4
Via cut size, metal overlap and
width can be defined based on via
width
DFM via classes can be defined
and specified for use
Cut spacing
Advanced Via Rule Support
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Generalized Mixed Signal PLL containing both Analog and Digital
Components
Differential VCO runs from 600MHz to 1.2GHz
Prescaler halves VCO frequency and converts differential signals to single-ended
Digital M and N-Dividers to control output frequency - FO = FR(N/M)
Frequency Synthesizer Circuit
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can skip this step
NOTES:
two script files:
data
tool home directory
settings
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Step 2: Create a New FreqSynth Layout
inside of the
TopDown_Floorplan
category of the GenericPLL
library
2. Click on the New Layout
icon
3. OK the New Layout form
using the default entries
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Step 3: Turn On Device Area Estimation
1. Click on the Logic Loading
options button in the New
Layout form
2. In the Create Cell: Logic
Loading Options for EDDM
form, enable Device area
estimation
3. Set the Viewpoint type to
Hierarchical
4. Add area to the list of
Copy: Logic Properties list
and OK both forms
NOTE:
Pyxis will evaluate the primitive
devices in each level of the
FreqSynth hierarchy to estimated
the size. This can be overridden
by using the area property.
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Step 4: View Loaded Logic
After loading all of the logic,
Pyxis Layout will show two
windows - the layout canvas
and the logic window in
TABBED mode. Initially the
schematic will be displayed as
shown.
1. Click on the far left Tab
which is attached to the
FreqSynth cell on the
layout canvas
NOTE:
Pyxis Layout is context
sensitive. Menus, toolbars,
palettes as well as hotkeys
and strokes automatically
adjust to present applicable
functionality depending on
the current context.
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Step 5: Begin Plan & Place
1. Click on Plan &
Place button under
Pyxis Assemble in the
IC Palettes window
NOTE:
The IC Palettes window
organizes key commands
depending on the design
phase. Clicking on the
Plan & Place button
displays commands that
will be needed for IC
Floorplanning and
Placement.
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Step 6: Autoplace All Blocks
1. Click on the Blocks
button under the Auto
Placement section of
the Plan & Place
Palette
2. In the BPlace form,
set the Orientation
constraints to Normal
orientations and OK the
form
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Step 7: Set Block Area
instance
2. Click on the
BlockArea button in the
palette
3. Lock the Width and
Height Attributes
4. Change the Width to
60 and then click the
Calculate button and
OK the form
NOTE:
The Set Block Area form
allows you to set key
attributes for you
floorplanning shape and
have other attributes
calculated automatically.
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Step 8: Arrange Blocks
1. Using the m hotkey
and v hotkey for
dynamic alignment,
loosely arrange the blocks
as shown
NOTE:
Dynamic Align (v hotkey) is
a setting available during most
editing operations that aligns
the object being moved to
other objects in the layout.
Other hotkeys available during
move, placement and copy are
c to constrain the direction.
f/F for flip, r/R for rotate
and d/D for drag ruler. The
available hotkeys for a given
command are shown in the
status window.
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Step 9: Set Cell Origin
menu item Context ->
Layout -> Set Origin:
2. Using Dynamic Align,
select the lower left hand
corner of the DIV_BY_N1
block
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Step 10: Align Blocks with Offset
1. Select the
PRESCALER1 instance
2. Select pull-down
menu item Edit->Align
3. Click on the
DIV_BY_N1 block for
the reference
4. In the Align form,
select Left to Right with
an offset of 10 and OK
the form
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Step 11: Create Custom Block Shape
1. Select the pfd Instance
2. Click on the Draw button
in the Boundary section of
the Plan & Place palette
3. Draw a box as shown
using the v hotkey to
align new shape and the d
hotkey to display the new
shape area (be sure that
the new area is greater
than 100%)
NOTE:
Floorplanning blocks can
instantly be reshaped with area
displayed this is a must have
for Custom IC floorplanning.
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Step 12: Open Hierarchy Window
1. Select the menu item
Windows ->
Hierarchy Window
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Step 13: Setup Quadrant Tiling
menu item MGC->Setup
2. In the General section of
the Setup Preferences form,
set the View to Default
and the Window Layout to
Quadrant Tiling as shown,
then OK the Setup
Preferences form
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Step 14: Multi-Window Selection
Pyxis allows you to select
objects from the Layout,
Logic, or Hierarchy windows
1. Select the DIV_BY_M1,
FILTER1 and PRESCALER1
instances in the Hierarchy
Window and examine the
display in the other windows
2. Close the Pyxis Layout
window and move onto the
next step
NOTE:
Each window provides a different
palette for viewing and operating
on your design.
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Step 15: Open Pre-Floorplan Layout
1. Open the pre-floor-planed
FreqSynth layout inside of
the TopDown_Assembly
library
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Step 16: Open Logic Window
menu item Windows ->
Logic
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Step 17: Select all Blocks
1. Click on the far left Tab
to show the layout canvas
again
2. Area select all blocks
3. Click on the Plan & Place
button in IC Palettes
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Step 18: Autoplace Pins
1. Click on the Auto
Placement Pins button
to invoke the Autoplace Pins
command
2. In the Autoplace Pins
form, set the Left/Right
Level to by M4 and the
Top/Bottom Level to be M5
3. Enable the Selected
Instances and Optimize
through hierarchy options
and OK the form
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Step 19: Open Route Palette
1. Click on the Route
button in the Plan & Place
Palette
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Step 20: Setup ARoute
1. Click on the Direction
button under the Aroute
Setup section of the ARoute
Palette
2. In the Set Preferred
Routing Direction form, turn
on only M2, M3, M4, M5 and
M6 levels and set the
Direction entries to
Horizontal 1
st
3. If showing Overflows
instead of Nets, click on the
Overflows button and set it
to Nets
4. Click on the Run button
under the ARoute Commands
section
NOTE:
The directions and Route Nets
settings will likely already be set
by your startup profile.
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Step 21: ARoute Results
1. Examine the displayed
routing results as well as
the Transcript Area Window
for detailed information on
ARoute command
2. Close the Pyxis Layout
window and continue to
the next step
NOTE:
Shown are initial results after
performing basic routing. In
further floorplanning stages, we
need to account for setting up
instance route blockages and
customize the pin positions.
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Step 22: Open Routing Layout
FreqSynth layout inside of
the TopDown_Routes category of
the GenericPLL library using the
popup menu item:
RMB->Open->Layout Editor
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Step 23: Run Calibre DRC
item Tools->Calibre->Run
DRC
2. In the Calibre Interactive
form, click on the Run DRC
button
NOTE:
The DRC run is automatically set
up with the correct stream out file
and Top Cell name. The rule deck
is specified by the Technology
Configuration that is used by the
Pyxis_SPT project.
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Step 24: Show M4 Spacing Error
1. In the Calibre RVE window,
toggle the pull-down menu
setting View->Tree Options-
>Show Empty Checks
The M3.A.1, M4.A.1, and M5.A.1
violations are via metal island
errors. These can be addressed
manually or by post-processing in
Pyxis or Calibre and we will skip
them in this tutorial.
2. Select the M4.S.3 check and
select the RMB (Right Mouse
Button) pop-up menu item
RMB->Highlight
3. Examine the highlighted
spacing error
NOTE:
This wide metal spacing error can be
avoided by setting process override
for the cell or setting up a spacing
constraint for the net. Ask your
Mentor contact how to do this.
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Step 25: Slide Route
1. Select the wide M4 path
2. Click on the Slide Route
icon
3. Drag the M4 path away
from the violation
NOTE:
Slide Route allows you to quickly
make routing adjustments without
worrying about the attached vias.
You can also push and jog existing
routes and vias to make room for
the new route location.
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Step 26: Open Calibre LVS Interactive
item Tools->
Calibre -> Run LVS
2. Do not click the "Run LVS"
button yet. Youll need to do
some setup first. Proceed to
the next slide
NOTE:
As with Calibre DRC Interactive,
the LVS run is automatically set up
with the correct stream out file,
exported source netlist and Top
Cell names. The LVS rule deck is
specified by the Technology
Configuration that is used by the
Pyxis_SPT project.
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Step 27: Setup Floorplan LVS Run
1. For Inputs:H-Cells, Turn on Match
cells by name (automatch) and Use H-
Cells file: and use the hcells file name
2. For LVS Options:Supply, set the Power
nets and Ground Nets as shown
Use the pull-down menu item:
Setup->LVS Options to see the LVS
Options section
Power nets: vdd vdd_cp vdd_vco vdd_ps
Ground nets: vss vss_cp vss_vco vss_ps
3. For the LVS Options:Include section,
type in svrf.includes
4. Click on the Run LVS button
NOTE:
The svrf.includes file uses the LVS BOX
command to specify empty cells in the layout
and schematic. In this run, only the routing will
be checked.
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Step 28: Highlight Net Discrepancy
1. In the Calibre RVE
window, expand the
Comparison Results
2. Select one of the
discrepancies and use the
RMB (Right Mouse Button)
pop-up menu item RMB-
>Highlight Net to highlight
the net in the Layout
NOTE:
There are unfinished routes, so
this run is not clean. In the next
few steps, we will finish them and
rerun Calibre LVS.
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Step 29: Select Overflows
1. Expand the IC Palettes,
select the Route button, then
click on the SOvrf button to
select all Overflows
An Overflow my also be referred to
as a fly line. It is a point to point
representation of connectivity that
has not been routed
2. Examine the Select count in
the Status Toolbar
NOTE:
The Select Overflow command
shows which routes are unfinished.
When used in a Correct by
Construction environment like Pyxis
with ICassemble, it can be used as
a fast LVS check.
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Step 30: Zoom to Ctrl Busses
1. Use your RMB (Right
Mouse Button) to zoom
into the ctrl busses on the
left
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Step 31: Set Preferred Routing Direction
1. Click on the Direction
button under the Aroute
Setup section of the
ARoute Palette
2. In the Set Preferred
Routing Direction form,
turn on only M2, M3, M4,
M5 and M6 levels and set
the Direction entries to
Horizontal 1
st
3. Area select the upper

four ports of the 4-bit bus
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Step 32: Select Four-Bit Bus Ports Nets
item Select->On Selected:
2. Make sure the SEL_ON_S
prompt value shows net
and OK the prompt or type
enter
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Step 33: ARoute Selected Nets
1. Click on the Run
button in the ARoute
Commands section of the
ARoute palette
NOTE:
When there are nets selected,
ARoute will only route the
selected nets, otherwise,
ARoute will attempt to route all
unfinished nets.
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Step 34: Open IRoute Options
Next we will use IRoute to
interactively route the 8-bit bus
1. Open the Setup Preferences
form by selecting the pull-down
menu item MGC->Setup
2. In the Dockables section,
enable the IRoute Options entry
3. If you prefer, you may detach
the form as shown, otherwise, be
sure it is pinned and visible for the
next few steps
NOTE:
IRoute is hotkey driven. The IRoute
options form makes it easy to see the
status of your current route as well as
help new users access IRoutes full
potential.
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Step 35: IRoute Select Bus Ports
under the IRoute Commands
Section of the ARoute palette
2. Area select the 8 bits as
shown
NOTE:
IRoute will display the selection as
the area as drawn. Additionally,
IRoute can be used to probe net
attributes before beginning a new
route.
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Step 36: IRoute - Change Route Level
1. Drag the Route to the right
2. Type 4 to increment the
layer by 1 level up to M5
3. Type Shift-V to stagger the
Via Pattern to the diagonal_2
setting
4. Move the drop vias above
the bus pins on the div_by_n
block until you see the finish
route alignment area
5. Do a LMB click to drop the
vias and bring the M5 routes
down to the targets
NOTE:
When routing a bus, the first net
selected becomes the Master Wire
and is what is used to display details
on the route in progress.
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Step 37: IRoute Finish Bus Route
1. Click to finish the bus route
when you see the check
mark.
NOTE:
By default, IRoute will fan-in
busses and taper them to fit the
target pitch even if the target
pitch is not uniform as is often the
case in custom IC layout.
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Step 38: Route Single Net
1. Click on the IRoute icon
in the SDL toolbar.
2. Select the RESET pin of
the div_by_n block as
shown
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Step 39: Push and J og Existing Routes
1. Use the j hotkey to
enable the Allow J ogs
settings and the p hotkey
to set the Push Mode
setting to two direction
or do this directly in the
IRoute options form
2. Route the M4 signal
into the bus as shown
NOTE:
By default, only 10 routes are
pushed. This can be increased
by changing the Max number
of pushes IRoute setting.
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Step 40: Cleave Existing Bus
1. Use the backspace key to
undo a route point
2. Type 4 to increment the
route to M5
3. Drop an M4M5 via and bring
the M5 route upwards
4. Type 3 to decrement the
route down to M4
5. Drop an M4M5 via in the 4-
bit bus as shown and bring the
M4 route to the right
6. Type 4 to go to M5, drop
the via as shown and finish the
route
NOTE: For first-time users, this
usually takes a few attempts, so
dont be discouraged. J ust enter the
u hotkey to undo and try again.
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Step 41: Zoom to Analog Signal
1. Zoom into the analog
current reference signal using
diagonal MMB (Middle Mouse
Button) Stroke
NOTE:
When called from the SDL Toolbar,
the IRoute command will remain
active for successive routes until it
is canceled.
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Step 42: Display Routing Parasitics
1. Start an IRoute from the
iref_400u port
2. Type 4 three times to
increment from M2 to M5 and
drop the stacked via as
shown
3. Type c to show the net
capacitance and o to show
the route resistance
NOTES:
IRoute can also be used to
probe the total net capacitance
of an existing route.
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Step 43: Finish Route
1. Complete the last section
of the iref_400u route in M4
as shown
NOTES:
Use the 3 hotkey to decrement
from M5 to M4.
The hotkey Shift-A will complete
a single net IRoute in progress
using the current ARoute settings.
Notice the widths of the iref_400u
path segments. You may want to
ask your Mentor contact how
these widths are set.
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Step 44: Rerun Calibre LVS
1. Click on the SOvrf button
in the ARoute palette and
look at the select count.
If it is 0, then we are done
and probably LVS clean. To
verify, we can rerun Calibre
LVS
2. Rerun Calibre LVS and
examine the results
This concludes the
Floorplanning and Assembly
tutorial. Please feel free to
continue exploring this material
or move on to the next tutorial.
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Summary
Floorplanning and Assembly using Pyxis Assemble
Achieve fast and accurate results to plan your design
Automatic area estimation
Customize floorplan shapes while constrained to estimated block area
Optimize pin placement to reduce routing interconnect
Route early, route often with ARoute
Create routing solution at floorplanning stage
Signal routes are constrained to width and spacing per layer
Use IRoute for interactively routing detailed routes
Interactively route signal busses with different source and target pitches
Avoid obstacles with DRC and LVS clean pushing, jogging, sliding
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Stage 8: Schematic Driven Layout
DRC, LVS,
xRC
Transistor Level
Schematics
Design Verification
Mixed Signal
Floorplanning
and
Assembly
Full-Custom
Layout
Automated
Layout
Analog
RF
Parasitic Modeling
Area Estimation
Design Capture
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Perform the Following Tasks using
Pyxis SDL
Create a new layout using the cell
schematic for connectivity
Place transistors from the schematic and
from the LDL Cockpit
Map layout devices to schematic instances
using the LDL Cockpit
Run Calibre RealTime DRC with Run DRC
on Edit turned on and turned off
Place ports on layout and fill VDD / VSS
ports with shape based nwell / psub vias
Complete routing interactively with IRoute
Add text on ports and run Calibre LVS
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can skip this step
NOTES:
two script files:
data
tool home directory
settings
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Step 2: Copy buffer cell from MixedSims
2
1. Navigate to and select
the buffer cell in the Mixed
Sims library of the
Pyxis_SPT project
2. Use your Right Mouse
Button to select the popup
menu item: RMB->Copy
NOTE:
The buffer example created in
Stage 2 of this tutorial could be
used as well.
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Step 3: Paste buffer cell in GenericPLL
2
1. Select the GenericPLL
library in the Pyxis_SPT
project
2. Use your Right Mouse
Button to select the menu
item - RMB->Paste
NOTE:
In Design Manager you can
also use hotkeys Control-c and
Control-x to copy and cut and
Control-v to paste.
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Step 4: Create new buffer layout
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1. Refresh the project to
make sure the buffer cell
appears under the
GenericPLL library
2. Select the buffer cell
under the GenericPLL
library and select RMB->
New->Layout
3. OK the New Layout form
with the default entries
NOTE:
This will launch Pyxis Layout
and request that a new Layout
view be created for the buffer
cell.
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Step 5: OK New Layout Default Options
1
1. Examine the New
Layout form, then OK the
form with the default
entries
NOTES:
The New Layout form enables
users to create a new layout
with our without schematic
(Logic) connectivity.
By default, the Logic source is
set to the component which
means is uses the default
schematic under the cell.
The cell name is pre-populated
based on the information from
Design Manager.
The Process and Rules (SDL
Rules) are set by the projects
Technology Configuration.
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Step 6: Setup SDL Options
1. Click on the Setup SDL
icon in the SDL toolbar
2. Set the Action when
name not found setting to
Prompt user and OK the
Setup SDL form
NOTE:
Setup SDL enables you to
modify how Pyxis Layout maps
schematic instances to layout
cells and parameterized device
generators. Additionally, it
controls how cells in the
hierarchy are created. We
wont need to change any
Setup SDL options for this
simple tutorial, but for more
complex SDL designs, be sure
to review Chapter 3 Schematic
Driven Layout the Pyxis
Layout Device Level
Automation (DLA) Manual.
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Step 7: Select M1 on Schematic
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2
1. Select M1
2. Click on the Inst
button in the DLA Logic
Palette
NOTE:
When starting and SDL Layout,
the schematic Tab is initially set
active. From here you can
select instances and instantiate
Inst them to the Layout
Canvas. When instantiated this
way, connectivity information
will be added to the objects in
the layout to assist placement
and routing.
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Step 8: Place M1 Device on Layout Canvas
1
2
1. Place the M1 device in
the layout with an LMB
mouse click
NOTE:
Once the instantiation is
complete, the schematic Tab
will become active again
allowing you to instantiate
more devices.
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Step 9: Select M2 on Schematic
1
2
1. Select M2
2. Click on the Inst
button in the DLA Logic
Palette
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Step 10: Zoom and Pan in Pyxis Layout
1. Use your middle mouse
button to zoom on the
layout
In mid-command zooming and
panning can be performed by
doing a MMB stroke or using
your mouse wheel.
2. Take a moment to
become familiar with
zooming and panning
using your middle mouse
scroll wheel before moving
to the next step
NOTES:
Pyxis Layout recognizes inputs
from the mouse scroll wheel in
most of its forms.
Shift +
Control +
Zoom-In
Zoom-Out
Pan Horizontal
Pan Vertical
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Step 11: Place M2 on Layout Canvas
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2
1. Use the dynamic hotkey
v to turn on alignment
the layout to the right of
and aligned to M1 with an
LMB mouse click
NOTE:
The dynamic hotkeys available
for a command are displayed in
the Status toolbar.
In preparation for the next
step
menu item MGC-> Setup
4. Set the View to
Default with the Window
Layout to Left Right
Tiling and OK the Setup
Preferences form
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Step 12: Cross Selection in SDL
1. Select M1 in the
schematic and see it
selected in the layout
2. Show the Layer Palette
3. In the Select Filter, enter
Control-a to clear the
selectable objects
4. In the Select Filter, enable
Devices to be selectable
5. LMB point select the M2
PMOS device on the layout
and see it selected in the
schematic
6. In the layout, enter the
hotkey j or select the pull-
down menu item Windows->
LDL Cockpit to display the
LDL Cockpit
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3: Ctrl-a
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Step 13: Cross Selection with LDL Cockpit
1
1. Select M1 in the LDL
Cockpit and see the
corresponding objects
selected in the layout and
schematic
NOTES:
The LDL Cockpit provides an
interactive listing of the
instances in the layout along
with the connections to their
pins. In the absence of a Pyxis
Schematic, the LDL Cockpit can
be used to place instances
from a spice netlist connectivity
source.
The LDL Cockpit can also be
used to map instances and
instance connections.
In the next steps, well show
how to place an instance from
the LDL Cockpit as well as map
an parameterized device in the
layout to an instance in the
layout.
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Step 14: Place Instance with LDL Cockpit
1. Select M4 in the LDL
Cockpit and then select the
pop-up menu item RMB->
Place Instance
2. Click on the Title Border
of the Pyxis Layout
window to make it active
3. Use the dynamic hotkey
v to turn on alignment
the layout below and
aligned vertically to the M2
PMOS device
5. Maximize the layout
window for the next step
1 (RMB)
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Step 15: Copy Device Instance
1. Select M4 on the layout
2. Enter the hotkey c to
perform a copy
3. Place the copied
instance to the left of M4
as shown
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Step 16: Edit Copied Device Instance
1. With the copied instance
selected, enter the hotkey
q to open the Edit Object
form
2. Change the sequence to
cgc to specify only one
finger
NOTE:
On most PDKs, the number of
fingers for the device is
specified directly by a nf or
fold property. This PDK is
older and uses the sequence
property.
3. Change the name
attribute to copied
4. OK the Edit Object form
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Step 17: Map Instance in LDL Cockpit
1. In the LDL Cockpit,
enter the hotkey Control-r
or select the pull-down
menu item View->Refresh
to refresh the window
2. Holding your Shift key
down, LMB point select the
copied instance device and
M3
item: RMB->
Map Instances > M3
4. Observe the copied
device it should now be
mapped to M3 and have
overflows indicating the
pin connections. Leave it
selected for the next step
1: Ctrl-r
2: Shift-LMB
2: Shift-LMB
3 (RMB)
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Step 18: J oin M3 and M4
1. Enter the hotkey m to
begin the move operation
2. During the move enter the
hotkey f to flip the device
3. Place M3 so that its
source drain area overlaps
the source drain area on the
far left of M4
NOTES:
We did the flip so we could have
the overlapping source drain
areas of M3 and M4 be on the
same net which will allow them
to be joined into a composite
device.
If the devices do not join it may
be because either the source/
drain areas are not connected to
the same net or the J oin MOS
devices on MOV/PLACE setting is
not enabled in your Setup
Preferences.
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Step 19: J oin M1 and M2
1. Repeat the last two
steps to going M1 and M2
into a composite device
(be sure to flip the device
so the source/drain
connections line up)
NOTES:
The rest of the tutorial
assumes that the M1, M2
composite device is aligned
vertically with the M3, M4
composite device. You may
want to try moving one of the
devices and aligning it vertically
to the other using the v
hotkey for align.
You can use undo (Hotkey u)
to undo your changes from the
last two steps and try again if
necessary.
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Step 20: Load Calibre RealTime
menu item Setup->
Toolbars->
Calibre RealTime
NOTES:
Calibre RealTime enables you
to perform layout steps and get
immediate feedback if youve
created DRC errors.
When you show the Calibre
RealTime toolbar, the Calibre
RealTime server is started and
awaits instruction from Pyxis
Layout. When DRC verification
checks are performed, they are
done directly in memory
without the need to write data
directly to disk.
You can skip this step if you do
not have Calibre RealTime
installed.
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Step 21: Run Calibre RealTime
1. Click on the Run DRC
icon to see Calibre
RealTime results
2. Expand the Error Result
list to see what errors have
been found
3. Hover you mouse one of
the errors to see a popup
of the violation description
4. When you are done
viewing errors, clear all
errors by clicking on the
NOTE:
The LAT.3P and LAT.3N errors
are due to the MOS devices not
having a proper tie to their
back gates. We will fix these
by placing the vdd_imp and
vss_imp ports.
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Step 22: Place Ports from Schematic
1. Click on the buffer
schematic Tab
2. Click on the Port button
in the DLA Logic palette to
add all the buffer ports
NOTES:
The Port button in the DLA
Logic palette will enable you to
place all of your ports in the
metal layer you want. As you
place each port, the existing
net connectivity is highlighted
to guide youre placement.
You can change the metal layer
using the hotkeys 3 to go up
a level and 4 to go down a
level.
In the next step, youll place all
the ports in M1 and use the
dynamic align v to snap the
ports to objects on the layout.
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Step 23: Place Ports on Layout
1. Use the 3 and/or
4 hotkey to change
the port to M1
2. Enter v for align
3. Place the Ain port
snapped to the lower
left corner of the
PMOS composite
device
4. Turn on alignment
and make sure the port
is in M1
5. Place the vdd_imp
port snapped to the
upper left corner of the
PMOS composite device
3
1: 3 or 4
2: v
5
7
9
and make sure the port
is in M1
7. Place the vss_imp
port snapped to the
lower left corner of the
NMOS composite
device
and make sure the
port is in M1
9. Place the Zout port
snapped to the lower
right corner of the
PMOS composite
device
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Step 24: Final Port Placement
1. Fit the layout in the
window using the f
hotkey and examine the
changes
2. If necessary adjust the
layout to match as close as
possible to the picture on
the left before continuing
to the next step
NOTE:
Now that the vdd_imp and
vss_imp ports are placed, we
can modify them and add back-
gate connections to the MOS
devices.
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Step 25: Stretch vdd_impM1 Port Shape
1. Turn on Shape in the
Select Filter gadget
2. Zoom into the area
surrounding the vdd_imp
port shape
3. Type s to start the
stretch command
4. Select the upper right
corner of the vdd_imp M1
port shape
5. Enter the v hotkey to
turn on alignment
6. Stretch the vdd_imp
port shape so that it spans
the width of the PMOS
device and it is about
0.8um taller using the LMB
mouse point click
4
1
3: s
6
5: v
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Step 26: Stretch vss_impPort Shape
1. Similar to the previous
step, stretch the vss_imp
port shape so that it spans
the width of the NMOS
device and it is about
0.8um taller using the LMB
mouse point click
NOTE:
By default, Pyxis will use the
existing default schematic for
the Logic connectivity source.
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Step 27: Run Calibre RealTime DRC
1. Run Calibre RealTime
and view the results
NOTES:
You should still see the LAT
errors. We will fix them in the
next two steps
(in preparation for the next
step)
2. Select the vdd_imp port
shape
3. Click on the IC Palettes
Tab
4. Click on the DLA Device
button in the IC Palettes
palette
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Step 28: Add m1psub VIA to vss_impPort
1. Scroll down the DLA
Device Palette using your
middle mouse wheel and
expand the Via* sub-menu
to select Via*->Fill
Selected
2. In the ICdevice Shape
Via form, select m1psub
3. OK the form
4. Enter the Shift-f
hotkey to display the
contents of the added
via
NOTE:
This will place a shape-based
via device within the selected
object shape.
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4: Shift-f
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Step 29: Add m1nwell VIA to vdd_impPort
1. Turn on the Run DRC
on Edit icon
2. Select the vdd_imp port
shape
3. Select Via*->Fill
Selected from the DLA
Device Palette
4. In the ICdevice Shape
Via form, select m1nwell
and OK the form
5. Enter the Shift-f
hotkey to view the
contents of the added via
NOTE:
You should see the LAT rule
violations disappear due to the
edits adding a proper back gate
connections.
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Step 30: Begin IRoute
1. Clear the DRC error
markers by clicking on the
Clear All Highlights icon
2. Turn off Run DRC on
Edit
to begin IRoute
NOTE:
The Calibre RealTime Run DRC
on Edit switch enables users to
quickly turn on and off Calibre
RealTime check depending on
phase of the design.
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Step 31: Route vdd_impConnections
With IRoute active:
1. Click on the top of the
source pin connected to
vdd_imp
2. Enter the hotkey Shift-
w
3. Click on the vdd_imp
port to finish the route
4. Click on the other
vdd_imp source pin
5. Enter Shift-w
6. Click on the vdd_imp
NOTE:
When invoked from the SDL
Toolbar, IRoute remains active
and allows you to add multiple
routes sequentially.
1
2: Shift-w
3
4
5: Shift-w
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Step 32: Route vss_impConnections
With IRoute active:
1. Click on one of the
NMOS source pins
connected to vss_imp
2. Enter Shift-w
3. Click on the vss_imp
4. Click on the other NMOS
source pin connected to
vss_imp
5. Enter Shift-w
6. Click on the vss_imp
NOTE:
We can view all available
IRoute options in the IRoute
Options Window.
3
2: Shift-w
1
4
5: Shift-w
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Step 33: Show On Iroute Options Window
menu item Setup->
Windows-> Iroute Options
NOTES:
The IRoute Options window on
the next slide displays all of the
available options for IRoute
along with the associated
hotkey.
The IRoute Options window is
interactive, allowing beginners
to modify settings directly on
the window without entering
the hotkey. As users become
more familiar with IRoute and
its capabilities, they generally
drive it interactively using
hotkeys.
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Step 34: Route Zout Signal
1. Stretch the IRoute
Options window to view
the three columns
With IRoute active:
2. Click on the PMOS drain
pin connected to Zout
3. Move the route down in
M1 and type Shift-w
Observe the Taper Wire
Width state in the IRoute
Options window
4. Finish Routing the drain
connections in M1 and
gate connections in POLYG
prior to moving to the next
step
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Step 35: Route Ain Signal
With IRoute active:
1. Click on the POLYG
route connected to Ain and
route it left towards the
Ain port shape
2. Enter the hokey s to
set the Slide Mode to
Single Edge Slide
3. Bring the horizontal
route upwards and
downwards
NOTE:
Slide Mode allows you to adjust
your previous route point as
needed to complete you route.
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3
2: s
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Step 36: Dropping VIAs and Pushing
1. Enter hotkey 4 to increment the
routing layer and load a POLYG to M1 VIA
2. Position the VIA under the Ain port
shape so you see the completion arrow
and drop the VIA with a LMB click
4. Complete the Route to the Ain port
shape
5. Start and IRoute from M1 path shown
6. Enter hotkey 3 to decrement level
7. Enter Control-v to set the via size
8. Set the width and height to 2 and
specify its for the Number of contacts
9. Enter the p hotkey until Pushing is set
to two directions
10. Push the existing M1 routes out of the
way and drop the 2x2 POLYG to M1 VIA
1: 4
2
3
5
6: 3
7: Ctrl-v
9: p
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Step 37: Completed Layout
1. Finish Routing the gates and drains of the
last stage of the buffer
NOTE:
You should have a result similar to what is shown. If
not, dont hesitate to hit the u hotkey to undo changes
and start again.
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Step 38: Add Text on Ports
menu item Add->Text on
Ports
2. OK the Add Text on
Ports form with the default
entries
NOTE:
Add Text on Ports will add port
text to you layout to prepare it
for Calibre LVS. This command
will remove all existing text
that was added from a previous
Add Text on Ports command
and add new text on the
current port positions. If you
do move a port, you do not
need to keep track of moving
the text along with it. You
simply run Add Text on Ports
prior to performing a new
Calibre LVS run.
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Step 39: Launch Calibre Interactive LVS
menu item Calibre->
Run LVS
2. In the Calibre
Interactive nmLVS
window select the pull-
down menu item Setup->
LVS Options
NOTE:
The Calibre Interactive
nmLVS form will be
automatically loaded with the
correct design, run directory
and LVS rules specified by your
projects Technology
configuration.
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Step 40: Specify Power and Ground Nets
1. Enter vdd_imp for the
Power nets
2. Enter vss_imp for the
Ground nets
3. Click on the Run LVS
button
NOTE:
The Calibre LVS rule deck
requires that the design
contain power and ground nets
to be considered correct.
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Step 41: View Calibre LVS Results
1. Examine the New
Layout form, then OK the
form
This concludes the Schematic
Driven Layout tutorial. Please
feel free to explore this data
further or move on to the next
stage in the Pyxis_SPT.
.
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Perform Schematic Driven Layout using Pyxis SDL
Schematic driven layout starts by selecting a cell in your project -
the design connectivity, SDL rules and process options are setup
automatically by default
Use the LDL Cockpit to place devices from the connectivity source
and to fix instance mapping and connectivity changes
Use IRoute with LVS and DRC correct pushing, jogging and via
insertion to fully route your design
Summary
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Stage 9: Automated Layout
DRC, LVS,
xRC
Design Verification
Mixed Signal
Floorplanning
and
Assembly
Full-Custom
Layout
Automated
Layout
Analog
RF
Parasitic Modeling
Area Estimation
Design Capture
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Perform the Following Tasks using
Pyxis Assemble
Edit a previously floor planned digital
block
Use the Hierarchy Window to flatten
digital block hierarchy
Place standard cells and Feedthru cells
View Power Route options and create
power ring
Setup and run ARoute and Batch
ARoute
Complete unfinished routes using
IRoute with DRC and LVS clean
pushing, jogging and auto-route
completion
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can skip this step
NOTES:
two script files:
data
tool home directory
settings
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Step 2: Open Hierarchical Layout
FreqSynth layout inside of the
TopDown_Automation
library using the popup menu
item:
RMB->Open->Layout Editor
NOTE:
You may notice that one option to
open the layout is Layout Editor
(Shared). This will open the
layout in a Shared Editing Mode
session using Pyxis Concurrent
which enables multiple users to
edit the same cell at the same
time.
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menu item Windows->
Hierarchy Window
NOTE:
The hierarchy window provides
an interactive hierarchical listing
of the layout.
Step 3: Open Hierarchy Window
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The context of the design
hierarchy is currently the top cell
FreqSynth as indicated by the
context arrow. Using the down-
stroke, we can set the context to
the DIV_BY_N1 instance of the
div_by_n cell.
1. Use your MMB (Middle
Mouse Button) to draw a
down stroke beginning on
the DIV_BY_N1 instances
NOTES:
If you dont have a Middle
Mouse Button on your system,
you can select the DIV_BY_N1
instance in the Hierarchy
Window, switch to the IC Layout
window, enter the x hotkey to
set the context to the selected
object, then switch back to the
hierarchy window.
After setting the context, you
should see the context arrow
point to the DIV_BY_N1
instance.
Step 4: Set Context to div_by_n Block
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1. Select the hierarchical
cells under div_by_n
2. Click on the FltnHi
button in the Floorplanning
section of the Hierarchy
Palette
NOTE:
The hierarchy is flattened to
enable all the cells in the
div_by_n layout to be placed
together with the Standard Cell
Placer.
Step 5: Select Hierarchy to Flatten
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1. OK the ICgraph Query
to reserve the div_by_n
cell
2. Set the Place argument
to noplace
3 OK the FLA HI command
prompt
Step 6: Flatten Hierarchy
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1. Note the changes in the
DIV_BY_N hierarchy
2. Click on the Layout
Canvas tab
NOTE:
The instances affected during
the flatten hierarchy will have
information on their original
hierarchy shown inside of their
respective instance names.
Step 7: View Flattened Hierarchy
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1. Load the Plan & Place
Palette
2. Select Add Rows FP:
3. Set the Site Number to
1
6. Enable Route area ratio
and set the ratio to 0
7. Set the Edge gaps to be 5
to enable extra room for
power
8. OK the Add Rows form
and the prompt
Step 8: Add Rows by Floorplan Shape
6
5
7
4
1
4. Click on Options
In the Add Rows by
FP Options form:
5. Set Row layout: to
Alternating (Bottom
normal)
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3
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1. Click on the StdCell
button in the Auto
Placement section of the
Plan & Place Palette
2. OK the AUTOPLA ST C
prompt
3. Click on the Feed
button in the Auto
Placement section of the
Plan & Place palette
4. Set the Slide direction to
Left, enable Fill row and
OK the Autoplace Feedthru
Cells form
NOTE:
Fill cells are placed with the
standard cells to fill in the gaps
and square up the placed
layout for easier power routing.
Step 9: Add Standard and Feedthru Cells
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1. Click on the Route
button at the top of the
Plan & Place Palette to
load the ARoute Palette
2. Click on the Setup
button in the Power
Routing section of the
ARoute Palette and inspect
the default settings in the
Power Routing form, then
OK the form without
making changes
NOTE:
The Power Routing setup can
modified as needed or be
loaded from process settings or
the cells process overrides
settings.
3. Click on the Power
Routing Run button
Step 10: Power Routing
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Were going to go up one level
so we can run Autoplace pins
on the div_by_n block. This
will optimize the pin placement
to its connections within the
upper level context.
menu item Context->
Hierarchy-> Set Context
Up:
2. OK the SET CO U
prompt
NOTE:
You can also use the MMB
(Middle Mouse Button)
upstroke to set the context up
one level.
Step 11: Set Context Up One Level
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1. Select the div_by_n
block
2. Click on the Plan button
in the ARoute Palette to
load the Plan & Place
Palette
2. Click on the Autoplace
Pinsbutton in the Plan &
Place Palette
3. Set the Left/Right Level
to M2 and the
Top/Bottom Level to M3
and OK the Autoplace Pins
form
NOTE:
It is important to match the pin
placement with the routing
directions used by ARoute to
ensure good routing results.
Step 14: Autoplace Pins on div_by_n Block
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1. Set the context back
down to the div_by_n
block and bring up the
ARoute palette
under the ARoute
Commands in the ARoute
Palette
NOTE:
ARoute is already setup to
complete the routing. In the
next few steps, well see how
to modify ARoute settings an
reroute the design.
Step 15: Run ARoute
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ARoute should completely
route the design with the
settings loaded upon startup.
menu item Setup->
Windows->ARoute Options
NOTE:
The ARoute Options Window
will enable you to view and
change all ARoute settings.
Step 16: ARoute Results
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1. In the ARoute Options
Window, turn off routing in
M4, M5, and M6
2. Click on the Delete
button under Routing
Results in the ARoute
Palette
3. OK the DEL RO prompt
with the Nets value set to
all
NOTE:
You can delete all routing in
the current context or only
delete routing on nets that are
currently selected.
This command will delete both
the signal and power routing.
Step 17: Setup Directions and Delete Results
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under the Power Routing
under the ARoute
Commands
Step 18: Rerun Power Routing and ARoute
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Because there were fewer
layers this time, there should
be some unfinished routes.
You can view the ARoute
transcript in the Transcript Area
Window.
1. Stretch the Transcript
Area Window to view the
ARoute transcript
ARoute will list the number of
nets and the reason they did
not route. The classification
AR_need_more_time means
ARoute could not determine if
the nets could be routed.
2. Click on the Delete
button under Routing
Results in the ARoute
Palette
3. OK the DEL RO prompt
with the Nets value set to
all
Step 19: View Transcript and Delete Results
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3
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One way to improve your
results is to run Batch ARoute.
Batch ARoute enables you to
specify multiple passes,
relaxing the constraints for
each pass. The first pass is
typically routing by nets instead
of individual overflows with
wrong way disabled. This
helps to prevent more signals
from being accidentally
blocked. The last pass is
typically routing by overflows
with wrong way enabled which
allows more nets to be routed
at the possible cost of blocking
other signals.
1. Click on the Batch
button under the ARoute
Commands
2. After inspecting the
Batch ARoute settings, OK
the form to launch Batch
ARoute
Step 20: Run Batch ARoute
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1. After Batch ARoute is
completed, click on the
SOvrf button under
Routing Results
You should see three overflows
selected. In general, you can
use SOvrf or Select Overflows
to see if your connectivity
driven design is fully routed by
looking at the select count in
the Status Toolbar.
Because there are only three
unfinished routes, we can use
IRoute quickly finish routing
the design.
2. Zoom-into the upper
left hand corner of the
design
Step 21: Batch Route Results
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Step 22: Load IRoute Options Window
The congested area may look
hopeless, but IRoute was
designed to address these
types of situations that
invariably come during custom
IC design. Youll see how
running IRoute with toggling
pushing, jogging and auto-
complete can help you quickly
finish your layout.
menu Setup-> Windows->
IRoute Options
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Step 23: IRoute Unfinished Signals Part I
in the SDL toolbar to begin
IRoute
2. Click on the first un
routed port on the left and
route downwards
3. Type the hotkey p to
set the push mode to two
directions (Youll see the
setting in the Iroute
Options Window) to move
the M1-M3 vias out of the
way
4. LMB click to define a
route point below the
congested area and route
to the right
5. Enter the hotkey Shift-
a to Auto Complete the
route
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2
4
4: Shift-a
3: p, p
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Step 24: IRoute Unfinished Signals Part II
to begin the route if it is
not active
2. Click on the next un
route downwards
3. Enter the hotkey 3 to
transition down to M2.
(You wont see a drop VIA
outline yet because its
blocked)
4. Set the push mode to
two directions using p
5. LMB click to drop the
VIA just below the port
2
3: 3
4: p, p 5
6
7
8: Shift-a
6. LMB click to define a route point just above the large power via and route to the right
7. LMB click to define a route point once the route is clear of the large power via and route downwards
8. Enter the hotkey Shift-a to Auto Complete the route
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Step 25: IRoute Unfinished Signals Part III
to begin the route if it is
not active
2. Click on the last un
route downwards
3. Set the push mode to
two directions using p
4. LMB click to define a
route point just and
continue routing in M3 to
the right
5. Enter the hotkey 3 to
transition down to M2
2
3: p, p
4
5: 3
6
7: Shift-a
6. LMB click to drop the M3 to M2 VIA and routed downwards
7. Enter the hotkey Shift-a to Auto Complete the route
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Step 26: Completed Layout
Your completed layout should
look similar to screenshot on the
left.
This concludes the Automated
Layout Stage of the Pyxis SPT.
Feel free to continue
experimenting with Power and
ARoute routing options using this
data.
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Summary
Automated Layout using Pyxis Assemble
Perform custom standard cell place and route in the same
environment used for floorplanning and transistor level schematic
driven layout
Fast automatic routing enables you to iteratively adjust routing
and automatic signal and power routing according to your design
needs
Finish routes in congested areas using interactive routing with
DRC and LVS clean pushing, jogging and auto-route completion
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Quick Start Recipes
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Pyxis Quick Start Recipes
Setup Hotkey Example
This Pyxis Quick Start Recipe was created to demonstrate how to map
a hotkey to an existing registered function using the Setup->Hotkeys
pull-down menu item
In this example, well map the hotkey Shift-Control-m to the move
relative command in the Pyxis Layout editor
This recipe guides users through the following exercises:
Invoke Setup Hotkeys
Search registered functions by filter string
Map a hotkey to an existing registered function
Save the UI change in the profile for later use
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Customizing the Pyxis GUI
Before getting started
The Customize Your Pyxis Toolbars Recipe is based on the Pyxis Self
Paced Tutorial data updated in April, 2013
The tarball file name is Pyxis_SPT_v10.2_12.1_r01.tgz
Contact your local AE if you need a copy of this file
Please see the README file inside the unpacked Pyxis_SPT data for
instructions and required tool versions
Pyxis v10.1 or later is required for this recipe
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the open_Pyxis_SPT script
NOTE:
The Pyxis_SPT data is used as an example.
This steps learned here should be
independent of the project and technology
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Step 2: Open the Pyxis Layout editor
1. Select the GenericPLL
library
2. Select the D_FF cell
3. Select the D_FF_layout
layout choose the RMB
popup menu item RMB-
>Open->Layout Editor
NOTES:
You can open any layout or
simply open the Pyxis Layout
editor without a layout cell
loaded.
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Step 3: Search for the Move Relative command
1. In Pyxis Layout, select the pull-down menu item Setup->
Hotkeys
2. In the Setup Hotkeys form, click in the registered
commands area enter the Control-f hotkey to bring the
search gadget
3. Type relative to search for the move relative command
4. Click on the Next button in the search gadget until you
find the $$move_relative command
5. Select the $$move_relative command to specify the scope
and command on the right hand side of the form
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2: Control-f
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Step 4: Specify the desired hotkey
1. Click on the Start button
2. Enter the Control-Shift-m
hotkey
3. Click on the Apply button
Pyxis Layout will check if there is
already an existing mapping for
the specified hotkey. If there is,
you will be asked if you want to
first clear it. In this case
Control-Shift-m is mapped to the
Setup Macros command by
default. If you wish, you can
click on Cancel and select a
different hotkey for the
mapping.
4. Click on the Yes button in the
Query form
4
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Step 5: Determine Target Command
You should see that the
$$move_relative command is
now mapped to the hotkey
Ctrl+Shift+M
1. OK the Setup Hotkeys
form
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Step 6: Test the new hotkey mapping
1
1. Select one fo the NOR02 gates
in the D_FF_layout canvas
2. Enter the hotkey:
Control-Shift-m
3. In the MOV RE prompt, enter
2 for the X offset and type
return
If you are able to do the above steps,
the hotkey was mapped successfully!!
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2: Control-Shift-m
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Step 7: Save the Profile
Multiple profiles can be saved
and then reloaded in the same
or subsequent Pyxis Layout tool
sessions. For this example, lets
save the profile to a unique
name hotkey_mapping.
item Setup->Profiles->Save As
2. Specify the Profile Name to
be hotkey_mapping and OK
the Save Profile As form
The hotkey_mapping profile
will become the active profile
and can be loaded in later Pyxis
Layout tool sessions.
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Additional Notes
The hotkey mapping done by Setup Hotkeys updates the Register
Commands list. If you find $$move_relative in the Setup Register
Commands form, you will see it mapped to the Control-Shift-m hotkey
Setup Hotkeys is part of the Common User Interface and it works similarly
in Pyxis Layout, Pyxis Schematic, Pyxis Project Manager and Pyxis Language
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This Pyxis Quick Start Recipe was
created to demonstrate how to add a
custom Browse for Instance and
Edit Objects icon to the Pyxis
Schematic Edit Toolbar
This recipe guides users through the
following exercises:
Search and find information on
registered commands using Setup
Registered Commands
Use Setup Macros to create and
register a custom function
Add customized icons to a registered
command using Setup Registered
Commands
Customize your Edit Toolbar and
save changes in a reloadable profile
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Before getting started
The Customize Your Pyxis Toolbars Recipe is based on the Pyxis Self
Paced Tutorial data updated in April, 2013
Pyxis v10.1 and AMS v12.1 or v11.2 is required for this recipe
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NOTE:
The Pyxis_SPT data is used as an example.
This recipe is intended to teach users how
to Toolbars can be customized in the Pyxis
environment.
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Step 2: Create a New Schematic
1. Select one of the libraries under
the Pyxis_SPT project.
2. Click on the New Schematic
icon
3. Specify dummy_schematic for
the Cell Name
NOTES:
You can also perform the next steps on
an existing schematic open in a Pyxis
Schematic session.
The Pyxis Project Manager and Pyxis
Layout windows can be customized in
the same manner outlined in the steps
ahead.
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Step 3: Determine Icon Short Description
1. Hover your mouse over the Add Instance icon
to see the pop-up hint describing the command
The step above is done to identify the Short Description of
the registered command which is Add Instance. This is
useful and will help you to find the system command and
icons associated with the description.
2. In the Pyxis Schematic window, select the pull-
down menu item: Setup-> Registered Commands
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Step 4: Search in Setup Registered Commands
1. Enter the hotkey
Control-f in the command
list area to show the Search
bar
2. Search for the short
description you find in the
previous step - Add
Instance. Youll need to
click on the Next button
until you find the registered
command with both
medium and large icon
images
Remember the full filenames of
these icon images. You can use
these images directly in your
customized registered command
or copy and modify them to be
more descriptive.
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Step 5: Determine Target Command
1. Search for the string
Browse to find an existing
command that will browse
for an instance first
In v10 and v10.1, this is called
$da_variant_browse_instance
and it is registered in the
da_windowscope.
2. Remember this command
so you can use it when you
define a macro in the next
step
3. Close the Setup
Registered Commands form
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Step 6: Define a Custom Macro
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1. In the Pyxis Schematic window,
select Setup->Macros
2. Enter my_browse_instance
for the macro name
3. Enter
$da_variant_browse_instance()
in the command area
4. Register a hotkey by clicking on
the Start button and typing
Control-b
5. Save the macro
6. Close the Setup Macros form
NOTES:
The Setup Macros form is a short-cut to
define and register custom commands.
A hotkey is always required, but we can
remove the hotkey definition when we
modify the registration.
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Step 7: Customize Icons
1. Copy the AddInstance icons found
in step 4 to a stable location
This example is using the
my_MGC_CUSTOM_TYPE_DIR/icons
directory as it was created in another Pyxis
QuickStart Recipe guide - Register
Custom Data Type and Tool. This used
the $MGC_CUSTOM_TYPE_DIR
environment variable and had the softpath
entry placed in the projects
mgc_location_map file making the actual
path portable. This makes it an ideal
location to place customized icons
intended for site-wide use.
2. Edit the enabled icons with your
favorite image editor to make them
more descriptive
This example skips the disabled icons
because they tend to be grayed out and
not visible.
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Step 8: Update Registration for Macro
1. Open the Setup
and search for
my_browse_instance
2. Clear the hotkey
3. Setup the enabling
condition to be
$scope_visible(schematic) -
the same as the original
Add Instance command
4. Specify the icons that
were modified in step 7 or
use the icon images found
in step 4
5. Add a Short and Long
description
6. Click on Register
Command to preserve the
changes and close the form
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Step 9: Customize Edit Toolbar
1. Select Setup->Toolbars->Customize
2. Search for the newly added Browse for
Instance icon.
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3. Drag the original Add Instance icon
from the Edit Toolbar to any location in
the the Customized Toolbars form and
replace it with the new Browse for
Instance icon
4. OK the Customize
Toolbars form
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Step 10: Search Command in Setup Registered Commands
1. Search for the
$show_object_editor
command in the Setup
The command is in the cms_tk
scope. When customizing the
toolbars, Pyxis Schematic does
not see icons from this scope so
first you need to register the
command to the fb_schematic
scope.
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Step 11: Register Command to New Scope
1. Change the scope name
to fb_schematic
2. Clear the Hotkey (to
minimize a chance of a
conflict)
3. Set the Short and Long
Descriptions to you liking
4. Register the command
the close the form
Now you will be able to see an
icon associated with the
$show_object_editor command.
5. As in step 9, use the
Customize Toolbars form to
add the Edit Object icon
to the Edit Toolbar
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Step 12: Test Customization and Save Profile
1. Test the added icons for functionality
2. Select Setup-> Profiles-> Save As and specify an
adequately descriptive profile name
NOTES:
The new profile is saved under your $HOME/mgc/profiles directory
If youre using the Pyxis_SPT data, your $HOME directory is
mapped to the ic_settings/my_home directory under the unpacked
Pyxis_SPT location.
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Additional Notes
When you create a macro using the Setup Macros form, it registers the
commands you specified as a custom function and stores it in your $HOME
directory when you save your profile. You do not need to worry about
loading any Ample userware
The icon images specified in the Setup Registered Commands form are not
stored in a profile and need to be loaded from their specified locations. It is
best to place these image files in a location that can be included in your
mgc_location_map
When the Customize Toolbars form is showing, you can drag and drop icons
from the Customize Toolbars from or other toolbars onto your target toolbar
Please reference the Pyxis Common User Interface Users Manual for
detailed information regarding Setup Registered Commands, Setup Macros
and Customize Toolbars functions
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Register Custom Data Type and Tool
This exercise guides you
through the following:
Setup the
MGC_CUSTOM_TYPE_DIR
location
Login as Admin
Create a new type for
simulation .wdb files and
the new tool for EZwave
Launch EZwave from Pyxis
Project Manager
Open EZWave on existing
.wdb file using the (classic)
Navigator window
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Register Custom Data Types and Tools
Quick Start Recipe
The Register Custom Data Types and Tools Quick Start Recipe is
based on the Pyxis Self Paced Tutorial data updated in April, 2013
Pyxis v10.1 and AMS v12.1 or v11.2 is required for this recipe
Please reference the Pyxis Project Managers Reference Manual for
detailed information on registering custom types and tools
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Step 1: Create MGC_CUSTOM_TYPE_GUI location
1. In the unpacked Pyxis_SPT
directory, make a directory called
my_MGC_CUSTOM_TYPE_DIR
2. Make another directory called
my_MGC_CUSTOM_TYPE_DIR/ icons
3. Use your favorite text editor to edit
4. Update the
MGC_CUSTOM_TYPE_DIR path to
point to `pwd`/
my_MGC_CUSTOM_TYPE_DIR
NOTE:
The $MGC_CUSTOM_TYPE_DIR location will
hold the custom tool registry and
qualification scripts.
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Step 2: Update MGC_LOCATION_MAP
1. Use your favorite text editor to edit the
mgc_location_map in the Pyxis_SPT project
(ic_projects/Pyxis_SPT/mgc_location_map)
2. Add a single line - $MGC_CUSTOM_TYPE_DIR
NOTE:
This will allow you to specify the icons to be in the portable
$MGC_CUSTOM_TYPE_DIR/icons location.
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run the open_Pyxis_SPT script
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Step 4: Login as Admin
1. Select the pull-down menu item:
Setup-> Admin Login
2. Enter the password
admin1234
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Step 5: Setup New Type
1. Select the pull-down menu item:
Setup> New Type
2. Specify the Type Name to be
ezwave_wdb
NOTE:
The Type Name is not the same as the
extension. It should be clearly unique
from other object types and descriptive.
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Step 6: Edit Type
1. Fill out the Edit Type form as
shown
NOTES:
Verify the path to the ViewEZ_L.png and
ViewEZ_M.png icons. These will be
platform dependent.
The default icons can be copied into your
$MGC_CUSTOM_TYPE_DIR/icons directory
and used as a starting point for your custom
icons. You can use kiconedit to make
graphical changes to the icons, but be sure
they remain the same size in in the same
format.
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Step 7: Launch EZwave from Tools Menu
1
EZwave should be immediately available as a custom tool and accessible from the Tools pull down menu.
1. Select the pull-down menu item: Tools-> Launch Ezwave
2. Verify EZwave opens and then close the window.
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Step 8: Launch EZwave from Navigator
If you have a wdb file in your project, you can navigate to it using the (classic) Navigator window and invoke EZwave directly.
Shown is a wdb file that would be generated after completing the Stage 2: Design Capture lab.
1. Select the $PYXIS_SPT/GenericPLL/Sim/comp/tb_comp/transient/tb_comparator_transcient.wbd file
2. Select the popup menu item: RMB-> Launch Ezwave
3. Verify EZwave opens and loads the transient/tb_comparator_transcient.wbd file and then close the window
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Additional Notes
Multiple Types and Tool Types can be registered when logged in as
admin
Types and Tool Types can be edited using Setup->Edit Type or
Setup->Edit Tool Type
The invocation qualification script can be edited to further control
how custom type data is opened
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2013 Mentor Graphics Corporation. All rights reserved.
This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this
document may duplicate this document in whole or in part for internal business purposes only, provided that this entire
notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable
effort to prevent the unauthorized use and distribution of the proprietary information.
TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics
Corporation or other parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics
or the owner of the Mark, as applicable. The use herein of a third-party Mark is not an attempt to indicate Mentor
Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party.
A current list of Mentor Graphics trademarks may be viewed at: www.mentor.com/trademarks.
End-User License Agreement: You can print a copy of the End-User License Agreement from: www.mentor.com/eula.

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