N-Channel Enhancement Mode Field Effect Transistor

FEATURES
Super high dense cell design for extremely low R
DS(ON)
.
High power and current handing capability.
ABSOLUTE MAXIMUM RATINGS T
c
= 25 C unless otherwise noted
Parameter Symbol
Limit
Units
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
Drain Current-Pulsed
a
Maximum Power Dissipation @ T
C
= 25 C
- Derate above 25 C
V
DS
V
GS
I
D
P
D
I
DM
e
650
0.33
41
8
2
30
V
W
A
A
V
W/ C
1
G
S
D
CEB SERIES
TO-263(DD-PAK)
S
D
G
CEP SERIES
TO-220
CEF SERIES
TO-220F
S
D
G
Type V
DSS
R
DS(ON)
I
D
@V
GS
CEP02N65D
CEF02N65D
650V
650V
6.9
6.9
2A
2A
d
10V
10V
TO-220/263 TO-220F
0.22
27
8
d
2
d
CEP02N65D/CEB02N65D
CEF02N65D
CEB02N65D
Lead free product is acquired.
650V 6.9 2A 10V
http://www.cetsemi.com
This is preliminary information on a new product in development now .
Details are subject to change without notice .
Rev 1. 2009.July
S
G
D
Operating and Store Temperature Range T
J
,T
stg
-55 to 150 C
Thermal Characteristics
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Parameter Symbol Limit Units
C/W
C/W
62.5
3 RJC
RJA
4.5
65
PRELIMINARY
Electrical Characteristics T
c
= 25 C unless otherwise noted
Parameter Symbol Min Units
Off Characteristics
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage Current, Forward
Forward Transconductance
Gate Threshold Voltage
Static Drain-Source
On-Resistance
BV
DSS
I
DSS
IGSSR
I
GSSF
6.9
2.5 4.5
-100
100
1

V
nA
nA
A
V
S
2
Gate Body Leakage Current, Reverse
On Characteristics
b
Dynamic Characteristics
c
Input Capacitance
Reverse Transfer Capacitance
Output Capacitance
Switching Characteristics
c
Turn-On Delay Time
Turn-Off Fall Time
Turn-Off Delay Time
Turn-On Rise Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Drain-Source Diode Characteristics and Maximun Ratings
Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
b
Test Condition
V
GS
= 0V, I
D
= 250A
V
GS(th)
R
DS(on)
g
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Typ Max
650
V
DS
= 650V, V
GS
= 0V
V
GS
= 30V, V
DS
= 0V
V
GS
= -30V, V
DS
= 0V
V
GS
= V
DS
, I
D
= 250A
V
GS
= 10V, I
D
= 0.8A
V
DS
= 10V, I
D
= 0.6A
V
DD
= 300V, I
D
= 1.3A,
V
GS
= 10V, R
GEN
=4.7
V
DS
= 480V, I
D
= 1.3A,
V
GS
= 10V
V
DS
= 25V, V
GS
= 0V,
f = 1.0 MHz
270
55
25
11
10
27
7.5
15.5
1
10
1.3
1.5
0.8
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
A
V
4
14.3
13
35.1
9.75
20.1
5.6
CEP02N65D/CEB02N65D
CEF02N65D
I
S

f
V
SD

Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature .
b.Pulse Test : Pulse Width < 300s, Duty Cycle < 2% .
c.Guaranteed by design, not subject to production testing.
d.Limited only by maximum temperature allowed .
e.Pulse width limited by safe operating area .
.

V
GS
= 0V, I
S
= 0.6A
g
3
C
,

C
a
p
a
c
i
t
a
n
c
e

(
p
F
)
C
iss
C
oss
C
rss
300
250
200
150
100
50
0
0 5 10 15 20 25
R
D
S
(
O
N
)
,

N
o
r
m
a
l
i
z
e
d
R
D
S
(
O
N
)
,

O
n
-
R
e
s
i
s
t
a
n
c
e
(
O
h
m
s
)
VDS, Drain-to-Source Voltage (V)
Figure 1. Output Characteristics
VGS, Gate-to-Source Voltage (V)
Figure 2. Transfer Characteristics
VDS, Drain-to-Source Voltage (V)
Figure 3. Capacitance
TJ, Junction Temperature( C)
Figure 4. On-Resistance Variation
with Temperature
V
T
H
,

N
o
r
m
a
l
i
z
e
d
G
a
t
e
-
S
o
u
r
c
e

T
h
r
e
s
h
o
l
d

V
o
l
t
a
g
e
TJ, Junction Temperature( C)
Figure 5. Gate Threshold Variation
with Temperature
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
V
DS
=V
GS
I
D
=250A
-50 -25 0 25 50 75 100 125 150
I
S
,

S
o
u
r
c
e
-
d
r
a
i
n

c
u
r
r
e
n
t

(
A
)
VSD, Body Diode Forward Voltage (V)
Figure 6. Body Diode Forward Voltage
Variation with Source Current
0.2 0.6 1.0 1.4
10
-1
10
-2
10
0
2.2 1.8
V
GS
=0V
CEP02N65D/CEB02N65D
CEF02N65D
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
GS
=10V
I
D
=0.8A
-100 -50 0 50 100 150 200
I
D
,

D
r
a
i
n

C
u
r
r
e
n
t

(
A
)
I
D
,

D
r
a
i
n

C
u
r
r
e
n
t

(
A
)
0 5 10 15 25 20
1.5
0.0
1.2
0.9
0.6
0.3
V
GS
=6V
V
GS
=5V
V
GS
=10,9,8V
0.4
0.3
0.2
0.1
0.0
1 2 3 4
0.5
5 6 7
T
J
=125 C
-55 C
25 C
4
V
G
S
,

G
a
t
e

t
o

S
o
u
r
c
e

V
o
l
t
a
g
e

(
V
)
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
VDS, Drain-Source Voltage (V)
Figure 8. Maximum Safe
Operating Area
I
D
,

D
r
a
i
n

C
u
r
r
e
n
t

(
A
)
Figure 9. Switching Test Circuit Figure 10. Switching Waveforms
t
V
V
t
t d(on)
OUT
IN
on
r
10%
td(off)
90%
10% 10%
50% 50%
90%
toff
tf
90%
PULSE WIDTH
INVERTED
VDD
R
D
V
V
R
S
V
G
GS
IN
GEN
OUT
L
r
(
t
)
,
N
o
r
m
a
l
i
z
e
d

E
f
f
e
c
t
i
v
e
T
r
a
n
s
i
e
n
t

T
h
e
r
m
a
l

I
m
p
e
d
a
n
c
e
Square Wave Pulse Duration (msec)
Figure 11. Normalized Thermal Transient Impedance Curve
10
-2
PDM
t1
t2
1. RcJC (t)=r (t) * RcJC
2. RcJC=See Datasheet
3. TJM-TC = P* RcJC (t)
4. Duty Cycle, D=t1/t2
10
0
Single Pulse
0.01
10
-1
10
-2
10
3
10
4
10
2
10
1
10
0
10
-1
0.02
0.05
0.1
0.2
D=0.5
10
8
6
4
2
0
0 3 6 9 18
V
DS
=480V
I
D
=1.3A
12 15
4
CEP02N65D/CEB02N65D
CEF02N65D
10
1
10
0
10
-1
10
-2
10
-3
10
3
10
2
10
1
10
0
1s
100ms
10ms
DC
Single Pulse
T
A
=25 C
T
J
=150 C
1ms
R
DS(ON)
Limit