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5. [4] Masoud Zargari, Member, IEEE, David K. Su, Member, IEEE, C. Patrick
Yue, Member, IEEE, Shahriar Rabii, David Weber, Brian J. Kaczynski,
Member, IEEE, Srenik S. Mehta, Member, IEEE, Kalwant Singh, Sunetra
Mendis, and Bruce A. Wooley, Fellow, IEEE, �A 5-GHz CMOS Transceiver
for IEEE 802.11a Wireless LAN Systems�
8. Ji-Hoon Kim and Hyung-Joun Yoo �Low Power Octa-phase LC VCO for
Direct Conversion 5 GHz WLAN Receiver.� APMC 2005 proceedings.
9. A.Ravi, K.Soumyanath, L.R. Carley, and R. Bishop, �An Integrated 10/5 GHz
Injection-locked Quadrature LC VCO in a 0.18�m digital CMOS process.�
ESSCIRC 2002 pp. 543-546.
10. Jussila J., Ryynanen J., Kivekas K., Sumanen L., Parssinen A., Halonen K., �A
11. Marques, A., Steyaert, M., Sansen, W., �Theory of PLL fractional-N frequency
synthesizers�, Wireless Networks, No. 4, 1998, pp. 79-85.
12. Vankka, J., Waltari, M., Kosunen, M., Halonen, K.A.I., �A Direct Digital
Synthesizer with an On-Chip D/A-Converter�, IEEE Journal of Solid-State
Circuits, Vol. 33, No. 2, pp. 218-227, February 1998.
13. Sander L.J. Gierknin, Salvatore Levantino, Robert C.Frye, Carlo Samori, and
Vito Boccuzzi, �A Low-Phase-Noise 5-GHz CMOS Quadrature VCO Using
Superharmonic Coupling� IEEE Journal of Solid-State Circuits, VOL. 38, No.
7, July 2003.
16. Hamid R. Rategh, Hirad Samavati, and Thomas H. Lee, �A CMOS Frequency
Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz Wireless
LAN Receiver.� IEEE Journal on Solid-State Circuits, Vol. 35, No. 5, May
2000.
17. Vankka, J., Waltari, M., Kosunen, M., Halonen, K.A.I., �A Direct Digital
Synthesizer with an On-Chip D/A-Converter�, IEEE Journal of Solid-State
Circuits, Vol. 33, No. 2, pp. 218-227, February 1998.
18. Ahola, R., Vikla, J., Lindfors, S., Routama, J., Halonen, K., �A 2 GHz Phase-
Locked Loop Frequency Synthesizer with On-Chip VCO�, Analog Integrated
Circuits and Signal Processing, Vol. 18, No. 1, pp. 43-54, January 1999.
20. Robert C. Chang and Lung-chih Kuo, �A new Low-Voltage Charge Pump
Circuit for PLL�. ISCAS 2000, May 28-31. pp. 701-704.
22. Jung-Sheng Chen and Ming-Dou Ker, �Impact of Gate Tunneling Leakage on
Performances of Phase Locked Loop Circuit in Nanoscale CMOS Technology�
IEEE 07CH37867 45th
Annual International Reliability Physics Symposium pp.
664-665.
23. Chih-Ming Hung, Brian A. Floyd, Namkyu Park, and Kenneth K.O, �Fully
Integrated 5.35 GHz CMOS VCOs and Prescalers� IEEE Transactions on
Microwave Theory and Techniques, VOL. 49, NO. 1 Jan 2001 pp. 17-22.
24. Chih-Ming Hung, and Kenneth K.O, �A Fully Integrated 1.5-V 5.5-GHz
CMOS Phase-Locked Loop� IEEE Journal on Solid-State Circuits, Vol. 37, No.
4, April 2002. pp. 521-525.