- 1 -

CHAPTER 1
INTRODUCTION


1.1 Motivation
Power consumption plays an important role in the present day VLSI technology. As many
of the present day electronic devices are portable, they need more battery backup which
can be achieved only with the low power consumption circuits that are internally designed
in them. So energy efficiency has become main concern in the portable equipment to get
better performance with less power dissipation. As the transistor count per chip increases
rapidly in the system-on-chip (SoC) era, significant reduction in power overhead in
dynamic switching and leakage is of particular importance. There were various
technologies proposed like MTCMOS, VTCMOS, Domino logic etc. to make the circuits
more energy efficient and reliable .Adiabatic logic style was one of them. Adiabatic logic
style has emerged as a promising approach to achieve ultra-low power without sacrificing
noise immunity and driving ability. Numerous adiabatic circuits have been presented over
the years [1][6]. They are based on the same principle, but the structures and complexity,
such as
1) Number of operation clock;
2) Single- dual-rail style;
3) Charging/discharging path;
4) Reversible-/irreversible-logic style, differ from each other.
Because the reversible energy recovery circuits have the control signal(s) coming from the
next stage, the design overhead for applying such logic in a large system is considerable
[2][4].

1.2 Objective
Most of the irreversible adiabatic circuits are, however, referred to dynamic circuit
properties which are of higher switching activity and ratioed logic [12] in spite of their
advantages. In addition, the requirements of multiphase and multiclock operations also
make them unfavourable in terms of design complexity and implementation area except for
- 2 -

few works. A quasi-static energy recovery logic (QSERL) has been proposed in order to
overcome the drawbacks of the irreversible ERL families [7][10] but it also leads to the
evaluate and hold phases which reduce the efficiency. The main objective of previous
technologies was to reduce the energy and power losses and yes these techniques got
success but at the cost of another parameters like delay and noise immunity. Hence there
was a need of much more improvement to maximize the efficiency. The use of
complimentary sinusoidal power clocks leads to a great improvement in energy dissipation
in comparison to previously used biasing techniques and the QSERL the one which uses
this biasing technique. The main objective of this report to present an another ERL
adiabatic technology CEPAL which proves itself much more efficient and no hold phases
in comparison of previous one QSERL. Here we present a comparative study of QSERL
and CEPAL at various design circuits and results will prove the CEPAL a better one.

1.3 Performance evaluation parameters
QSERL features simplicity and static logic- resembled characteristics, which substantially
decreases the complexity and switching activity. The employment of only complementary
sinusoidal power clocks makes it be provided with higher energy efficiency compared to
those of the prior arts utilizing trapezoid or triangular clocking scheme. Despite the
advantages, QSERL suffers from inrobustness caused by output floating associated with
the alternate hold phases in operation. Although the floating can be eliminated by adding
clocked feedback keeper to each logic (keeper is turned ON only when QSERL is in the
hold phase), there will still be unwanted power loss. Also, the added area overhead as well
as control signals would restrict its application. Motivated by this, this report proposes a
complementary energy path adiabatic logic (CEPAL). CEPAL inherits all the advantages
of QSERL, but it eliminates further the hold phase for the same operation conditions,
thereby not only improving the robustness but also drastically increasing the throughput as
a whole. We analysed the performance of CEPAL through extensive experiments.
Different from those studies in the literature, the efficiency of using CEPAL in clocked
storage element (DFF) [13-14] will be explored.



- 3 -

1.4 Thesis organization
The rest of the report is organized as follows chapter 2 describes the literature review of
QSERL and CEPAL adiabatic logic circuits. Under this chapter we describe the basic
principle of adiabatic switching. In subsequent sections we briefly describe the different
aspect of some representative irreversible ERL families and discuss the limitations in
QSERL which also consideration of CEPAL. Analysis of CEPAL containing its structure,
operation and performance is detailed in the next section of this chapter. Chapter 3
describes the simulation and setup results at various circuit level designs like chain
inverter, DFF, J K FF and counter with comparative results of power and delay using both
QSERL and CEPAL technologies followed by concluding remark in chapter 4.


















- 4 -

CHAPTER 2
Literature review of QSERL and CEPAL circuits


2.1 Adiabatic principle




Fig. 2.1 Curve of switching period (T) in supply voltage versus MOS power
Dissipation (P
d
) for the inverter in charging phase.

The fundamental of adiabatic switching can be interpreted with the inverter structure
shown in Fig. 2.1. Considering the power dissipation in the charging phase first, the
relationship between the voltage drop (V
R
) across the PMOS transistor and the output
voltage (V
C
) can be expressed as

(1)
- 5 -

where is the rising time of the supply voltage and RC is the product of PMOS regarding the
resistance and output load. By solving (1), we have

(2)

Given that the power dissipation (P
d
) can be calculated by

(3)

For the charging phase, we obtain
(4)

If T in (4) is far larger than RC, P
d
will approximate ((RC/T))CV
DD
2
.

On the other hand, we can do a substitution for e
T/RC
by means of

(5)

approximated by Taylor series (omitting the higher order terms).
TheP
d
changes into

- 6 -


(6)

The above calculation implies that we may dramatically reduce the power dissipation by
somehow prolonging . Considering another circumstance that the PMOS is off, the NMOS
is on, and theV
C
HIGH is going to be discharged. If the discharging takes the same time as
the charging with a T long enough, we say the energy is recovered (or recycled) during that
phase. A curve representing T versus P
d
is shown in Fig. 2.1. Since the transistors are not
turned on immediately at initial states of both the phases (due to the gradually rising gate-
source voltage), a realistic power loss to the adiabatic inverter for a whole operation cycle
including charging and discharging can be approximated as

(7)

where we assume that the equivalent resistances and the absolute threshold voltages of
MOS transistors are identical (V
t
) . The power loss caused by theV
t
drop is often classified
as one kind of nonadiabatic loss.






- 7 -

2.2 QUASI STATIC ENERGY RECOVERY LOGIC (QSERL)


2.2.1 Brief analysis
With few exceptions, energy recovery logic families are dynamic in nature and often use
differential signalling, which is only suitable for some arithmetic circuits such as adders.
Higher switching activity of circuit nodes in dynamic approaches is unfavourable for low
power design. Large transistor and wiring overheads are other difficulties in applying
energy recovery logic. Previous energy recovery logic designs require multiphase
trapezoidal clock schemes.
Sinusoidal waveforms can be generated with higher energy efficiency than trapezoidal
waveforms. However, sinusoidal clocks cannot be efficiently utilized by most previous
designs. quasi-static energy recovery logic (QSERL) which uses two complementary
sinusoidal supply clocks and possesses several positive characteristics of static CMOS
logic. Circuit nodes are not necessarily charging and discharging every clock cycle which
reduces the node switching activities significantly. The lower switching activity reduces
energy dissipation.
Fig. 2.2 shows a schematic of QSERL which resembles the static CMOS logic. However,
the circuit operates in a nearly adiabatic fashion. A QSERL gate is based on a static CMOS
gate with two additional diodes. The diode on the top of the pMOS tree controls the
charging path, while the other diode at the bottom of the nMOS tree controls the
discharging path. Two sinusoidal clocks in complementary phases, and bar , are
sufficient. Hence, the complexity in circuit wiring and design are greatly reduced
compared to other energy recovery logic families. The supply clock signal consists of two
phases, evaluation and hold, as shown in Fig. 2.2.
- 8 -



Fig. 2.2. Quasi-static energy recovery logic (QSERL): Only two sinusoidal
clocks in complementary phases are required.

In evaluation phase swings up while bar swings down. One of the two paths, the pMOS
pull-up tree or the nMOS pull-down tree, is turned ON.
There are four cases as follows:
1) The circuit output node X is LOW and the pMOS tree is
turned ON. Then follows as it swings HIGH.
2) The circuit node X is LOW and the nMOS tree is ON.
X remains LOW and no transition occurs.
3) The circuit node X is HIGH and the pMOS tree is ON.
- 9 -

X remains HIGH and no transition occurs.
4) The circuit node X is HIGH and the nMOS tree is ON. X follows bar down to LOW.
In the hold phase, swings down while swings up. The circuit node X remains
unchanged due to the diodes. Note that cascaded gates are in alternate phases. The second
gate in Fig.2.2 evaluates its logic value while the first gate is in hold phase. Advantages of
this QSERL include the simplicity and its similarity to static CMOS. In contrast to
dynamic energy recovery logic in which each gate charges and discharges in every cycle,
QSERL is static. Circuit nodes are not necessarily charging and discharging every clock
cycle, thus reducing the node switching activity substantially.


2.2.2 Limitations of QSERL
A four-stage inverter chain has around half PC cycle increment of delay at the output of
each stage as a result of the interlaced evaluation and hold phases (i.e., an inverter can
evaluate only when its previous stage is being in the hold phase). It makes QSERL slightly
disadvantageous compared to its static CMOS counterpart in spite of the power efficiency.
Moreover, QSERL is susceptible to noise as a result of the output floating mentioned
previously. Once its input does not get changed during next evaluation, the output level
remains constant and the floating will be kept longer. Occurrence of hold phase in each
cycle makes QSERL disadvantageous or hindered to take full advantage. It reduces a lot of
energy dissipation in comparison to previous used technologies but not so efficiently.










- 10 -

2.3 COMPLEMENTARY ENERGY PATH ADIABATIC LOGIC


2.3.1 Operation and Analysis of CEPAL



Fig. 2.3 Proposed CEPAL. (b) CEPAL chain. (c) Balanced feedthrough
effect. The voltage level of V
out
can remain stable when its evaluation is
completed. Note that there are no interlaced circuit configurations and
multiphase operation.

- 11 -

The structure of CEPAL and its logic chain are shown in Fig.2.3(a) and (b), respectively.
CEPAL is composed of two charging transistors (P1 and P2), a pull-up network, two
discharging transistors (N1 and N2), and a pull-down(N-) network. This structure, as the
name suggests, is with two paths, without respect to charging or discharging. As far as
operation is concerned, assuming that the output (V
out
) is initially LOW, and the P-
network is on while the N network is off, the output follows either its complement
as it swings HIGH. Once V
out
reaches HIGH, the followed power clock then swings down,
and therefore forces the output node of CEPAL to become floating. Nevertheless, the
situation is soon removed as the complement of the followed power clock swings up,
thereby eliminating the weak HIGH at V
out
. Supposing the peak values and the operation
frequency of PCs are V
DD
and f , the condition that V
out
can be recharged during the
floating state is

(8)


where V
tp
, C
L
, I
ds
and t are the PMOS threshold voltage, the output load, the leakage
current of the adopted process, and the accumulated time from which the output node has
become floating, respectively. In order for further analysis, we assume that the switching
point (at which the output transition between HIGH and LOW occurs) of CEPAL is (1)/(2)
V
DD
, and V
out
has been fully charged. The condition for maintaining theV
out
correctness
(or the correctness of the subsequent stages) can be deduced through combining the
following equations:

A (9)
B
- 12 -


where t
HL
and t
RC
are, respectively, the required time that the output of CEPAL drops to
the switching point by leakage and the required time that correct output HIGH can be
maintained by the power clock which is the complement of the power clock used for
pulling the output to reach the HIGH. The start for both t
HL
and t
RC
is at the peak values of
PCs. Thus, we have

(10)


While the foregoing analysis is for V
out
=HIGH, a similar analysis can also help us to
understand how the weak LOW at the output can be eliminated by the complementary
energy path. With the analysis, we can discover that QSERL has around (1)/(2f) output
floating time longer than its CEPAL counterpart under the same operation conditions. The
main power dissipation in CEPAL occurs at the (MOS) diodes (non adiabatic loss), similar
to QSERL. It should be noted that the two more diodes in CEPAL only increase the power
dissipation slightly as there is only one charging or discharging transistor turned on at an
instant in time for the most part.










- 13 -

2.3.2 Fault Tolerance
From previous discussion, two approximate boundaries that the output correctness of
CEPAL can be maintained are located at which the power clock is one |V
tp
(V
tn
) higher
(lower) than (1)/(2) V
DD
for an evaluated output HIGH (LOW), as illustrated in Fig.2.4.




Fig. 2.4 Analysis of fault tolerance of QSERL and CEPAL. Illustration of
test concept.


- 14 -

2.4 QSERL D FLIP FLOP


Fig. 2.5 Structure of QSERL DFF

The above structure shows the schematic diagram for QSERL DFF using share and non-
share schemes.
- 15 -



Fig. 2.6 Timing diagrams of QSERL DFF with share scheme.

The structure of the QSERL DFF and the timing diagrams illustrated in Fig. 2.5 and 2.6,
respectively. If an input would like to be correctly captured, the position at which a clk
trigger must appear after that PC has been one |V
tp
| higher than the switching point of the
inverter a ((1)/(2) V
DD
). Otherwise, the output of Master latch will be ambiguous, resulting
in a possibility of incorrect Q.

- 16 -

Concluding remark
Adiabatic techniques have been effective means to power minimization using these
techniques we can greatly minimize or make the device much more effective. The
comparative view of QSERL and CEPAL techniques shows the practicability of the
adiabatic ELR for the greatly minimization the energy losses to the system. Previous
discussion shows how the limitations of QSERL play an important role for advanced
technique CEPAL it will be justify in next chapter.


























- 17 -

CHAPTER 3
SIMULATION AND RESULTS


TOOLS USED:
Schematic Editor: Cadence Virtuoso
Simulation Environment: Spectre
Cadence Virtuoso Schematic Editor:
Cadence Virtuoso Schematic Editor provides numerous capabilities to facilitate fast and
easy design entry, including design assistants that speed common tasks by as much as 5x.
Well-defined component libraries allow faster design at both the gate and transistor levels.
Sophisticated wire routing capabilities further assist in connecting devices. For larger and
more complex designs, Virtuoso Schematic Editor not only supports multi-sheet designs
but also provides the ability to design hierarchically, with no limit on the number of levels
used. The Hierarchy Editor makes hierarchical designs easy to traverse, and automatically
ensures all connections are maintained accurately throughout the design.
Features/Benefits:
Speeds common design entry tasks by 5x (GXL).
Enables adding design constraints to the schematic to maintain consistency and
preserve the designers intent on critical pieces of the design.
Eases the development of multiple tests over multiple conditions to validate a
designs performance against the target specification.
Allows advanced user to quickly execute commands using user-programmable bind
keys and object-sensitive pop-up menus, which display relevant operations.
Virtuoso Spectre Circuit Simulator:
Cadence Virtuoso Spectre Circuit Simulator provides fast, accurate SPICE-level simulation
for tough analog, radio frequency (RF) and mixed-signal circuits. It is tightly integrated
with the Virtuoso custom design platform and provides detailed transistor-level analysis in
- 18 -

multiple domains. Its superior architecture allows for low memory consumption and high-
capacity analysis.
Features/Benefits:
Provides high-performance, high-capacity SPICE-level analog and RF simulation
with out-of-the-box tuning for accuracy and convergence.
Facilitates the tradeoff between accuracy and performance through user-friendly
simulation setup applicable to the most complex analog and custom-digital ICs.
Enables accurate and efficient post-layout simulation with RLCK parasitics, S-
Parameter models (n-port), and lossy coupled transmission lines.
Performs application-specific analysis of RF performance parameters (spectral
response, gain compression, inter-modulation distortion, impedance matching,
stability, isolation).
Includes advanced statistical analysis (Smart, Monte Carlo, DC match) to help
design companies improve the manufacturability and yield of ICs at advanced
process nodes without sacrificing time to market.
Delivers fast interactive simulation set-up, cross-probing, visualization, and post-
processing of simulation results through tight integration with Virtuoso Analog
Design Environment.
Ensures higher design quality using silicon-accurate, foundry-certified device
models shared within Virtuoso Multi-Mode Simulation.










- 19 -

3.1 Four-stage QSERL inverter chain schematic.
Here is a four state QSERL inverter chain schematic to analyze the waveforms at each
stage which reveals the applicability of QSERL technology.




Fig. 3.1 Four-stage QSERL inverter chain schematic



- 20 -

3.1.1 Simulation waveforms of a four-stage inverter chain with 1-MHz
input rate and 2-MHz PCs obtained from Cadence.
During the evaluation of each QSERL inverter, the output follows PCs up (down) to HIGH
(LOW). Note that the delay occurs at the output of each stage.


Fig.3.2 Simulation waveforms a four-stage inverter chain

The delay at each stage leads to the erroneous output. And this delay is caused by the
alternative occurrence of hold and evaluate phase this is main drawback of QSERL.
- 21 -

3.2 Four-stage CEPAL inverter chain schematic.

This figure presents a four stage CEPAL inverter chain schematic. This CEPAL inverter
chain schematic gives smooth and perfect output waveforms at each stage in contrast to the
QSERL chain inverter.



Fig 3.3 Four-stage CEPAL inverter chain schematic



- 22 -

3.2.1 Simulation waveforms a four-stage CEPAL inverter chain with 1-
MHz input rate and 2-MHz PCs obtained from Cadence.
The simulation waveform for CEPAL inverter chain. These waveform reveals the driving
capability of CEPAL inverter these are perfect and better than the previous one.


Fig 3.4 Simulation waveforms a four-stage CEPAL inverter chain
The complementary power clock, following the evaluation-used power clock, restores the
output level within a short period of time so as to maintain correct operation of the CEPAL
- 23 -

inverter chain. We may therefore claim that the CEPAL has no hold phase compared to its
QSERL counterpart under the same operation conditions. From another point of view,
throughput for CEPAL is twice as high as for QSERL.

3.3 Analysis of driving ability of QSERL versus CEPAL.
Waveforms represent respectively, input, outputs of stage1 to stage3 of QSERL inverter
chain, PCs, outputs of stage1 to stage3 of CEPAL inverter chain, and outputs of stage4
with respect to the two logic. The two inverter chains were tested under identical input
rate (1MHz) and power clock frequency (2 MHz).


Fig 3.5 Comparative analysis of driving ability of QSERL versus CEPAL

- 24 -

Concluding Remark
Here it is clearly visible from the waveforms that the driving capability of CEPAL
technique is much better than QSERL. From last two waveforms output level shows a
great delay in QSERL while CEPAL have very less or negligible delay.


3.3.1 Average power consumption (in inverter chain) versus frequency.
(Power in nW)

PC 200K 500K 1M 2M 5M 10M 20M 25M
QSERL 48.40 57.28 67.74 82.15 114.80 163.40 247.80 285.20
CEPAL 6.466 15.78 30.91 60.23 97.40 282.6 561.3 697.4

Table 3.1 Average power consumption

From the table 3.1 which reveals the average power dissipation in chain inverter. Here it is
clearly visible that the power dissipation in QSERL technique is much more than the
CEPAL and results verify this. Here after 5MHz frequency power dissipation in CEPAL
technology becomes larger than the QSERL and this is the main disadvantage or limitation
of CEPAL over QSERL. Hence this limitation of CEPAL makes it more effective for low
frequency operations. At high frequencies QSERL proves itself much more effective

3.3.2 Delay in QSERL and CEPAL chain inverter (in ns)

PC 200K 500K 1M 2M 5M 10M 20M 25M
QSERL 2602 1048 530.8 267.0 108.9 55.87 28.78 23.25
CEPAL 427.6 192.4 105.1 57.5 26.01 14.36 8.01 6.20

Table 3.2 Delay in QSERL and CEPAL chain inverter (in ns)
- 25 -

In table 3.2 we analyses the average delay of both inverter chain schematics and results
show the great improvement in delay by CEPAL technique in comparison to the QSERL.
As in previous chapter we discussed about evaluate and hold phases in case of QSERL and
result also proves the drawback of this technique by showing the much larger delay in
comparison to CEPAL technique. In further sections of this chapter we will see how
CEPAL is more effective in flip flops and counters rather than only inverter.
With the analysis, we can discover that QSERL has around output floating time 1/2f longer
than its CEPAL counterpart under the same operation conditions. The main power
dissipation in CEPAL occurs at the (MOS) diodes (nonadiabatic loss), similar to QSERL.
It should be noted that the two more diodes in CEPAL only increase the power dissipation
slightly as there is only one charging or discharging transistor turned on at an instant in
time for the most part.


















- 26 -

3.4 Schematic of QSERL DFF
On the behalf of previous results this circuit presents a master slave QSERL DFF using
transmission gates and inverters and analyse the various parameters. The various
parametric results are listed in forthcoming tables.




Fig. 3.6 Schematic of QSERL DFF

- 27 -

3.5 Schematic of CEPAL DFF
The following figure is a master slave CEPAL DFF working in same manner as previous
one using transmission gates and inverters. The only difference is the biasing technique
used.



Fig. 3.7 Schematic of CEPAL DFF


- 28 -

3.5.1 Comparison of POWER , DELAY and ENERGY for DFFs,

POWER [Watt]
PC 200K 500K 1M 2M 5M 10M 20M 25M
QSERL
DFF
7.50
E-9
25.01
E-9
38.2
E-9
53.3
E-9
104.18
E-9
182.41
E-9
305.14
E-9
373.04
E-9
CEPAL DFF 3.22
E-9
8.18
E-9
16.32
E-9
34.28
E-9
85.01
E-9
183.02
E-9
317.10
E-9
393.03
E-9

Table 3.3 Comparison of POWER

Clk-Q [Seconds]
PC 200K 500K 1M 2M 5M 10M 20M 25M
QSERL DFF 98
E-9
95
E-9
90.8
E-9
88.9
E-9
56
E-9
38
E-9
25.95
E-9
21.76
E-9
CEPAL DFF 39.8
E-9
36.6
E-9
30.6
E-9
24.7
E-9
22.2
E-9
17.9
E-9
12
E-9
9.87
E-9

Table 3.4 Comparison of DELAY

Energy (fJ )
PC 200K 500K 1M 2M 5M 10M 20M 25M
QSERL DFF 0.73 2.37 3.47 4.74 5.84 6.94 7.92 8.12
CEPAL DFF 0.12 0.30 0.50 0.85 1.89 3.29 3.83 3.88

Table 3.5 Comparison of ENERGY

- 29 -

Energy saving [%]
% 83.5 87.3 85.5 82 67.6 52.5 53.6 52.2

Table 3.6 Percentage of energy savings

Simulated power, delay, and energy (power-delay product), under: 1) different PCs speeds;
2) equal switching probability on the input Din; 3) the same transistor sizes and frequency
ratios of the input signals to PCs; 4) identical operation voltages for both. The comparison
of power, delay and energy can easily be carried out on the basis of listed tables.
Table 3.3 reveals power dissipation in master slave DFF using QSERL and CEPAL
technologies and is clearly visible that which one is efficient. CEPAL DFF power
dissipation is too low as comparison to QSERL DFF and shows the same inference as was
in case of inverter chain. Here it can also be seen that after 5MHz frequency it is not as
effective as it was earlier in lower frequency.
In next Tale 3.4 shows the delay occur in these D flip flops using these two schemes and it
can easily be seen that there is a great minimization in delay using CEPAL technology in
comparison to QSERL technique . It can be seen the CEPAL DFF has the energy
efficiency higher than its QSERL counterpart in virtue of the lack of the hold phase for the
same operation conditions. Also, the energy savings regarding the CEPAL cases will be
even higher if the keeper is integrated with the QSERL DFF. As a result, the performance
of CEPAL is verified.







- 30 -

3.6 Schematic of CEPAL J-K FF
Motivated from the previous results here we design a master slave CEPAL J-K FF and
analyse the power dissipation.



Fig 3.8 Schematic of CEPAL J -K FF


- 31 -

3.6.1 Waveforms for CEPAL master slave J-K FF
Following figure shows the waveforms which came after simulation of previously
designed J K FF.



Fig. 3.9 Waveforms for CEPAL master slave J -K FF

Here we have not presented the QSERL JK FF because the waveforms from this technique
were not so proper to analyse. And this is due to the unwanted delay from the evaluation
- 32 -

and hold phases. While its counterpart CEPAL gives smooth and clear pattern and results
show the effectiveness. Figure 3.9 shows the waveforms of an edge triggered J K_FF and
we can easily see that the waveform are smooth and tends towards the perfectness.

3.7 Counter from CEPAL master-slave J-K FF
Here circuit utilize the previously made CEPAL master slave J-K FF to design a counter.
And the analysis of this 3bit synchronous counter will be made next subsequent
sections.


Fig 3.10 Counter from CEPAL master-slave J -K FF

This 3 bit synchronous counter contains 3 CEPAL master slave J K FF along with one
CEPAL and gate.
- 33 -

3.7.1 Waveforms for counter
Here are the simulation waveforms for CEPAL 3 bit synchronous counter.


Fig. 3.11 Waveforms for a counter

- 34 -

3.8 Analysis of power and delay of CEPAL J-K FF and COUNTER at
various pc frequencies

Power (watt)
PC 200K 500K 1M 2M 5M 10M 20M 25M
CEPAL
J-K FF
45.202
E-9
103.4
E-9
115.50
E-9
356.70
E-9
836.3
E-9
1.596
E-6
3.083
E-6
3.75
E-6
CEPAL
COUNTR
151.1
E-9
250.4
E-9
475.1
E-9
906.3
E-9
2.135
E-9
4.084
E-6
6.812
E-6
9.21
E-6

Table 3.7 Analysis of power for CEPAL J K FF and CEPAL COUNTER

Delay (seconds)
PC 200K 500K 1M 2M 5M 10M 20M 25M
CEPAL
J-K FF
4.064
E-9
2.336
E-6
790.4
E-9
498.1
E-9
198.4
E-9
98.61
E-9
48.71
E-9
38.72
E-9
CEPAL
COUNTR
4.996
E-6
2.980
E-6
997.7
E-9
500.2
E-9
198.5
E-9
98.65
E-9
50.20
E-9
39.3
E-9

Table 3.8 Analysis of delay for CEPAL J K FF and CEPAL COUNTER

The analysis of power and delay for CEPAL J K FF and CEPAL COUNTER are shown in
above listed tables 3.7 and 3.8 respectively and we can see the delay and power variations
with the high frequencies.




- 35 -

CHAPTER 4
CONCLUSION

Adiabatic techniques have been effective means to power minimization in deep sub-micron
VLSI systems. In this report, we discussed a newly developed ERL family termed CEPAL
for low-power design. The proposed logic style outperforms those currently demonstrated
in irreversible energy recovery literature in terms of several aspects. Specifically, we
presented the efficiency of the DFFs made up of QSERL and the proposed logic style. And
at the last we design a counter from CEPAL master-slave J K FF that is highly efficient
from other techniques. The power saving in these circuits is because of:
1. The energy stored in the load capacitor is pumped back into the supply to realize a
transition from 1 to0.
2. Charging and discharging takes place throughout the cycle of supply voltage, hence
saves more energy.
3. There is no short circuit current from the supply to ground at any time during the
transition of logic 1 to logic0 unlike in CMOS circuit.
It has been shown that CEPAL approach generally results in a saving of upto 87% of what
is normally dissipated in similar QSERL circuits. Since the impact of leakage on CEPAL is
of trifling importance[11], low- Vt devices can be introduced so as to minimize the non
adiabatic loss, enabling higher circuit performance. Such low- Vt devices have been
available in the processes 0.25 m and beyond.
If we talk about cost and efficiency since each single CEPAL has two more diodes over
those involved in QSERL, it results in higher implementation cost when designing a large
system. The ERL, as such, are suitable for middle- or low- speed operation. It is therefore
possible to share the diodes among certain stages for both the logic styles without
increasing the channel widths of the diodes and sacrificing the driving ability as the
switching current draw in the ERL has been dramatically decreased. It is deserved to be
mentioned that owing to the interlaced phases in QSERL, the two logic have the same cost
when using the share scheme.


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