Sunteți pe pagina 1din 10

Different cells used for Low Power Design - Power management Techniques ~ VLSI Basics And Interview Questions

file:///C|/Users/COMSOL/Desktop/isolation%20cells,%20power%20witches%20,retention%20registers.htm[7/16/2014 8:05:39 PM]


Different cells used for Low Power Design - Power
management Techniques
Level Shifters, Isolation Cells, Retention
Registers, Power Switches, Always on
Cells
Level Shifters:
Level Shifters are used in multi voltage design in which more than
one voltage supply used. Consider In your design two voltage
domains are there. One voltage domain V1 has 1.2V power supply
another domain V2 has 1V power supply. Signal has to cross from
one domain to another domain while in functional mode. Now
assume signal crossing from Low voltage domain V2 to High

Get this

VLSI Basics And Interview Questions


This Blog is created for Basic VLSI Interview Questions. This content is purely VLSI Basics.


Different cells used for Low Power Design - Power management Techniques ~ VLSI Basics And Interview Questions
file:///C|/Users/COMSOL/Desktop/isolation%20cells,%20power%20witches%20,retention%20registers.htm[7/16/2014 8:05:39 PM]
voltage domain V1, It's logic is interpreted wrongly at V1. To
prevent this level shifters are inserted between the different voltage
domains for the signals which cross from low voltage domain to
High voltage domain and from High voltage domain to low voltage
domains.
The main functionality of the level shifters is to shift the voltage
one voltage to another voltage level depending upon the the signal
crossing different voltage domains.
Isolation Cells:
Isolation cells are used between the domains. Consider there are
two domains are in your design i.e,. D1 and D2. The domain D1 is
power shut down mode and other domain D2 is in active mode.
Since Domain D1 is power down mode it can propagate invalid
logic to domain D2. To prevent this, Isolation cells are inserted
between the domains to clamp a known value at its output, While
domain D1 is shut down mode. Isolation cells should be placed in
always on domain to serve it's functionality (clamp the known value
to the other domain)
Power Switches:
Power switches are used in power gating technique. As we
already discussed in previous post, Power gating is used to reduce
the static (Leakage) power in the design. Power gating is performed
by shutting down the power for portion of design. Power switches
are used to turn off the portions of design which are inactive at a
point of time to reduce leakage power.
Different cells used for Low Power Design - Power management Techniques ~ VLSI Basics And Interview Questions
file:///C|/Users/COMSOL/Desktop/isolation%20cells,%20power%20witches%20,retention%20registers.htm[7/16/2014 8:05:39 PM]
Retention Registers:
Retention Registers are used to store register states before power
down mode. These values will be restored when power is up. So
retention cells should be always on to serve the purpose. As these
are always on, It can consume power even power down mode.
Always On cells:
These cells are special cells which should be always on to their
purpose.

11:03

KHADAR BASHA

NO COMMENTS
Related Posts:
VLSI Compani es (Pr oduc t Based) i n I ndi a
VLSI Companies in India 1. Intel (Intel Technology India Pvt Ltd) 136 Airport Road,
Bangalore, Karnataka, India Unit 03, No 65/2 Bagmane Tech, Byrasandra in Ward
no. 83, Bangalore, Karnataka, India 4 Floor, Read More
St at i c Ti mi ng Anal ysi s (STA) Over vi ew
Timing Analysis: Timing Analysis is a method of validating the timing performance of
a design. i.e. How fast the design is going to operate. Timing Analysis can be done
in 2 ways 1. Static Timing Analysis (STA) 2. Dynam Read More
I R Dr op Anal ysi s I nt er vi ew Quest i ons
IR Drop Analysis Interview Questions 1. What is IR Drop Analysis? A. The power
supply in the chip is distributed uniformly through metal layers (Vdd and Vss) across
+1 Recommend this on Google
Different cells used for Low Power Design - Power management Techniques ~ VLSI Basics And Interview Questions
file:///C|/Users/COMSOL/Desktop/isolation%20cells,%20power%20witches%20,retention%20registers.htm[7/16/2014 8:05:39 PM]
0 comments:
Post a Comment

Newer Post Older Post Home
Internet Marketer Function Web Designers Widgets Design By Feed
Writing a business plan Performance Management Download open office Or Library
the design. These metal layers have finite Read More
I R Dr op Anal ysi s usi ng Redhaw k - Over vi ew
IR Drop Analysis using Redhawk: Redhawk performs several types of power analysis
on a circuit. Static Voltage (IR) drop with average cycle currents Dynamic Voltage
drop with worst-case switching currents Electromigration Read More
Physi c al Desi gn Fl ow Pr ac t i c al Appr oac h w i t h I C Compi l er
(Synopsys)
Physical Design Flow Practical Approach with IC Compiler (Synopsys) The general
ICC flow is as shown in figure 1. The first step in ICC Flow is Data Setup. In this step, we create
Container which is known as Design Read More
Different cells used for Low Power Design - Power management Techniques ~ VLSI Basics And Interview Questions
file:///C|/Users/COMSOL/Desktop/isolation%20cells,%20power%20witches%20,retention%20registers.htm[7/16/2014 8:05:39 PM]
Notify me
Comment as:

Popular Posts
Static Timing Analysis (STA) Interview Questions
Static Timing Analysis Interview Questions Static Timing Analysis plays major role in physical
design(PD) flow. It checks the design...
IR Drop Analysis
What is IR Drop Analysis? How it effects the timing? The power supply in the chip is distributed
uniformly through metal layers (Vdd a...
Physical Design (PD) Interview Questions - Floorplanning
1. What is floorplaning? A. Floor planing is the process of placing Blocks/Macros in the chip/core
area, thereby determining ...
Clock Tree Synthesis (CTS) - Overview
Clock Tree Synthesis Clock Tree Synthesis (CTS) is the process of inserting buffers/inverters along
the clock paths of the ASIC design to...
Low Power Design
Power Planning: Power is limiting factor affection performance and features in most important
products. When you decided to buy a mobile,...
IR Drop Analysis Interview Questions
IR Drop Analysis Interview Questions 1. What is IR Drop Analysis? A. The power supply in the chip is
distributed uniformly through met...
Static Timing Analysis (STA) Overview
Publish Preview
Different cells used for Low Power Design - Power management Techniques ~ VLSI Basics And Interview Questions
file:///C|/Users/COMSOL/Desktop/isolation%20cells,%20power%20witches%20,retention%20registers.htm[7/16/2014 8:05:39 PM]
Timing Analysis: Timing Analysis is a method of validating the timing performance of a design. i.e.
How fast the design is going to oper...
Physical Design Flow
Physical Design Flow: The design flow of the physical implementation is mentioned above in the
figure. The physical design stag...
Basic Terminology in Physical Design
Design: A circuit that performs one or more logical functions. Cell: An instance of a design or library
primitive within a design. P...
Power Planning - Power Network Synthesis (PNS)
Power Planning - Power Network Synthesis (PNS) In ICC Design Planning flow, Power Network
Synthesis creates macro power rings, creates th...
Blog Archive
2014 (5)
April (2)
March (1)
February (2)
Different cells used for Low Power Design - Power ...
Physical Design Flow Practical Approach with IC ...
2013 (21)
Recent Posts

Different cells used for Low Power Design - Power management Techniques ~ VLSI Basics And Interview Questions
file:///C|/Users/COMSOL/Desktop/isolation%20cells,%20power%20witches%20,retention%20registers.htm[7/16/2014 8:05:39 PM]
Definition List
Text Widget
Pages
Home
Site Index - Content
VLSI Interview Questions
VLSI Video Tutorials
VLSI Books
About Us - Contact Us
Total Pageviews
4 2 6 3 1
Different cells used for Low Power Design - Power management Techniques ~ VLSI Basics And Interview Questions
file:///C|/Users/COMSOL/Desktop/isolation%20cells,%20power%20witches%20,retention%20registers.htm[7/16/2014 8:05:39 PM]
Copyright @ VLSI Basics Team . Powered by Blogger.
Physical Design Tutorials

Follow by Email
Contributors
vlsi.projectguru
khadar basha
VLSI Basics Team
+1
Submit
Different cells used for Low Power Design - Power management Techniques ~ VLSI Basics And Interview Questions
file:///C|/Users/COMSOL/Desktop/isolation%20cells,%20power%20witches%20,retention%20registers.htm[7/16/2014 8:05:39 PM]
+1 Recommend this on Google
Follow us on Twitter Now
Fol l ow @VLSI Basi c s 4 followers
Search This Blog
Infolinks Text Ads
Subscribe To
Posts
Search
Different cells used for Low Power Design - Power management Techniques ~ VLSI Basics And Interview Questions
file:///C|/Users/COMSOL/Desktop/isolation%20cells,%20power%20witches%20,retention%20registers.htm[7/16/2014 8:05:39 PM]
COPYRIGHT 20142014 VLSI BASICS AND INTERVIEW QUESTIONS | POWERED BY
BLOGGER
DESIGN BY AUTOMATTIC | BLOGGER THEME BY NEWBLOGGERTHEMES.COM
Comments

S-ar putea să vă placă și