Project Number: MQP-SJB-1A03

Solar Panel Peak Power Tracking System

A Major Qualifying Project
Submitted to the Faculty
of
WORCESTER POLYTECHNIC INSTITUTE
In partial fulfillment of the requirements for the
Degree of Bachelor Science
March 12, 2003
By
Eric Anderson
Chris Dohan
Aaron Sikora
Professor Stephen J. Bitar
Professor John A. McNeill
Abstract
The design of a Maximum Peak Power Tracking (MPPT) controller for a solar
photovoltaic battery charging system is proposed utilizing a boost-converter top
ology. Solar
panel voltage and current are continuously monitored by a closed-loop microproce
ssor based
control system, and the duty cycle of the boost converter continuously adjusted
to extract
maximum power. System testing confirms peak power tracking under changing lighti
ng
conditions. Under specific conditions, efficiencies in excess of 90% are shown t
o be possible.
Acknowledgements
We would like to thank Professor Stephen J. Bitar and John A. McNeill for their
more
than helpful contributions over the course of the project. We would also like to
thank them for
use of the analog lab and all of its equipment.
Table of Contents
2.0 Background .................................................................
.............................................................. 8
2.1 Solar Panel Phenomenology ..................................................
............................................... 8
2.1.1 Solar Power Fundamentals .................................................
........................................... 8
2.1.2 Efficiency ...............................................................
........................................................ 8
2.1.3 Voltage-Current (V-I) Characteristic .....................................
...................................... 10
2.2 Insolation Levels ..........................................................
....................................................... 13
2.3 Charge Controllers .........................................................
..................................................... 16
2.4 Storage Batteries ..........................................................
....................................................... 18
2.5.1 Multiple Panels per MPPT..................................................
......................................... 20
2.5.2 Individual MPPT per Panel.................................................
......................................... 21
2.5.3 The Best Approach ........................................................
.............................................. 23
3.0 Methodology ................................................................
........................................................... 24
3.1 System Block Diagram .......................................................
................................................ 24
3.2 Battery Requirements........................................................
.................................................. 25
3.3 Boost Converter Description.................................................
.............................................. 27
3.3.1 Stage One: Initial Conditions.............................................
......................................... 30
3.3.2 Stage Two: Switch Closing.................................................
........................................ 30
3.3.3 Stage Three: Switch Opening ..............................................
....................................... 32
3.3.4 Stage Four: On and off switching .........................................
...................................... 34
3.4 Boost Converter System Equations ...........................................
......................................... 36
3.4.1 Thevenin Equivalent ......................................................
.............................................. 37
3.4.2 Average Current ..........................................................
................................................. 39
3.4.3 Current Ripple............................................................
.................................................. 43
3.4.4 Voltage Equations ........................................................
................................................ 44
3.4.5 Equivalent Resistance and Power Equations ................................
............................... 46
3.4.6 Equation Accuracy.........................................................
.............................................. 46
3.5 Current Sensing Methods.....................................................
............................................... 48
3.5.1 Inductor Current Sensing .................................................
............................................ 49
3.5.2 Current Sensing Conclusion ...............................................
......................................... 54
4.0 Implementation .............................................................
.......................................................... 58
4.1 Parts Selection.............................................................
........................................................ 58
4.1.1 MOSFET Selection .........................................................
............................................. 58
4.1.2 Inductor Selection .......................................................
................................................. 63
4.1.3 Instrumentation Amplifier ................................................
........................................... 71
4.1.4 Diode Selection ..........................................................
.................................................. 74
4.1.5 Voltage Regulator ........................................................
................................................ 75
4.1.6 MOSFET Gate Driver .......................................................
........................................... 76
4.2 Operating Frequency.........................................................
.................................................. 77
4.3 Voltage Sensing ............................................................
...................................................... 79
4.4 Current Sensor .............................................................
....................................................... 84
4.4.1 Alternative Methods.......................................................
.............................................. 85
4.4.2 Gain setting .............................................................
..................................................... 87
4.4.3 Initial Testing ..........................................................
..................................................... 90
4.4.4 Common Mode Voltage.......................................................
........................................ 92
4.4.5 Differential Voltage .....................................................
................................................ 94
4.4.6 Common Mode Rejection Ratio (CMRR) .......................................
............................ 96
4.4.7 Common Mode Range ........................................................
....................................... 102
4.4.8 Output Filter ............................................................
................................................... 104
4.4.9 Current Sensing Schematic ................................................
........................................ 106
4.5 Controls....................................................................
......................................................... 107
4.5.1 Simulation ...............................................................
................................................... 111
4.6 Microprocessor .............................................................
.................................................... 126
4.6.1 Algorithm ................................................................
................................................... 132
4.7 Self Powering ..............................................................
...................................................... 135
4.7.1 24-Volt Supply............................................................
............................................... 135
4.7.2 5-Volt Supply.............................................................
................................................ 137
5.0 Power Loss Analysis ........................................................
..................................................... 140
5.1 Operating Losses............................................................
................................................... 140
5.2 Diode Losses ...............................................................
...................................................... 142
5.3 IC Losses...................................................................
........................................................ 144
5.4 Overall MPPT Efficiency ....................................................
............................................. 146
6.0 Results.....................................................................
.............................................................. 148
6.1 Thevenin Equivalent ........................................................
................................................. 148
6.2 Indoor Testing .............................................................
...................................................... 153
6.3 Outdoor Testing ............................................................
.................................................... 158
7.0 Future Recommendations .....................................................
................................................ 164
8.0 Conclusions.................................................................
.......................................................... 165
References .....................................................................
.............................................................. 166
Appendix A: Schematic ..........................................................
.................................................... 167
Appendix B: Datasheets..........................................................
.................................................... 168
AD627 ..........................................................................
........................................................... 168
IRL7833 ........................................................................
.......................................................... 184
MBRD1040CT......................................................................
.................................................. 196
PIC16F87XA .....................................................................
..................................................... 199
Appendix C: MPPT Code ..........................................................
................................................. 216
1.0 Introduction
Solar power is an alternative technology that will hopefully lead us away from o
ur
petroleum dependent energy sources. The major problem with solar panel technolog
y is that the
efficiencies for solar power systems are still poor and the costs per kilo-watt-
hour (kwh) are not
competitive, in most cases, to compete with petroleum energy sources. Solar pane
ls themselves
are quite inefficient (approximately 30%) in their ability to convert sunlight t
o energy. However,
the charge controllers and other devices that make up the solar power system are
also somewhat
inefficient and costly. Our goal is to design a Maximum Power Point Tracker (MPP
T), a specific
kind of charge controller that will utilize the solar panel to its maximum poten
tial.
The MPPT is a charge controller that compensates for the changing Voltage vs. Cu
rrent
characteristic of a solar cell. The MPPT fools the panels into outputting a diff
erent voltage and
current allowing more power to go into the battery or batteries by making the so
lar cell think the
load is changing when you really are unable to change the load. The MPPT monitor
s the output
voltage and current from the solar panel and determines the operating point that
will deliver that
maximum amount of power available to the batteries. If our version of the MPPT c
an accurately
track the always-changing operating point where the power is at its maximum, the
n the
efficiency of the solar cell will be increased.
There are many different applications for solar power systems, but there are als
o many
limitations to these applications. The cost-benefit is too low for solar power s
ystems to be
widely used for powering homes, businesses, or even individual products. Solar p
ower systems
are used as the main power source for a large majority if not all of the satelli
tes that orbit the
earth. However, the benefit of utilizing solar power in space far outweighs the
cost to implement
them. There are wide ranges of different products available to the consumer that
are solar
powered, but they can be expensive or impractical because of their limitations.
Solar power
systems are not competitive on the market because consumers are familiar with th
e practical,
more convenient products that have more common power sources that they are used
to. Some
consumer products are radios, flashlights, motor-home trickle charging systems,
outdoor solar
lighting, laptop charging systems, and even home systems that can be tied to the
ir existing power
grid. Some of the more practical applications are used for remote locations such
as cabins or
small villages that are located far from the closest power grid. As a result, th
e cost to install a
solar power system is cheaper than the cost to send transmission lines from the
power grid. Solar
powered systems are also very convenient in small applications such as powering
calculators,
outdoor lighting, and even traffic lights.
By attempting to make solar panel systems more efficient altogether, solar power
ed
products could be used more commonly. While solar panels are not very efficient
due to their
current limitations, we hope to extract the maximum amount of possible power fro
m the solar
panel with our MPPT device. This is just one aspect of making solar power more e
fficient. The
actual manufacturing of solar panels is important and is not something that we a
re able to take on
in this project. There are many important factors that determine the amount of p
ower the solar
panels can extract from the sun including temperature, time of year, geographic
location, and
positioning of the sun. These factors can be minimized by designing a proper sys
tem that can
monitor the output of the solar cell and extract the maximum amount of possible
power from the
solar panels.
In order to enable us to complete this project in an effective manner we need to

understand the solar technology and the most important aspects of it. We will lo
ok at different
applications and whether or not they are even feasible at the current state of s
olar technology.
After understanding more about the technology that solar power involves and the
different
applications that it is used for, we can then approach our problem for a specifi
c application and
design the best solar panel peak power tracking system.
2.0 Background
2.1 Solar Panel Phenomenology
2.1.1 Solar Power Fundamentals
The amazing thing about solar power is that all the electricity is generated fro
m the
material of the solar panels and the energy from the sun. The solar panels are m
ainly made out
of semiconductor material, Silicon being the most abundantly used semiconductor.
The benefit
of using semiconductor material is largely due to the ability of being able to c
ontrol its
conductivity whereas insulators and conductors cannot be altered. The electrons
of the
semiconductor material can be located in one of two different bands: the conduct
ion band or the
valence band. The valence band is initially full with all the electrons that the
material contains.1
When the energy from sunlight, known as photons, strikes the electrons in the se
miconductor,
some of these electrons will acquire enough energy to leave the valence band and
enter the
conduction band. When this occurs, the electrons in the conduction band begin to
move creating
electricity. As soon as the electron leaves the valence band, a positively charg
ed hole will
remain in the location the electron departed. When this occurs, the valence band
is no longer full
and can also play a role in the current flow. This process basically describes h
ow Photovoltaic
(PV) systems function. However, PV systems further enhance the rate at which the
electrons are
sent into the conduction band through the process of doping.2
2.1.2 Efficiency
Solar power would be the leading source of energy if it were able to efficiently
extract a
majority of the energy delivered to the earth from the sun on a daily basis. On
the equator at
noon, 1000 watts/m2 of sun energy touches the ground. Unfortunately only about 2
0 percent of
this power can be transferred into usable energy. This inefficiency is directly
related to the
percentage of photons that are absorbed. The electrons in the semiconductor mate
rial will only
jump into the conduction band if they absorb a photon. The photons can either be
absorbed,
1 Sayigh, A.A.M., ed. Solar Energy Engineering. New York: Academic Press, 1977.
2 Neville, Richard C. Solar Energy Conversion. The Netherlands: Elsevier Science
, 1995.
reflected, or can even pass right through the semiconductor.3 In order to increa
se the number of
photons absorbed ultimately increasing the efficiency of the solar panel, the pe
rcentage of
photons that pass through and reflected must be reduced. There is an obvious los
s of electric
potential when the photons are reflected off the semiconductor material. To redu
ce the
percentage of reflected photons, an anti-reflective coating is usually put on th
e semiconductor,
which will decrease the number of reflected photons increasing the total number
of photons that
will become absorbed. However, there is still a chance that these photons could
pass right
through the material without striking an electron.
Some of the photons from light pass straight through the semiconductor as if the

semiconductor were transparent. The photons in sunlight have a wide variety of d
ifferent
wavelengths causing some to pass right through.4 The photons that pass through t
he
semiconductor have energy lower than the band gap energy of the semiconductor.5
As a result,
these photons do not contain enough energy to create an electron-hole pair, so t
he photon just
passes right through the semiconductor.6 If the photon has more energy than the
band gap of the
semiconductor, then the electrons absorb the photon. However, if the photon has
an excess of
energy, meaning it gives the electron more energy than the band gap, than this e
xcess will be
emitted as a form heat and the electron will settle down in the conduction band.
To minimize the
amount of photons that pass through the semiconductor, some semiconductors are m
anufactured
with many layers, each having a different band gaps in order to better match the
light spectrum.
A highly efficient solar panel can be designed by cascading semiconductor materi
als with
different band gaps to perfectly match the light spectrum. However, this would r
equire an
infinite amount of semiconductor material making it utterly impossible. For the
solar panels to
be cost-effective, the can only be designed with a few different layers. As a re
sult, there are still
some photons that pass right through the semiconductor and the energy lost from
the absorbed
photons as a form of heat.
Solar power is an amazing technology in the sense that it converts sunlight into
electricity
through the semiconductor material alone. However, it is clear that there are ma
ny flaws and
3 Turning Sunlight into Electricity. Nation Center for Photovoltaics. 20 Oct. 2002
.
<http://www.eren.doe.gov/pv/siatomic.html>
4 Aldous, Scott. How Solar Cells Work. How Stuff Works. 02 Nov. 2002.
<http://fitness.howstuffworks.com/solar-cell.htm?printable=1>
5 Neville, Richard C. Solar Energy Conversion. The Netherlands: Elsevier Science
, 1995.
6 Aldous, Scott. How Solar Cells Work. How Stuff Works. 02 Nov. 2002.
<http://fitness.howstuffworks.com/solar-cell.htm?printable=1>
complications in the ability to design a solar panel that can utilize a majority
of the energy that is
emitted from the sun on a daily basis. There are numerous ways to design and man
ufacture solar
panels. The uses of different kinds of semiconductor materials, crystal structur
es, and
manufacturing methods all have a different affect on the efficiency and cost of
the solar panel.
One crystal structure may be more efficient, but the cost may make it too expens
ive to consider.
As time goes on, newer manufacturing techniques and designs will prove these sol
ar panels more
efficient and less costly in future years. Rather than focusing on the issues re
lating to the design
and semiconductor physics behind the solar panels themselves, this project will
focuses more on
the devices that control the output of the solar panels. A solar panels output va
ries depending
on certain ambient weather conditions such as temperature, illumination, how cle
ar the sky is, so
on and so forth. Our task at hand is to design a device that will extract the ma
ximum amount of
power from the solar panels, regardless of how efficient or inefficient the sola
r panels may be.
2.1.3 Voltage-Current (V-I) Characteristic
Extracting the maximum amount of power from the solar panel is difficult due to
the
nonlinearity of the Voltage-Current (V-I) characteristic. Figure 2-1 shows the V
-I characteristic
for SolarCorps 379 Solar Panel.
Figure 2-1: Characteristic of Solar Corp 379 Panel
The blue line in Figure 2-1 is the actual V-I characteristic and the pink line c
orresponds to the
power as a function of the voltage (P = I*V). As you can see, the voltage to cur
rent relationship
is not linear, which makes it a little more difficult to determine the maximum p
ower point. The
maximum power point on a linear curve would occur at the midpoint of the V-I cha
racteristic.
However, in the case of a nonlinear relationship, the power needs to be determin
ed by
calculating the voltage to the current. To get the maximum power from the solar
panel, the solar
panel must always be operated at or very near the point where the power curve is
at a maximum,
its peak point. However, this operating point will constantly change due to the
constantly
changing ambient conditions. In fact, the temperature and other affects such as
irradiance alter
the V-I characteristic changing the operating point that would allow us to pull
out the maximum
amount of power. As a result, we need to constantly track the power curve and ke
ep the solar
panel operating at the point where the maximum amount of power would be achieved
.
Irradiance is a characteristic that deals with the amount of sun energy reaching
the
ground. The irradiance reaching the earth in ideal conditions is 1000W/m2 . Howe
ver, this value
is altered significantly depending on where you are located geographically, the
angle of the sun,
and the amount of haze or cloud cover preventing all of the suns energy from rea
ching the
ground. Since solar panels run strictly off the energy emitted from the sun, the
ir output is
affected by the changing irradiance. The Figure 2-2 below demonstrates the affec
t irradiance has
on the output of solar panels.
Figure 2-2: Solar Panel V-I Characteristic vs. Irradiance
As you can see in Figure 2-2, a smaller irradiance or light intensity gives you
a reduced output.
However, only the output current is really affected by the changing irradiance.
This is due to the
generated current being proportional to the flux of the photons. If less light o
r weaker light is
striking the solar panels, then the flux of photons is going to be lower than mo
re powerful
sunlight resulting in a reduced generated current. The voltage on the other hand
is hardly
affected by the change in irradiance. In fact, the change is so small that in th
e change in voltage
is considered negligible and disregarded in most practical applications. The ope
n circuit voltage
is the voltage level at the point when there is no current flow. As a result, th
e voltage is
somewhat independent of the changing flux of photons resulting in very small cha
nges in open
circuit voltage. The open circuit voltage does however depend logarithmically on
the irradiance,
which explains the small changes in open circuit voltage.7 The irradiance is a v
ery important
factor in predicting the V-I characteristic of the solar panel, but the temperat
ure of the panels
also plays a very important role in predicting the V-I characteristic.
The temperature of the solar panels plays just as significant a role in determin
ing the
output of the solar panels. Typically, you would expect the solar panels to oper
ate more
efficiently with a higher temperature. However, Figure 2-3 below shows otherwise
.
Figure 2-3: Solar Panel V-I Characteristic vs. Temperature
7 Bogus, Klaus and Markvart, Tomas. Solar Electricity. Chichester, New York.
Wiley Press, 1994.
As shown in Figure 2-3 above, the output does in fact increase with decreasing t
emperature.
There are many factors in determining why this occurs. A huge reason is due to t
he electron and
hole mobility of the semiconductor material. As the temperature rises, the elect
ron and hole
mobility in the material decreases significantly. The electron mobility for a Si
licon
semiconductor solar panel will decrease from 1700 cm2/volt-sec at 27oC to 440 cm
2/volt-sec at
227oC where the hole mobility will decrease from 600 cm2/volt-sec at 27oC to 200
cm2/volt-sec
at 227oC.8 These test temperatures are unrealistic operating conditions for sola
r panels, but do
get the point across that the electron and hole mobility decrease as the tempera
ture rises.
Temperature also causes the band gap energy of the semiconductor material to inc
rease. The
photons from the sun provide the electrons in the valence band of the semiconduc
tor with the
energy to leap over the band gap into the semiconductor material. With larger ba
nd gap energy,
the electrons will require more energy from the photons in the sun to reach the
conduction band.
As a result, fewer electrons will reach the conduction band giving us a less eff
icient solar cell.
These changes in temperature and irradiance make the V-I characteristic near imp
ossible
to predict or control. The only thing we have control over is the operating poin
t of the solar
panel. Without control over this operating point, the output of the solar panels
will be very
unpredictable resulting in an even more inefficient solar power system.
2.2 Insolation Levels
Insolation levels are a measure of how much sunlight energy is delivered to a sq
uare
meter over a single day. The suns energy is most powerful at the equator at solar
noon, or when
the sun is directly overhead. The suns energy will be dramatically decreased by t
he earths
atmosphere. Energy will also be lost because of the angle of reflection against
the solar panel.
The suns energy is strongest when it is straight overhead, where the earths atmosp
here, and the
solar panels reflection has the least affect.
Insolation levels measure the amount of energy in watt-hours for a square meter
over a
single day in Kwh/m2/day. Insolation level units are not always stated, and can
be seen as a ratio.
Therefore we will intentionally leave the units off. The suns energy varies as th
e sun moves
from the horizon to directly overhead. The insolation level is an equivalent sol
ar energy level.
8 Neville, Richard C. Solar Energy Conversion. The Netherlands: Elsevier Science
, 1995
The suns energy at the equator at solar noon is equal to 1000 watts per square me
ter. In effect,
we are finding the amount of equivalent hours the sun has put out 1000 watts per
square meter.
Although the sun may have been shining at 500 watts per square meter for 8 hours
, there is only
4 equivalent hours of 1000 watts per square meter. Insolation levels give an eas
y way to compare
sunlight energy levels between locations as well as find typical solar and batte
ry requirements for
a given location.
An insolation level between one and two is considered to be low. Four and five a
re
considered to be moderate and seven to eight is high. The map in Figure 2-4 show
s the
insolution, or the number of full hours of sun any location in the United States
gets per day on a
worst-case average.
Figure 2-4: Worst Case Insolation Levels for the U.S.
Again these are worst-case values. NASA has done extensive research on this subj
ect and
has data for most locations in the world based on at least ten years of data. Th
e average
insolation levels in Massachusetts are located in Table 2.1. The Clear Sky colum
n shows the
insolation levels with a perfectly clear sky.
Location: Worcester, MA N 38 20 W 75 30
Average Clear Sky Solar Tracking
January 1.51 3 2.53
February 2.34 4.32 3.27
March 3.18 5.99 3.68
April 4.78 7.48 5.07
May 5.68 8.24 5.73
June 6.63 8.3 6.66
July 6.75 8 6.76
August 6.26 7.11 6.54
September 5.03 5.78 5.86
October 3.3 4.47 4.78
November 2 3.21 3.44
December 1.32 2.61 2.37
Average 4.07 5.71 4.72
Table 2-1: Insolation Levels in Massachusetts in kWh/m2/day
Notice that the summer months have significant more energy available. It is ofte
n
common for solar panels to be backed up by a generator to supply power for the w
inter months.
We can use the solar panels more efficiency by angling them towards the sun. Sun
tracking
mounts designed for solar cells exist now. These self powered mounts point the s
olar cells
directly to the sun to get the most amount of solar power. Of course this also u
ses some of the
energy from the solar cell itself. NASAs database also has collected insolation l
evels for this
and assuming the optimal angle is always set the average insolation levels impro
ve slightly. The
average insolation levels are shown in the solar tracking column above in Table
2.1. Here the
yearly average was 4.07. With solar tracking, this number is improved 16% to 4.7
2.
Our solar panel is not rated in just efficiency but instead how many watts it ca
n produce.
The solar panel we have been provided with is 50W. If this panel is producing 50
W under ideal
conditions (1000W/m2) then we can expect to draw four times as much as that per
day in
Massachusetts since the insolation level is 4000W/m2 . Therefore we can expect t
o store an
equivalent of 50W for four hours, or a more standard form to state this is 200W
of power for one
hour or 200Wh. The storage of this power depends greatly on the sun. We can expe
ct the most
amount of power while the sun is around solar noon. Before and after solar noon,
we can expect
lower power levels. Therefore we are not storing 200W in one hour, but an equiva
lent to that. In
other words, after a full day of charging, we will have 200Wh available.
Sunlight energy around the world varies considerably. The closer to the equator,
the more
sunlight energy is available throughout the year. This is the most ideal place f
or solar electricity.
Other places, such as London have very low yearly averages and are not practical
to use solar
technology. Remote locations that are far away from power grids also provide a p
ractical use for
solar technology. Table 2.2 contains the average insolation level per year for t
hree different
locations around the world.
Worcester, MA
(N38 20 W75 30)
Kenya
(N0 12 E37 29)
London, UK
(N51 31 W0 04)
Average Insolation Level
(kWh/m2/day)
4.06 5.85 2.69
Yearly Low
(monthly average in kWh/m2/day)
1.32 4.94 0.52
Table 2-2: Comparing Insolation Levels across the Globe
2.3 Charge Controllers
Solar panels are almost always charging some type of battery. Overcharging some
types
of batteries can damage the battery. Also, the battery voltage determines the vo
ltage level at
which the solar panel will operate. However, operating at this voltage level pro
bably will not be
the most efficient for the solar panel. Due to these two reasons, charge control
lers are commonly
put in between the solar panels output leads and the storage batteries. There are
three different
kinds of charge controllers that are commonly used. There are basic charge contr
ollers, PWM
charge controllers, and Maximum Peak Power Tracker (MPPT) charge controllers.
The basic charge controller is designed to protect the battery from any form of
damage
due to overcharge or undercharge and prevents any reverse current that may be dr
awn from the
battery during the time period in which the solar panels are not generating any
power.
Overcharging some types of batteries can damage the battery as well as cause pos
sible
explosions or leaking. If energy is continually applied to the battery after it
has reach full
capacity, then the battery voltage will raise causing chemical reactions, which
will eventually
overheat the battery and damage it. To prevent overcharge, the charge controller
simply monitors
16
the charge going into the battery and regulates the voltage level sent to the ba
ttery to prevent any
further charging once a certain maximum capacity level is reached. The batteries
life cycle will
be dramatically shortened if the batteries are undercharged for to long a period
of time. In this
situation, the charge controller will disconnect the battery, known as Low Volta
ge Disconnect
(LVD), from any loads (lamps, appliances, etc.) once a certain capacity is reach
ed in order to
prevent the battery from losing any more charge. The basic charge controllers ar
e essential to
proper charging of batteries in order to protect the batteries from damage.
PWM charge controllers are similar to the basic charge controller. While basic c
harge
controllers can only disconnect or connect the battery to stop overcharging, PWM
charge
controllers can actually control the amount of current charging the batteries in
order to optimize
the charging time. When the battery nears full capacity, the PWM charge controll
er switches the
charging on and off using PWM (pulse width modulation) causing a trickle charge, w
hich
allows the battery to maintain a full charge. This feature optimizes the speed a
nd efficiency of
charging the battery.9 PWM and basic charge controllers both control the current
going into the
battery but do not attempt to optimize the efficiency of the solar panel. Maximu
m Peak Power
Trackers (MPPT) charge controllers can optimize the power output from the solar
panel, as well
as charge the battery up to its optimal charge capacity.
The problem with the PWM charge controller and basic charge controllers is that
they
operate the solar panels at the voltage level designated by the voltage level of
the battery. As
demonstrated earlier, the V-I characteristic of the solar panel is not linear. B
y operating at a fixed
voltage level, nothing guarantees that this voltage level is where the maximum a
mount of power
can be drawn. Further, the maximum power point will change due to irradiance and
temperature
guaranteeing that the PWM and basic charge controllers will rarely draw the maxi
mum amount
of power from the solar panel. The MPPT tracks this maximum power point and chan
ges the
operating point of the solar panels in order to constantly draw the maximum amou
nt of power
available. The MPPT allows for the maximum efficiency of the solar panel to be r
eached as well
as control the batteries charging requirements.
9 Distributed Power Solutions Home Page. 2003. Minneapolis, Minnesota.
<http://www.distributedpowersolutions.com/education/support.asp>
2.4 Storage Batteries
There are two types of storage batteries being used for solar power storage, aci
d or
alkaline. Alkaline batteries are made with nickel cadmium or nickel iron. The ma
in difference
between the two is nickel cadmium batteries have a faster discharge rate. Howeve
r, nickel
cadmium batteries are bad for the environment while the nickel iron does not hav
e any
environmental problems. Nickel iron batteries are slower to respond when a load
is applied and
have to be broken in before they can reach their maximum charging capacity. Both
types of
batteries will not freeze so there are no problems when operating in cold climat
es.
The most common type of battery used in solar systems is the lead-acid battery.
They are
used because they have a low initial cost and are common. Lead-acid batteries co
me in deep-
cycle, shallow cycle and car cranking. Deep cycle batteries are designed for dis
charging and
recharging over and over.10 Shallow cycle or cranking batteries are the type tha
t you use in your
automobile just to crank the engine initially. They are never discharged complet
ely. If the
battery is a shallow cycle or automotive type it will not function correctly for
solar purposes as
discharging the battery completely, which is quite common, will present problems
.
A variation from the standard lead acid battery is the gel cell battery. It is d
ifferent in the
fact that a gelling agent is added to the electrolyte to reduce movement inside
the battery.11 Many
gel batteries utilize one-way valves instead of open vents to help the normal in
ternal gas to mix
back into the water inside the battery. Gel batteries have a much higher interna
l resistance,
meaning they are unable to deliver and receive current as efficiently as a deep
cycle battery
would.12
The two main types of deep cycle batteries are sealed or flooded. A sealed batte
ry never
needs water added and doesnt need equalization charge. This type of battery can b
e mounted in
any position and are easy to transport because they wont leak or cause a chemical
spill. The
downside of this type of battery is that they need to be monitored closely for o
vercharging.
However, a flooded battery also needs close attention. The water level in a floo
ded battery needs
to be checked often and re-filled. Equalization charges also need to be performe
d which is
10 National Solar Supply Home Page. 2003 <http://www.nationalsolarsupply.com/pag
e.asp?id=18>
11 Optima Batteries Home Page. 1996-2004. Johnson Controls Inc., <http://www.opt
imabatteries.com/faq.asp>
12 Ibid.
basically a long stable overcharging method. This removes sulfation from the bat
tery plates and
restores the batterys capacity, but it can shorten the life of the battery by war
ping the plates.13
New alkaline batteries can be left unattended for long periods of time and they
can be
fully discharged without any damage done to their life (approximately 4,000 cycl
es.) If properly
taken care of, alkaline batteries will last for around 20 years in a home power
system. They can
also be reconditioned to restore them to near their original condition because t
hey utilize a
solution of lithium hydroxide, potassium hydroxide, and distilled water, which d
oes not destroy
cells. Lead acid type batteries cannot be reconditioned because the acid destroy
s the cells.14
There are reconditioned nickel-cadmium batteries on the market, which cost about
one-third the
amount of a new one. New nickel iron batteries have recently become available an
d they out
perform any other battery. They generally have a 90 percent capacity for no less
than five years,
which is better than any other battery at the current time.15
2.5 Panel System Setup
Since we have discovered that the MOSFET is not the limiting factor in setting u
p solar
panels in parallel with one MPPT circuit we can look further into the option of
each solar panel
having their own circuitry. Since solar panels are relatively expensive (upwards
of $300), it
might be a good investment to obtain an efficient circuitry for each one. This w
ill provide the
best result from each individual panel. We know that multiple panels have to be
connected in
parallel because we want to have a set voltage level with a large current level,
but there is the
option of them all being controlled and monitored by one circuit, or individual
circuits.
13 National Solar Supply Home Page. 2003 <http://www.nationalsolarsupply.com/pag
e.asp?id=18>
14 Ibid.
15 Ibid.
2.5.1 Multiple Panels per MPPT
All of the panels associated with this solar panel system configuration are all
connected
and controlled by one MPPT circuit. Figure 2-5 indicates how this configuration
would appear.
Figure 2-5: One Boost Circuit for All Panels
If the panels were in parallel with one MPPT circuit for the whole system it is
safe to say that
they would end up outputting 33A maximum.
10 panels .
3.3A =
33 A (3.3 A for 1 panel) (2.1)
The circuitry can easily be designed to handle that much power. The most importa
nt component
to find would be the MOSFET switch. A MOSFET made by International Rectifier wit
h a 35A
current rating and a voltage rating of 30V is less than $2. Two dollars is a sma
ll amount of
money for such a large current handling MOSFET switch, but the power loss associ
ated with the
MOSFET that can handle more will be larger due to the higher internal resistance
of the
MOSFET. For example International Rectifiers 35A MOSFET has an Rds value that is
0.031,
whereas a smaller MOSFET would have a typical Rds value of approximately 0.004. W
hen
this MOSFET is used for 10 panels it will have a maximum of 33.3 A. The power di
ssipated is
then realized by the following:
P =
I 2 .
R (2.2)
P =
33.32 .
0.031 =
35 W
This means that out of a maximum power of 500 W the MOSFET will dissipate 35 W,
which is
equivalent to about a 7% efficiency loss.

PRDS

.
.
(2.3)
%EfficiencyLoss
100
=
P
Total

35

%EfficiencyLoss =
*100 =
7%

.
500
The cost of implementing this configuration is relatively inexpensive due to the
need of only one
MPPT circuit in the solar panel system. However, due to the larger components in
side of the
MPPT device, the power loss associated with this configuration is quite large gr
eatly reducing
the overall efficiency of the entire solar power system.
2.5.2 Individual MPPT per Panel
Instead of utilizing one MPPT for an entire solar power system, this configurati
on installs
one MPPT for every panel in the system. Figure 2-6 indicates how this configurat
ion would
appear.
Figure 2-6: Individual Boost Controller Circuits for Each Panel
This setup will maximize output power per individual panel, rather than the enti
re
system. Utilizing this configuration allows each individual solar panel to opera
te at its own
maximum power point increasing the overall efficiency of the solar power system.
With each
circuit monitoring their own specific panel the circuit can adjust to operate at
the peak power
point for that specific panel drawing the maximum amount of power from each indi
vidual panel.
In a typical solar power system, all the panels installed in the system will be
one and the
same model. However, this does not mean that each panel functions exactly the sa
me. The
efficiency and other ratings indicated in the data sheets for these panels are t
ypical values and the
actual values for each panel will vary from panel to panel. As a result, the max
imum power
point could be located at a different point for each panel. If there were only o
ne MPPT circuit
the best output would only be an average over the entire panel layout because it
would not be
able to adjust for the differences in each panel. As a result, the multiple pane
ls per MPPT circuit
will have a larger power loss.
When using separate circuits for each panel, smaller MOSFETS can be used because
the
circuitry in the MPPT will only have to handle 3.3 amps generated from each sola
r panel rather
than 33 amps with the single MPPT configuration. The smaller MOSFETS can switch
at the
same speed as one big MOSFET can, but they dissipate less power, thus resulting
in better
efficiency. International Rectifier makes a small MOSFET with an rDS value of 0.
004, which is
much smaller than 0.031 with the larger MOSFET. Using this MOSFET with a much sm
aller
RDS value will result in much less efficiency loss in the MOSFET.
P =
I 2 .
R
P =
3.32 .
0.004 =
0.04356 W
This 0.04356 W is out of a maximum value of 50W. So when using a small MOSFET th
e power
loss is equivalent to 0.09 % efficiency loss.
2.5.3 The Best Approach
A single MPPT configuration would reduce the cost of the solar panel system if u
sed in
place of a single MPPT on each solar panel. However, the efficiency loss associa
ted with this
configuration is quite large in comparison to installing an MPPT to each solar p
anel. Solar
power systems are not widely used due to their already inefficient designs. By i
mplementing a
single MPPT circuit for the entire system, then the already low efficiency would
be reduced by
even more. The efficiency of solar power systems is more of a concern than the o
verall cost
because the cost for one of these MPPT circuits is low compared to the cost of a
single solar
panel. As a result, it is recommended that each solar panel be implemented with
its own MPPT
device.
3.0 Methodology
3.1 System Block Diagram
The basic block diagram of the system is shown in Figure 3-1.
Figure 3-1: System Block Diagram
The solar panel will feed the boost converter directly which stores the electric
al energy
temporarily in an inductor and then charges the battery. The battery then feeds
the load during
sunlight hours as well as nighttime. The boost converter is to be operated by a
digital controller.
The digital controller will be based upon a microprocessor that monitors the vol
tage and current
levels coming from the solar cell and controls the boost converter accordingly.
Finally, the
charge sensor will keep track of the charge of the battery in order to not overc
harge the battery,
which may damage some types of batteries. While not shown, all active components
such as the
digital controller will be getting its power from the solar cell.
3.2 Battery Requirements
We created a design requirement of 24VDC because many appliances directed toward
s
solar energy applications are designed for 24VDC. Other popular voltages are 12V
and 48V. In
the case 120VAC is required; inverters are common for 24VDC and can easily be pu
rchased,
however with a high price tag. We believe the biggest turn off for most buyers i
s the size of the
solar panels, along with the cost. In choosing a power rating, instead of findin
g a particular
application to suit, we figured that any system over 10 panels, would require to
much space and
require to much money compared to other options. Therefore, ten of our 50W solar
cells would
generate 500W. This would yield a maximum of 20.8A, very comparable to other con
trollers
ratings.
This 24VDC may be used to run lights for the nighttime. We estimated lights are
typically used up to 8 hours per night. During cloudy days, we dont get as much e
nergy from the
solar cells as on a clear day, therefore we need to store enough energy to provi
de the cloudier
days with energy. The table below shows how big our batteries must be in amp hou
rs, to provide
a 100W light bulb with power. Table 3.1 is calculated using the following formul
a
Power * Hours * Days
Amp Hours =
Voltage
(3.1)
Where:
Power (Watts) The expected load to be run
Hours The amount of hours to be run per day
Days The amount of days to last with no re-charging
Voltage The systems voltage 24VDC
(all units in Amp
Hours)
100W Load 200W Load 300W Load
1 Day 34 67 100
2 Days 67 134 200
3 Days 100 200 300
4 Days 134 267 400
5 Days 167 334 500
6 Days 200 400 600
7 Days 234 466 700
Table 3-1: Battery Ah Capacity vs. Load without Charging
The smallest battery we should obtain to give enough energy for 7 days using a 1
00W load such
as a light bulb is a 234 Amp-hour battery. MK has different capacity batteries a
ll the way up to
265Ah at the C/100 rate. This is equal to 2.65A discharging for 100 hours. The b
atteries we
have already obtained for this project will be suitable for our design and testi
ng needs, but the
customer should evaluate their usage and location to come up with suitable, cost
effective
storage requirements.
Controller Specifications
Voltage 24VDC
Current 20.8A
Power 10 x 50W Panels
Battery 234Ah
Scaled Down Controller Specifications
Voltage 24VDC
Current 2.1A
Power 50W
Battery 234Ah
3.3 Boost Converter Description
The boost converter is one of the most important components to the Maximum Peak
Power Tracker. To achieve maximum power from the solar panels, we must operate t
he panels
at their optimum power point. By opening or closing a switch, the output of the
solar panel will
either be shorted or open circuited. The switch discussed will actually be a MOS
FET. The digital
controller will control this MOSFET. To understand the boost converter, the MOSF
ET is
modeled with a simple ideal switch. The switch, U1, will open and close to contr
ol the voltage
level over the inductor, which will essentially set the solar panels to their op
timum power level.
The boost converter is shown in Figure 3-2 with the solar panel shown as a volta
ge source Vs.
More accurate representations of the solar panel will be used shortly.
Figure 3-2: Boost Converter Schematic
Again the VI characteristic of the solar panel is shown in Figure 3-3. The power
of the
corresponding V-I is also on the same graph with a different Y axis.
Figure 3-3: Solar Panel V-I Characteristic and Power
As the switch is closed the voltage drops as the current increases towards its m
aximum
short circuit current. If the switch is closed for a long enough period of time
the voltage will
eventually drop to zero and thus the power at this point is zero. If the switch
is open, the voltage
will rise to its open circuit voltage and no current flows out of the solar pane
l. Again the power
will be zero watts. Due to the inductors presence in the boost converter, current
and voltage
transients will not happen instantly but instead take some time. Therefore the p
ower cannot
instantly move from optimum to zero, but instead takes some time constant. By op
ening and
closing this switch at fast speeds, it is possible to pick a place such as the p
eak power point and
operate close to this point.
In order to understand the boost converter we wanted a basic representation of t
he solar
panel. Even a simple model of the solar panel is quite hard to analyze at first.
Therefore we
choose to represent the solar panel as a basic thevenin equivalent for reasons t
hat will become
more apparent in section 3.4. The V-I characteristic of an ideal thevenin equiva
lent is a linear
line with a negative slope. This is unlike the non-linear curve of the solar pan
el, which will make
a first pass understanding of the system easier. The thevenin equivalent is repr
esented with a
voltage source VTH, and a resistance, RTH. This is shown in Figure 3-4.
Figure 3-4: Boost Converter Schematic with Thevenin Equivalent Source
The thevenin voltage source was chosen to be double of the voltage at which the
solar panel
operates at its maximum power point. This is about 15V and doubling this gives a
30V voltage
source. The thevenin current was also chosen to be double of what the solar pane
l can produce at
short circuit. The short circuit current of the solar panel is about 3.3 amps, t
herefore the thevenin
current should be double this, 6 amps. To achieve 6 amps with a 30 volt source a
thevenin
resistance RTH of 5.
was chosen. The V-I characteristic of the thevenin equivalent is compared
to the V-I curve of the solar panel in Figure 3-5.
Figure 3-5: Thevenin and Solar Panel V-I Characteristics
The maximum power point is at the top right of the solar panel V-I curve. The th
evenin
equivalent is shown in Figure 3-6 with its respective power curve superimposed o
n a different
scale. Notice the power curve of the thevenin equivalent is a parabola which eac
h voltage
extreme going down to a power level of zero watts.
Figure 3-6: Thevenin V-I and Power Curve
Analysis of this circuit will contain four stages. The first stage sets up our i
nitial
conditions, when nothing is happening in the circuit yet. The second stage occur
s when we close
the switch. When the switch is closed, the current in the inductor will build up
over some period
of time and no current will flow into the second loop of the circuit. The third
stage occurs when
switch is opened. The inductor will discharge at this stage and send current to
the 24V battery
source. The fourth stage is shown what happens when we do not let the inductor t
o saturate.
That is we turn the switch on and off quick enough before the current and voltag
e go to there
extremes and the power falls to zero watts.
3.3.1 Stage One: Initial Conditions
Stage 1 is an analysis of the circuit when no voltage or current is being applie
d to the
circuit. The inductor will have a voltage level of zero with a current of zero f
lowing through it.
The voltage over the inductor is related to the current through the equation:
L dI
V =
dt (3.2)
Since there is no change in current di/dt, the voltage across the inductor is ze
ro.
3.3.2 Stage Two: Switch Closing
When the switch is closed, the loop around the battery can be ignored. Without c
urrent
being forced through the diode, the anode on the diode will always have a lower
voltage than the
24V cathode making the diode reversed bias making the right loop an open circuit
. No current
will flow through this loop as a result, so analysis of the right loop is unnece
ssary. The circuit
can now be viewed as in Figure 3-7.
Figure 3-7: Current Path While Switch is Closed
The 30V voltage source and 5.
resistor provide the circuit with 6 amps of current. This current
will flow through the inductor and charge the inductor exponentially. The curren
t flowing
through the inductor cannot jump instantaneously to 6A, much like how the voltag
e cannot
instantaneously jump with a capacitor. As a result, when the switch closes, the
current will start
at 0 amps and exponentially increase until it saturates at the 6 amp current pro
vided by the
source and resistor. This saturation is due to the fact that the voltage source
can not provide any
more than 6 amps. The speed at which the inductor goes from zero amps to saturat
ion depends
on the value of the inductance and the resistance which is discussed in more det
ail in section 3.4.
For analysis purposes, a 10mH inductor was selected. The following Figure 3-8 sh
ows the
transient curve as voltage and current flow through the inductor.
40V
20V
SEL>>
0V
Voltage
V(R1:2)
10A
5A
0A
0s 5ms 10ms
Current
I(L1)
Time
Figure 3-8: Voltage and Current through Inductor as Switch Closes
At time t=0s, the voltage is at its initial 24 volts and the current is 0 amps a
s expected. At t=0s,
the switch closes allowing current to begin flowing through the inductor. The cu
rrent will
exponentially increase until it saturates at 6 amps, which occurs at approximate
ly 6ms. When
this happens, the voltage will decrease at the same rate the current is increasi
ng due to the
voltage/current relationship of an inductor as shown above in equation (3.2). At
saturation the
voltage drops to approximately zero volts and the inductor essentially becomes a
short circuit
and will remain a short circuit until the inductor is allowed to discharge, whic
h will be described
in stage three. Therefore as the voltage goes to zero volts, no matter what the
current is at short
circuit operation the power delivered is zero.
When the switch is closed, the main function is to build the current in the indu
ctor and
drop the voltage. Essentially, the voltage and current flowing through the induc
tor will control
the operating point of the solar panel. As a result, the operating point will de
pend on the duty
cycle of our switch.
3.3.3 Stage Three: Switch Opening
Opening the switch of the circuit allows us to send the charge previously stored
in the
inductor as a magnetic field to current flowing to the battery. The switch in th
e middle is
essentially open and therefore non-existent for this simple model. Figure 3-9 sh
ows the circuit
with an open switch.
Figure 3-9: Current Path while Switch is Opened
This stage is assumed to always happen after stage two to allow the inductor to
charge
with energy. This stage allows the inductors magnetic field to collapse and dump
its current into
the battery. The diode is there to not allow the battery to dump its current int
o the inductor.
When current begins to be forced through the diode, the voltage at the anode of
the diode will
shoot up to ensure that the diode is forward biased and the battery will be char
ging. Therefore
this voltage is equal to the battery voltage plus any additional voltage it take
s to forward bias the
diode. The voltage and current flowing through the inductor is shown in Figure 3
-10.
Time
0s 5ms 10ms
I(L1)
0A
1.0A
2.0A
SEL>>
V(R1:2)
20V
25V
30V
Time
0s 5ms 10ms
I(L1)
0A
1.0A
2.0A
SEL>>
V(R1:2)
20V
25V
30V
Figure 3-10: Voltage and Current through Inductor as Switch Opens
The current in the inductor is no longer building up; rather the current is disc
harging
through the diode and into the battery to charge. As the current decreases, the
voltage will
gradually increase at the same rate due again due to the relationship of an indu
ctor given by
equation (3.1). Notice that the voltage does not decrease to zero volts but inst
ead about 25V.
Once this inductors field is fully collapsed the voltage at the diode will be ess
entially the 30V
source in series with its 5.
resistor which provides the diode and 24V battery. The voltage at
this point is about equal to the 24V battery plus the forward voltage of the dio
de, which is about
0.7V.
3.3.4 Stage Four: On and off switching
This stage will use the entire thevenin equivalent circuit shown again in Figure
3-11.
Figure 3-11: Boost Converter Schematic with Thevenin Equivalent Source
The idea of this stage is to simulate the boost converter during full operation.
In order to
control the power point the solar panel operates at the switch will turn on and
off fast enough so
that the saturation values of the inductor are never reached. At the beginning o
f the exponential
curve, it is can be shown to be pretty linear. This concept will be made to grea
t use in our
analysis of this circuit. By adjusting the time the signal is high compared to l
ow or the duty cycle
of the pulse, it is possible to control where on the VI power curve the solar pa
nel is operated.
This duty cycle is easily adjusted with a PWM signal from our digital controller
. First we will
show how the above exponential switching can become linear at fast speeds. This
was done in
our simulation in Pspice by a time controlled switch.
For this simulation we guessed a switching speed of 1 kHz. This speed was guaran
teed
not to saturate. The voltage and current waveform is shown in Figure 3-12.
13.75V
12.50V
11.25V
SEL>>
V(R2:2)
4.0A
3.5A
3.0A
30ms 31ms 32ms 33ms 34ms
I(L1)
Time
Figure 3-12: Voltage and Current through Inductor (Switching)
Note the linearization of the voltage and current at the solar panel. We can see
at 30mS
the voltage seems to be decaying and the current charging. Therefore the switch
was closed at
this point and the inductors field was charging. At 30.5mS the switch is opened a
nd the current
starts to flow out of the inductor and charge into the battery. Notice the curre
nt value does not go
below 3.3A, unlike above when we let the inductors field collapse fully. The line
appears to be
perfectly linear, but in reality it is really just the very beginning of its exp
onential decay. As long
as we switch every 0.5mS, the current and voltage will never saturate as shown b
efore in our
single switching case.
As mentioned before, the duty cycle directly controls the voltage, current and p
ower at
which the solar panel operates. By varying the duty cycle of the voltage-control
led switch in
Pspice it is possible to graph the power. We then see exactly the same power par
abola curve as
expected in Figure 3-13.
Powe r Characte ristic of VI The v e nin
Equiv ale nt
0
10
20
30
40
50
0 50 100
Duty Cycle (%)
Power
(
Watts)
10m H
Powe r Characte ristic of VI The v e nin
Equiv ale nt
0
10
20
30
40
50
0 50 100
Duty Cycle (%)
Power
(
Watts)
10m H
Figure 3-13: Power Characteristic of VI Thevenin Equivalent
3.4 Boost Converter System Equations
To achieve the maximum power from a source the load resistance needs to be equiv
alent
to the internal resistance of the source. Figure 3-14 contains a simple source c
onsisting of Vs1
and the internal resistance of the source R1 with a load resistance of RLOAD. RL
OAD is the
resistance of the load being applied to the voltage source.
+
-
Vs1
Rload
R1
Figure 3-14: Basic Voltage-Resistor Source with Load
In order for the power source Vs1 to transfer maximum power into RLOAD, RLOAD mu
st be equal
to R1. Instead of a constant voltage source as a source, we are using a solar ce
ll. The solar cell is
not an ideal voltage or current source and therefore is modeled with a more comp
lex circuit. The
load is then our boost converter as shown in Figure 3-15.
Figure 3-15: Basic Voltage-Resistor Source related to MPPT
3.4.1 Thevenin Equivalent
Designing the controller system for the Maximum Peak Power Tracker requires a fu
ll
understanding of what is going on in the boost converter circuit. Deriving equat
ions for the
average current, IAVG, the average voltage, VAVG, the equivalent resistance, REQ
, the ripple
current, I, and the power, P, will allow us to predict the outcome of our circui
t. These equations
will also help determine the appropriate duty cycle to operate the switch at in
order to achieve
the maximum power point. The circuit in Figure 3-16 was used to analyze the circ
uit.
Figure 3-16: Nonlinear Model of Solar Panel and Boost Converter Circuit
Notice the few minor differences in this circuit than previous ones used. The so
lar panel
is being modeled as a linear thevenin voltage and resistance. The switching of o
ur circuit will
operate near the maximum power point of the nonlinear V-I characteristic of the
solar panel.
Since this is the case, we can design a linear solar panel model so the maximum
power point for
the linear model and the nonlinear model are almost one in the same. This can be
seen in Figure
3-17.
Figure 3-17: Solar Panel Linear and Nonlinear V-I Characteristics
As you can see from Figure 3-17, the maximum power points of the two curves are
almost perfectly aligned. To determine the correct thevenin voltage and resistan
ce, you simply
double the voltage at the maximum power point for the nonlinear model, because t
he maximum
power point for a linear model will occur at the midpoint and the thevenin resis
tance will simply
be the voltage over the current at the maximum power point. As a result, the the
venin voltage
will be 30 volts and the thevenin resistance will be 5. The use of the thevenin e
quivalent
source will greatly simplify the derivation of the boost converter system equati
ons and should
yield the same results as if an expression for the solar panel were used simply
because the
maximum power points occurring in the same spot.
3.4.2 Average Current
Since the diode acts much like a switch, a switch can be used to replace the dio
de in
Figure 3-16. This switch will close when the main switch, U1, is opened and vice
versa. At any
given point, the voltage from the solar panel will be lower than the voltage of
the battery. As a
result, the current will want to reverse direction and the exponential decay of
the current will act
as if it was saturating at a negative value. This can be seen in Figure 3-18.
Figure 3-18: Current Flowing from the Solar Panel
The diode in the boost converter will prevent the current from going negative at
any point
in time, but the exponential curves for the current will act as if it were going
to. In Figure 3-18,
if the current was allowed to reach its saturation points, then it would reach a
maximum current,
IMAX, and exponentially decrease until it reached a maximum negative current, IN
EG. The
maximum current will only be achieved when current is building in the circuit. T
his means the
switch, U1, will be closed, and the switch replacing the diode will be open. The
simplified
circuit is shown in Figure 3-19.
39
Figure 3-19: Simplified Boost Converter Circuit (U1 is closed, U2 is open)
With a steady state current of IMAX flowing through the inductor, the inductor w
ill act like
a short circuit and will be insignificant in determining the maximum current. Th
e only
remaining components are the thevenin voltage and resistance. As a result, the m
aximum current
is simply:
Vth
I =
(3.3)
max R
th
With a thevenin voltage of 30 volts and a thevenin resistance of 5, the maximum p
ositive
current flowing will be 6 amps.
To determine the maximum negative current flowing through the circuit, the switc
h, U1,
will be open while the switch replacing the diode will close. The simplified cir
cuit is shown in
Figure 3-20.
Figure 3-20: Simplified Boost Converter Circuit (U1 is open, U2 is closed)
Once again, the inductor acts as if it were a short circuit due to the current b
eing in steady
state. The only components now left in the circuit are the thevenin voltage, the
venin resistance,
and battery voltage. The negative current is determined to be:
V -V
TH BATT
I NEG =
(3.4)
RTH
A thevenin voltage of 30 volts, a thevenin resistance of 5, and a battery voltage
of 24 volts will
yield a maximum negative current of 1.2 amps. The actual ripple current will rem
ain somewhere
between zero amps to the maximum current, IMAX. The duty cycle and frequency wil
l control the
location and ripple size of the current. When the duty cycle is high, the curren
t will try to reach
the maximum current, IMAX, and the current will try to reach the maximum negativ
e current,
INEG, when the duty cycle is low. The general expression for an exponentially in
creasing or
decreasing current is:
-ttI (
)
t =
I F -
(I F -
Ii )e (3.5)
Where I(t) is the value the current reaches after a certain length in time, IF i
s the current that will
be reached, Ii is the starting point, t is the time period, and .
is the time constant L/R. When the
duty cycle is turned to high, the initial current is I2 and will increase until
the duty cycle goes
low, which will occur at I1. The curve will act as if it were increasing to its
saturation value of
IMAX, so IF will be equivalent to IMAX when the duty cycle is high. The time, t,
is equivalent to
the portion of the time period in which the duty cycle is high, DT0, where D is
the duty cycle and
T0 is the time period. The resulting expression is:
I (
)
t =
I MAX -
(I -
I )e
-t
(3.6)
MAX 2
Using the Taylor series and knowing that T0 will be much less than.
, equation (3.6) simplifies
to:

DT 0

DT 0
I1 =
IMAX .

+
I2 1-

(3.7)

.
.

.
.
The only two unknowns in equation (3.7) are I1 and I2 while the remaining variab
les are set
values. To solve for I1 and I2, a second expression with these two variables wil
l be needed.
When the duty cycle goes low, the initial current will be at I1 and will drop do
wn to I2 before the
duty cycle turns high. The exponential drop will look like it is decreasing to t
he maximum
negative value, INEG, and the amount of time, t, is the portion of the time in w
hich the duty cycle
is low, (1-D)T0. The resulting expression is:
()
=
(I -
e
-t
IT I -
I )
t(3.8)
NEG NEG 1
Simplifying this expression and using the Taylor series, equation (3.8) simplifi
es to:

(1-
D)T0

(1-
D)T0
I2 =
I NEG
+
I1 1-
(3.9)

.
/
.
/
We now have two equations and two unknowns. This allows us to solve for the maxi
mum and
minimum ripple values, I1 and I2 as a function of duty cycle, time period, satur
ation currents, and
.
. In order to determine the average current and ripple current expected in simul
ation, an
expression for I1 and I2 independent of one another needs to be derived. Inserti
ng equation (3.9)
into equation (3.7) will give us an expression for I1 independent of I2. The res
ulting expression
is:
DT
(1-
D)T
(1-
D)T
DT
0 0 O 0
I1 =
I MAX +

I NEG +
I1 1-
1-

(3.10)

t.
.
/

.

As you can see from equation (3.10), I1 is the only remaining unknown variable i
n the equation.
Solving for I1 and simplifying the expression yields the resulting equation:
DT 0 (1-
D)T0
DT 0
I +
I 1-

MAX NEG
.
.

.

I1 =
(3.11)

DT 0
(1-
D)T0
1-
1-

1-

.
.
.
/
In order to solve for I2, inserting equation (3.7) into equation (3.9) gives us
the following
equation:
(1-
D)T0
DT 0
DT 0
(1-
D)T0
I2 =
I NEG +
I MAX +
I2 1-

1-
(3.12)
.
.

.

.
/
As shown in equation (3.12), I2 is now completely independent of I1. Solving for
I2 and
simplifying the equation yields the following expression for I2:
(1-
D)T DT
(1-
D)T
00 0
I NEG +
I MAX
1-

.
t.
I2 =
(3.13)

DT 0
(1-
D)T0
1-
1-

1-

.
.
.
/
Now that an expression for I1 and I2 have been derived completely independent of
one another.
IAVG is one of the more important values that need to be derived. Not only does
it confirm that a
simulation of our model is correct, but will later yield an expression for the p
ower. The average
between any two points is simply half the sum. The average current will then dep
end on half the
sum of the maximum and minimum ripple values:
I +
I
=
1 2 (3.14)
I AVG
2
Inserting equation (3.11) and equation (3.13) into equation (3.14) will yield th
e following
equation:
DT 0
(1-
D)T0
(1-
D)T0
DT 0
I MAX
2 -

+
I NEG
2 -

.
.
/
.
.
I AVG =
(3.15)
T0
T0
2 1-
D(1-
D)

.
.
/
Note how the average current is dependant on known values. In order to simplify
equation
(3.15), knowing that T0 will be much less than.
, any term in equation (3.15) that will not
significantly alter the result will be approximately equal to zero. The simplifi
ed equation for the
average current is:
I =
I D +
I (1-
D)
(3.16)
AVG MAX NEG
When the duty cycle is at 100 percent, the average current will become the maxim
um positive
saturation value and when the duty cycle is at 0 percent, the average current wi
ll become the
maximum negative saturation value. This makes sense because if the main switch,
U1, is always
closed, then the current will build to its maximum current and if U1 is always o
pen then the
current will drop to the minimal amount of current.
3.4.3 Current Ripple
Another useful expression to derive is DI . DI will allow us to determine an app
ropriate
inductor value for our circuit. The ripple current will be important because it
affects the
precision of the average current and a smaller ripple will require a higher indu
ctor value. The
change in current, or DI , is simply the final value minus the initial value:
DI =
I1 -
I2 (3.17)
Plugging in the equations (3.11) and (3.13) into equation (3.17) will give us an
expression for
DI .
I D(1-
D)T0 -
I D(1-
D)T0
MAX NEG
DI =
(3.18)
T0
1-
D(1-
D)
Once again the equation for DI is very messy and can be cleaned up some. Using t
he same
assumption in determining the final equation for the average current, T0/
DI is very messy and can be cleaned up some. Using the same
assumption in determining the final equation for the average current, T0/.
is set to be
approximately equal to zero since T0 is much smaller than .
. However, there is an addition
T0/.
in the numerator that cannot be set to zero. The reason is that if set to zero,
then DI will be
equal to zero. As a result, the additional T0/.
cannot be set to zero in this simplification. The
final expression for DI is:

D(1-
D)T0
DI =
(I MAX -
I NEG )
(3.19)
.
/
As you can see from equation (3.19), by making the approximation that T0/.
will be
approximately equal to zero, simplifies the equation to an expression that will
simply describe
the amount the current will ripple through the inductor of the boost converter.
3.4.4 Voltage Equations
The next step is determining an expression that will allow an accurate predictio
n of the
average voltage. The voltage will move in the opposite direction the current mov
es at the same
rate. Figure 3-21 demonstrates how the average voltage will act along with a hig
h and low duty
cycle.
Figure 3-21: Voltage at Solar Cell
When the main switch, U1, is left closed for a while, the simplified circuit wil
l once
again look like Figure 3-19. The current will gradually build through the induct
or, decreasing
the voltage drop exponentially at the same rate the current is increasing. When
the current
increases, the voltage decreases due to the inductor. Performing a KVL around th
e loop will
give us the most negative value for average voltage, VNEG.
V =
V -
I R =
0 (3.20)
NEG TH MAX TH
The negative most value the average voltage can reach is zero volts. This makes
sense because
in the circuit from Figure 3-18, the current will build to its maximum value, wh
ich depends only
on the thevenin voltage and resistance. So for this to be true, the voltage must
be zero. The
maximum average voltage that can be achieved will occur when the main switch, U1
, is open.
The simplified circuit will look the same as Figure 3-20. For the maximum voltag
e to occur, the
average current must be at a value of zero amps. When this happens, the average
voltage will
simply be equivalent to the battery voltage.
V =
V (3.21)
MAX BATT
After going through the average current, the voltage is really easy to figure ou
t. Instead of going
through all of the math as was performed with the average current, it is much ea
sier to realize
that the voltage will decrease at the same rate as the current will decrease but
to different
saturation points. As a result, the equation for the average voltage will be muc
h similar to the
equation for average current. The only major difference is that when the current
reaches its
maximum value, the voltage reaches its minimum value and when the current reache
s its
minimum value, the voltage reaches its maximum value. As a result, INEG becomes
VMAX and
IMAX become VNEG in the derived average current equation. This yields the follow
ing simplified
expression for average voltage.
VAVG =
VMAX (1-
D)
(3.22)
Since VNEG is equivalent to zero volts, the average voltage equation is extremel
y simplified
compared to the average current equation.
The rippling voltage, V, is derived using the same method as finding VAVG. This r
esults
in the following expression for V.
DR TH VMAX (1-
D)
DV =
(3.23)
Lf
3.4.5 Equivalent Resistance and Power Equations
Now that an expression for the average voltage and current are obtained, it is e
xtremely
simple to derive expressions for the equivalent resistance of the circuit and th
e power. The
equivalent resistance is defined to be:
VAVG
REQ =
(3.24)
I AVG
Plugging in the equations for average voltage, equation (3.22), and average curr
ent, equation
(3.16), into equation (3.24) will give us an expression for the equivalent resis
tance.
VMAX (1-
D)
REQ =
(3.25)
I D +
I (1-
D)
MAX NEG
The predicted average power will also be a function of average current and volta
ge.
P =
I V (3.26)
AVG AVG AVG
Plugging equations (3.16) and (3.22) into equation (3.26) will yield an expressi
on for the
predicted average power.
2
PAVG =
I NEG VMAX (1-
D)
+
D(1-
D)(I MAX VMAX )
(3.27)
3.4.6 Equation Accuracy
Deriving expressions for VAVG, IAVG, REQ, DI , and Power give us a lot of unders
tanding
in how to design the controller circuit of the Maximum Peak Power Tracker. Howev
er, in order
to have complete faith in these equations, a comparative analysis of the compute
d average values
should be compared with the simulated values from the Boost Converter Descriptio
n section
using different duty cycles. The circuit used in simulation is the same as Figur
e 3-16. The two
switches are controlled by a Pulse Width Modulation (PWM) voltage source. When t
he PWM
voltage source sends a high signal, the switch, U1, will close while the switch,
U2 will open and
vice versa. Using this voltage source will allow us to change the duty cycle and
period of the
switching quite easily. A basic inductor value of 10mH was chosen to perform the
analysis. The
thevenin voltage and resistance is 30 volts and 5, and the battery voltage is 24
volts. Since a
linear model is being used, the thevenin resistance is dominant to all of the ot
her forms of
resistances in the circuit and is the only resistance used in evaluating the ter
m .
. The following
four figures compares the calculated or predicted values for VAVG, IAVG, DI , an
d PAVG over a
range of different duty cycles.
DI , and PAVG over a
range of different duty cycles.
Figure 3-22: Average Current vs. DC Figure 3-23: Change in Current vs. DC
Figure 3-24: Average Power vs. DC Figure 3-25: Average Voltage vs. DC
As you can see from the figures above, the computed values are extremely close t
o the simulated
values to the point where hardly any deviation is noticeable. As a result, the e
quations derived in
this section are extremely accurate and can be considered a very reliable method
to predict the
results.
3.5 Current Sensing Methods
The digital controller requires voltage and current feedback from the solar cell
in order to
optimally control the peak power level of the solar panel. The voltage is easy t
o interface to the
microprocessor by direct connection. A resistor divider may be needed to limit t
he voltage seen
by the microprocessor. Current is also common to measure, however most current s
ensing
techniques come with a loss. Two general types of current sensing include resist
ive and magnetic
sensing. Resistive current sensing is done by inserting some type of resistance
into the circuit and
measuring the voltage across this resistor. This resistor of course dissipates p
ower in the form of
an efficiency loss to our circuit. Magnetic sensing measures the magnetic field
around a wire or
loop that the current passes through. This technique is usually common in AC cur
rent or very
high current applications.
The easiest and most common way to measure current is a simple sense resistor. A
sense
resistor is basically a resistor placed in series with the load. Ohms law says th
e voltage drop
across the resistor is proportional to the current. When low current flows throu
gh the sense
resistor it can provide very accurate measurements if the resistance value has a
small tolerance.
Sense resistors are commonly made as low as 0.001.
at +/-1% tolerance. Even though sense
resistors can have high performance thermal packaging for larger current values,
they still result
in some insertion loss. Their measurement is also not isolated from transient vo
ltage spikes. The
power dissipated in the resistor is given by the equation
P =
I 2 R (3.28)
The lower the value of R, the lower the power loss will be. Therefore it is nece
ssary to pick the
lowest value of R as possible. Where I is the max current from the solar panel =
3.28 A.
P =
3.28 2 * 0.005 =
58 mW (3.29)
A 0.005.
resistor costs $0.45 and will use 53.8mW.
Another type of sensor is a coil in which a wire passes through the middle of th
e
windings. The magnetic field generated from the current in the wire induces a ma
gnetic field in
the coil as the current changes. This is therefore only useful to measure AC RMS
current. If there
is any bias in the current, this type of sensor will not pick it up. Our current
will be oscillating;
however there will also be a large bias making this kind of sensor inappropriate
for our
application.
Another possibility is to measure the current over the rDS of the MOSFET. Slight

variances of rDS values between different production batches of MOSFETs can be t
roublesome
perhaps not now, but if the board is manufactured on a wide scale. The rDS value
can also vary
slightly with the gate voltage being applied. Different temperature coefficients
can also vary this
resistance value and is not always given in datasheets. These variances can vary
up to 100%.16
A Hall Effect sensor next to a trace or a wire and determine the magnetic field
generated
from that wire or trace even with a DC current. Although the Hall Effect sensor
can measure
current without losing any power from the signal, the Hall Effect sensor may use
power from a
different source to amplify its signal. In our application, all the power is com
ing from the solar
panel; therefore any power the sensor used would be a loss in our efficiency. An
other problem
with Hall Effect sensors is that they are usually designed for large current mea
surements. Most
sensors are designed for current of 50A and more, therefore questioning its accur
acy at very low
currents. As an example, Allegro Micros smallest current sensing Hall Effect sens
ors used 710mA
just to turn on, which is almost 50mW, the same as the sensor resistor. This sen
sors are
also much more expensive than sensing resistors.
The last option for measuring the current flowing from the solar panel is induct
or current
sensing. Inductor current sensing is an inaccurate way of measuring the current.
However, the
output of the inductor current sensor is proportional to the current and the pow
er loss is
insignificant, making the inductor sensor an ideal method for this application.
3.5.1 Inductor Current Sensing
An interesting article was found that used the inductors internal resistance alre
ady in the
circuit to find the current passing through it. The idea originates from a buck
converter, and due
to the extremely small power loss expected from this approach, adapting the idea
to the boost
converter seems feasible.
The current through the inductor will be a linear triangle wave with some small
RMS
value and at some DC average. As the current is building up in the inductor the
voltage will be
falling. Therefore the voltage and current will be 180 out of phase in steady st
ate. By analyzing
the voltage across the inductor, it is possible to get the average current throu
gh the inductor. This
16 Current Sensing Techniques for DC-DC Converters <http://users.ece.gatech.edu/
rinconmora/
publicat/journals/mwscas02/isense.pdf>
is due to ohms law, which states that voltage is proportional to the current by
some resistance.
The resistance in this case is the internal resistance of the inductor. By apply
ing a low pass filter
across the inductor it is possible to filter out all or close to all of the high
frequencies leaving
only the DC part of the signal left and perhaps some very low frequencies. The m
odel of the
inductor has an internal resistance RL. The low pass filter is then applied over
the inductor as
shown in Figure 3-26.
Rf
Cf
L
RL
Figure 3-26: Inductor Current Sensing Schematic
Analysis of this circuit requires the use of two simple equations.
VL =
I (sL +
RL )
(3.30)
V
L (3.31)
VOUT =
1+sR F CF
Combine the two together to get the relationship between the output sense voltag
e, VL, to the
current flowing through the inductor, I.
V
1 +
S(L / R )
OUT L
R (3.32)
=
L

i 1+S .
R C
F F /
The inductor discussed here will be assumed to have a 1mH inductance with an int
ernal
resistance of 0.01W. There are three conditions that can take place by selecting
the appropriate
filter components.
1.) RFCF = L/RL
2.) RFCF > L/RL
3.) RFCF < L/RL
L
To set condition one true: set =
R C then the part in brackets [] goes to 1.
R FF
L
i 1+S .
RF CF /
VOUT
1 /L+
S( RL )
=
RL

(3.33)
VOUT
=
RL (3.34)
i
Therefore the voltage gain per ampere across all frequencies is set by the inter
nal resistance RL.
Here the voltage gain is steady independent of frequency. The inductor internal
resistance is
equal to RL, in this case 0.01W. The gain VOUT/i is equal to 0.01 or 40dB.
RFCF = L/RL
With the inductor discussed above L/RL= 0.001/0.01 = 0.1. Therefore by picking a
RFCF
value of 0.1 will allow analysis of the first condition. By picking a random RF
value of 1kW, CF
is calculated to be 100mF.
L 1mH L/RL 0.1
RL 0.01.
RF 1k.
RFCF 0.1
CF 100mF
Table 3-2: Component Values when RFCF = L/RL
Figure 3-27: Bode Plot when RFCF = L / RL
Notice the gain is the same throughout all frequencies. The phase is also zero d
egrees
across all frequencies. Therefore there will be no phase shift between the curre
nt and sensed
voltage.
The capacitor starts to act like a closed circuit at high frequencies and an ope
n circuit at
DC. Therefore at high frequencies the circuit will begin to dissipate power thro
ugh the resistor,
eventually dissipating V/R. The wave on top on the waveform below shows the powe
r dissipated
through the filter and the current going through the filter.
RFCF > L/RL
The second condition is met when RFCF is selected to be greater than L/RL. RFCF
is
shown below to be 10 times larger than L/RL by increasing the resistance from 1k
.
to 10k.
and
keeping CF at 100mF.
L 1mH L/RL 0.1
RL 0.01.
RF 10k.
RFCF 1
CF 100mF
Table 3-3: Component Value when RFCF > L/RL
Figure 3-28: Bode Plot when RFCF > L/RL
By increasing RFCF the transfer function takes the shape of a low pass filter. I
ncreasing
RFCF, lowers the frequency at which a pole is located thus decreasing the breakp
oint frequency.
This frequency response has the least attenuation at DC frequencies and greater
attenuation
occurs as the frequency is increased. The RC filter in this application wants to
block all high
frequencies and only read the average current which corresponds to the DC voltag
e. The higher
the order of the filter, the more attenuated higher frequencies are. This type o
f configuration is
the type that will be used to sense the current, as it gives the average voltage
level which is
proportional to the current through the inductor.
The breakpoint frequency of this transfer function also has the maximum phase sh
ift. The
point at which the magnitude drops 3dB, the phase angle is 45. Therefore the voltag
e sensing
will lag the current. Because of this, there will be a delay in our reading of t
he current and the
actual value at the current time. Depending on our switching frequency, this may
or may not be a
problem.
RFCF < L/RL
The third and final case is where RFCF is less than L/RL. In this example, RF is
decreased
from the original 1k.
to 100.
and CF is left at 100mF. The frequency response of this condition
is shown below.
L 1mH L/RL 0.1
RL 0.01.
RF 100.
RFCF 0.01
CF 100mF
Table 3-4: Component Values when 8 RFCF < L/RL
Figure 3-29: Bode Plot when RFCF < L/RL
Here the attenuation is greatest at DC frequencies and least at high frequencies
. Because
the circuit is measuring the average current through the inductor, the filter sh
ould have the least
attenuation at DC frequencies. Therefore RFCF should never go below L/RL as DC f
requencies
will start to be attenuated.
By increasing the RF resistor and decreasing the CF value by the same proportion
, the
filter achieves even less power dissipation and allows the RFCF value to stay th
e same, and
leaving the pole unchanged. Here it is shown the RF increased by a factor of 10
and CF decreased
by a factor of 10. It is evident that the power dissipated through the filter is
reduced by a factor
of 10. This is shown as the lower line.
Figure 3-30: Bode Plot Comparison as RFCF is reduced By a Factor of 10
3.5.2 Current Sensing Conclusion
Magnetic sensing techniques will not work in the current sensing application due
to the
small currents that need to be sensed and the fact that the current is AC; leavi
ng only resistive
sensing techniques. By utilizing the resistive components already found in the b
oost converter
circuit, the MOSFET and/or the inductor, the voltage over these components can b
e sensed and
treated much like a current sense resistor while losing no additional efficiency
. Unfortunately
these resistive components have a high tolerance. These tolerances will vary mos
tly with
temperature. However, current accuracy is not an issue as long as the voltage ou
tput from the
current sensor is proportional to the current.
Below a table is shown comparing the different methods described above. The accu
racy
was calculated based on the components tolerances. Each components accuracy is ca
lculated in
Table 3.5.
Value Accuracy Additional
Power (@3.3A)
Additional
Cost
Current Sense Resistor 0.01.
3% 16.mW $0.10
Current Sense Resistor High
Precision
0.005.
3% 33mW $0.42
MOSFET Rds -49% 0mW $0.00
Inductor Sensing -42% 1.5mW* $0.15
Hall Effect --50mW @5V $10.00
Table 3-5: Comparison of Current Sensing Methods
PCB Trace Resistance:
Typical thickness tolerance +/-0.l mil of a 1.3mil trace
Coppers temp tolerance = 0.1/1.3mil = 0.12
Tolerance = 13%
MOSFET rDS:
Initial rDS tolerance = 1.10
Temperature Tolerance reference to 25C= 1.004DT = 1.004(100-25) = 1.35
Tolerance = 1.10 * 1.35 = 49%
Inductor Sensing:
Initial Inductance Tolerance = 1.05
Temperature Tolerance Reference to 25C = 1.35
Tolerance = 1.05 * 1.35 = 42%
* 1.5mW is using a 100k.
and 1mF
3.6 Solar Cell Simulation Results
To model the solar cell in PSpice, we inserted our simple solar cell model into
the
simulation we used in the last chapter. Instead of using the thevenin equivalent
in the simulation,
we used the solar panel model. While our system equations are only valid for the
thevenin
equivalent it still shows how one variable reacts to another and is therefore st
ill quite useful.
Figure 3-31: Solar Cell/Boost Converter Simulation Circuit
We again adjusted the duty cycle of the switch U1 and measured values of the vol
tage,
current and power from the solar model. This presented us with a very useful gra
ph of duty cycle
verse the equivalent power from the solar cell. This is extremely useful to the
controls aspect of
the project. We can either derive this equation or simply fit a curve to the dat
a to arrive at a
transfer function for the plant in the control circuit. Our data is shown below:

Duty Cycle Power IAVG VAVG
10 0.54 0.032 17.55
20 2.13 0.122 17.53
25 3.29 0.188 17.52
30 11.01 0.636 17.44
35 47.92 2.94 16.3
40 45.4 3.04 15.2
50 39.2 3.1 12.52
60 31.4 3.18 10
70 19.65 3.22 6.29
75 15.75 3.25 5.02
80 12.4 3.27 3.87
90 10 3.29 3.06
Table 3-6: Simulated Results of Duty Cycle vs. Power, IAVG and VAVG
Solar Cell Power vs Duty Cycle
0
10
20
30
40
50
60
0 20 40 60 80 100
Duty Cycle (%)
Power
(W)
Solar Cell Power vs Duty Cycle
0
10
20
30
40
50
60
0 20 40 60 80 100
Duty Cycle (%)
Power
(W)
Figure 3-32: Solar Cell Power vs. Duty Cycle
Here you can see the non-linear curve of the delivered power from the solar cell
verse the
duty cycle. By finding a close fit transfer function of this waveform we can use
basic control
theory to control the duty cycle. However, not knowing how close our solar panel
model is to the
actual cell, this curves variance can be quite large. Our next step in the projec
t is to design,
implement, and test different control methods.
4.0 Implementation
4.1 Parts Selection
4.1.1 MOSFET Selection
Selecting a particular MOSFET for our design requires a power loss analysis in o
rder to
achieve a minimal power loss. There are three main power losses associated with
the MOSFET.
The first is the power loss due to the current flowing through the small interna
l resistance of the
MOSFET when the switch is closed. The second is the power lost due to the intern
al capacitance
at the gate of the MOSFET. The third is due to the rise and fall times of the sw
itch. Five
comparable MOSFETS with relatively low on resistance (rDS) and low gate to sourc
e charge
(QGS) were selected. The five MOSFETS are listed in Table 4.1.
MOSFET rDS
(m)
QGS
(nF)
Rise time
(ns)
Fall time
(ns)
IRL7833 4.50 32.0 50.0 6.90
IRLU7807 18.2 7.00 50.0 50.0
FDP6030L 17.0 13.0 12.0 12.0
FDP6030BL 18.0 12.00 11.0 8.00
IRL3713 4.00 75.0 160.0 57.0
Table 4-1: Parameters for five comparable MOSFETS
The lower the values for rDS and QGS, the lower the total power loss will be. Ho
wever, each
MOSFET has a tradeoff making it impossible to simply look at the parameters and
make a
selection. The QGS might have a larger impact on the power loss than the on resi
stance, rDS. A
thorough power loss analysis is required in order to determine which MOSFET will
give us the
least power loss as a result of switching speed and on resistance.
The power lost through the internal resistance of the MOSFET, rDS, will be const
ant with
a varying frequency. Power is only lost through a resistance when there is a cur
rent flow and is
determined by the relationship below:
Pr =
I 2 rDS (4.1)
DS
As you can see, the power loss through the on resistance of the MOSFET has no de
pendence on
frequency and will remain constant regardless of what the switching speed turns
out to be. The
MOSFET IRL3713 has the lowest rDS value and will have the lowest power loss out
of the five
MOSFETS when just looking at the power lost through rDS, but its QGS value is re
latively high
and the rise and fall time of the MOSFET could also bring the power loss up subs
tantially.
Depending on the impact of the power lost due to switching speed, the IRL3713 MO
SFET may
not be the most power efficient choice.
In order to close a MOSFET switch, a charge at the gate to source of the MOSFET
builds
up to allow current to flow from the drain to source. The charge required to bui
ld up before the
switch is closed depends on the QGS parameter of the MOSFET. Obviously, a lower
QGS value
will allow the switch to close with a smaller charge. This charge is stored in a
capacitor
connected from the gate to the source channel of the MOSFET. As soon as a charge
of QGS is
obtained in the capacitor, the MOSFET switch will close allowing current to flow
. The second
the switch is opened, all of the charge stored in the capacitor is lost. This me
ans that any charge
built up in the capacitor is lost resulting in some power loss. As the switch is
opened and closed
more frequently, meaning a higher frequency, the power lost will increase. A gen
eral expression
that describes the power lost due to the switching speed is described below:
PCGS =
QV f (4.2)
GS GS
Where VGS is 5 volts and is equivalent for each MOSFET. The only variable that i
s independent
for each MOSFET is QGS and is specified in the data sheet of each MOSFET. As you
can see,
the power lost due to switching does increase with frequency. The actual impact
of this power
loss can be seen in Figure 4-1.
Figure 4-1: Power Loss due to Gate Capacitance as a Function of Frequency
In Figure 4-1, the MOSFET IRLU7807 has the least power loss due to the gate char
ge, but has a
higher on resistance indicating that it loses more power from the current flowin
g through the
MOSFET than other MOSFETS. The gate charge does not show any significant differe
nce
between the MOSFET under 10 kHz and can be completely ignored below this frequen
cy.
Beyond this frequency, the gate charge losses gradually make a larger impact as
the frequency
rises. Since our design will most likely require a faster frequency than 10 kHz,
these losses
cannot be ignored.
The final power loss factor through the MOSFET will result due to the rise and f
all of the
current through the MOSFET as it switches on and off. Once the MOSFET is closed,
current
will be allowed to flow and the voltage drop over the MOSFET will be go to zero
resulting in no
power loss. Once the switch is open, the Voltage drop over the MOSFET will incre
ase to
approximately twenty-five volts, but the current will reduce to zero, again resu
lting in no power
loss. However, MOSFETS cannot switch instantaneously and each MOSFET has its own
unique
rise and fall time. While the current rises and falls accordingly, the voltage a
nd current are not
zero. As a result, there is a power loss associated with the switching of the MO
SFET. This
scenario can be visualized in Figure 4-2.
Figure 4-2: Current and Voltage Rise and Fall Power Loss
The voltage and current are assumed to rise and fall right after the other to av
oid calculating the
power loss from a parabola. Instead of a parabola, the power can be calculated i
n the resulting
triangle using simple geometry.
P fall rise -
bh
2
1 =
(4.3)
The base of the triangle is simply the sum of the rise and fall times of the MOS
FET. The height
is determined by multiplying the voltage and current together and the peak of th
e triangle occurs
when both the current and voltage through the MOSFET are at their maximum points
. The unit
for the equation above is in Watt-seconds. The actual power lost through the MOS
FET will also
depend on the frequency. Obviously, as the frequency increases, the switch opens
and closes
more often creating a higher power loss. Multiplying the above equation by the f
requency gives
you the power loss in Watts. The resulting equation is:
1
P =
(t +
t )V .
I .
f (4.4)
rise -
fall rise fall DS
2
Where VDS is 24 volts and I is 3.3 amps and both variables remain constant for a
ll of the
different MOSFETS. The only difference between the MOSFETS is the rise and fall
times. The
significance of this power loss is shown in Figure 4-3.
Figure 4-3: MOSFET Power Loss due to Rise and Fall times
In Figure 4-3, the increasing frequency has the same effect on the power loss du
e to the
switching speed as it did on the gate charge of the MOSFET. However, including b
oth power
losses together will cause the exponential increase in power loss with increasin
g frequency to
grow faster making smaller frequencies more practical for application.
To find the most efficient MOSFET out of the group, the power losses due to swit
ching
speed, internal resistance, and rise and fall times must be combined into one fi
gure. Summing
the internal MOSFET resistance, the gate to source capacitance, and the rise and
fall times gives
the total power loss due to the MOSFET.
P =
P +
P +
P (4.5)
MOS rDS CGS rise -
fall
(t +
t )V If
2 rise fall DS
P =
I r +
QV f +
(4.6)
MOS DS GS GS
2
The figure demonstrating the MOSFET power loss as a function of frequency using
equation 4.6
is shown in Figure 4-4.
Figure 4-4: Total Power Loss versus Frequency
Figure 4-4 provides enough information to select the most efficient MOSFET. The
higher the
line is on the figure, the higher the power loss is for the MOSFET. If the opera
ting frequency
does prove to be greater than 100 kHz, then an external PWM driver is required a
s the
microprocessor we are generating the PWM signal can not go beyond 100 kHz. It is

inconceivable that the operating frequency will be greater than 100 kHz making t
he IRL7833 the
choice. The power loss from the three main power losses due to the MOSFET only i
ncreases as
the frequency rises. As a result, when analyzing the power lost through the indu
ctor in the next
section, the power loss due to the MOSFET will push the frequency operating poin
t to a lower
frequency.
4.1.2 Inductor Selection
In selecting an inductor our primary goal again is to maximize efficiency. The m
ore
power loss our circuit draws, the less efficient the entire system is. The power
loss through the
inductor comes from the internal resistance associated with it. As a result, the
smaller the
internal resistance of the inductor, the smaller the power loss will be. Interna
l resistance of
inductors drop as the wire gauge is increased, which also allows more current to
pass through the
inductor at the cost of the inductors physical size and cost.
The system equations will be utilized to evaluate the power loss through the ind
uctor.
Table 4.2 includes all of the relevant values in order to evaluate the power los
s utilizing the
system equations:
Parameter Value
IAVG 3.30 Amps
IMAX 6.00 Amps
INEG 1.20 Amps
VMAX 24.0 Volts
VAVG 17.0 Volts
RTH 5.00.
D (Duty Cycle) 0.50
VGS 5.00 Volts
VDS 25.0 Volts
Table 4-2: Parameter Values for Power Loss Analysis
The power lost due to the internal resistance of the inductor changes as a funct
ion of frequency.
The power lost through any resistance can be determined by the following equatio
n:
P =
I 2 R (4.7)
Due to this relationship, as current increases through the resistance, the power
loss increases
exponentially. As a result, the higher the rippling current through the resistor
, the higher the
power loss over the resistor will be. To determine the actual power loss through
the internal
resistance of the inductor analysis of the rippling current waveform will be ana
lyzed. The ripple
current through the internal resistance will look like Figure 4-5.
Figure 4-5: Rippling Current through Inductor Resistance
The current will ripple over an average current. Taking the integral of an equat
ion that describes
the current waveform makes the calculation of the power loss due to the ripple a
nd average
current through the resistance relatively easy. To derive an expression for the
triangle waveform
will be complex. By looking at the current waveform in the figure above from tim
e at zero to
one quarter of the period, the current waveform becomes a straight line. The equ
ation for a
linear line is generally known as:
Y =
Mt +
B (4.8)
Where M is the slope of the line and B is the y intercept. In between the time f
rame of time at
zero to one quarter of the period, the slope is 2DI T and intersects the y-axis
at IAVG. The
equation for the current waveform between time at zero and one quarter of the pe
riod becomes:
2DI
I (t) =
t +
I AVG (4.9)
T
DI was derived in a previous section to be:
DR (I -
I )(1-
D)
TH MAX NEG
DI =
(4.10)
Lf
Now that there is a known expression for the current, calculating the power loss
due to the
rippling current waveform becomes a simple integral. A general expression for th
e power loss
using current a resistance is:
1 T
I (t)2
Rdt (4.11)
P
=
T

0
In our case, the resistance is constant and can be taken out of the integral whi
le the current is a
function of time. The time period T in equation five becomes T/4 due to the inte
gration being
over one quarter of the time period. Plugging equation (4.9) into equation (4.10
) gives the
following expression for the power loss, P1, where the current waveform is above
the average.
T
2
2
I

P1
4RL
t +
I
dt (4.12)
4

=

.

AVG
T
T
0
Simplifying the above equation gives us the following equation for the total pow
er loss through
the internal resistance of the inductor.
R DI 2 R I DI 2
L L AVG
P =+
+
I R (4.13)
1 AVG L
12 2
This power loss equation only includes the portion where the current waveform is
above the
average current. The portion of the current waveform that is below the average c
urrent will
reduce the overall power loss. The only difference in deriving this power loss i
s the slope of the
waveform is negative. The integral that determines this power loss, P2, is:
T
4RL
2
2
I

-
P2
I
dt (4.14)

4
t
=

.

AVG
T
T
0
Evaluating this integral generates the following expression:
R DI 2 R I DI 2
L L AVG
P =-
+
I R (4.15)
2 AVG L
12 2
The negative slope causes the middle term in the power loss from P1 to be negati
ve. As a result,
when deriving an equation that describes the power loss through the internal res
istance of the
inductor, the middle term in P1 and P2 drop out yielding the following expressio
n:
RL DI 2
2
P =
+
I R (4.16)
IND AVG L
12
This equation includes the power loss due to the DC bias current flowing through
the internal
resistance of the inductor and the rippling current over the DC bias. At lower f
requencies, the
rippling current, I, will increase resulting in a higher power loss through the i
nternal resistance
of the inductor.
Inductors of higher value reduce the size of the rippling current and voltage de
creasing
the power loss at lower frequencies. However, a higher internal resistance is us
ually associated
with a higher inductor value. The MOSFET power losses remain unchanged. The indu
ctors in
Table 4.3 were considered the most comparable for minimal power loss.
Inductor Size
(H)
Internal
Resistance
(m)
580-1410454 (Mouser) 100.0 42.0
580-1433428 (Mouser) 330.0 150.0
M6155-ND (Digikey) 56.00 20.0
M6199-ND (Digikey) 220.0 50.0
Table 4-3: Inductors Used in Power Loss Analysis
Plugging in the size of the inductors and their corresponding internal resistanc
e into the power
loss equation (4.16) derived above yields the results shown in Figure 4-6.
Figure 4-6: Inductor Power Loss
In Figure 4-6, the higher the rippling current through the internal resistance o
f the inductor, the
higher the power loss is. The 220 H inductor has the least power loss at low freq
uencies where
as the 56 H inductor has the least power loss at high frequencies.
Another major power loss is due to the rippling of the current and voltage. This
causes a
ripple off of the maximum power point, and the area between the maximum power po
int and the
actual ripple indicates a loss of power. This area will vary depending on the in
ductor value and
frequency that the switch is operated at. For a constant frequency, the ripple w
ill reduce as the
inductance is increased while a constant inductance will yield a smaller ripple
as the frequency
increases. To determine a value for this power loss as a function of inductance
and frequency,
the system equations derived in previous sections will need to be utilized. The
size of the ripple
current and voltage are and the size of the ripple voltage is described below:

D(1-
D)T0
DI =
(I MAX -
I NEG )
(4.17)
.
/
DR V (1-
D)
TH MAX
DV =
(4.18)
Lf
Due to the following relationship, as the current through the inductor increases
, the voltage drop
over the inductor will decrease at the same rate and vice versa.
dI
VL =
L (4.19)
dT
Figure 4-7 graphically shows the above relationship and the associated power cur
ve.
Figure 4-7: Rippling Current, Power, and Voltage Waveforms
The maximum power will occur when the current and voltage waveforms intersect. I
f the circuit
were able to operate at the intersection point without rippling, then there woul
d be no power loss.
However, there is a power loss when the voltage and the current waveforms move a
way from
this intersection point. The shaded regions in the figure above indicate where t
he power loss is
associated. Since the actual power waveform is parabola shaped, integration will
be required to
calculate the power lost. However, instead of utilizing complicated math, a stra
ight-line
approximation will give a good estimation of the power loss in this region. This
allows the
calculation of the power loss through finding the area of a triangle, and the di
fference between
the two approaches will be relatively insignificant.
Since the intersection of the voltage and current waveforms occurs twice in one
period,
the base of the triangle will be half the period or 1/2f. The amplitude of the t
riangle is simply the
difference between the maximum power and the minimum power due to the voltage an
d current
rippling.
DP =
P -
P (4.20)
MAX MIN
The minimum power is the average of the power at the two peak points of the curr
ent and
voltage waveforms in any given period.
+
P
P1 2
=
(4.21)
PMIN
2
P1 and P2 are the different power values at the two different points where the v
oltage and current
intersect in one period. P1 and P2 are defined to be:

DI
DV
P1 =
.
I AVG +
VAVG -

(4.22)

2
2 .

DI
DV
P2 =
.
I AVG -
VAVG +

(4.23)

2
2 .
The minimum power is equivalent to the average of P1 and P2. This yields the fol
lowing
expression for PMIN.
DI .
DV
P =
I V -
(4.24)
MIN AVG AVG
2
The maximum power at any point in time will simply be the average current times
the average
voltage.
(4.25)
P =
AVG I AVG
MAX V
The amplitude of the power waveform is defined to be the maximum power, PMAX, su
btracted by
the minimum power, PMIN. This yields the following expression:
DI .
DV
DP =
(4.26)
2
Now that the amplitude of the triangle is known, an expression can be composed t
o describe the
power loss due to the rippling current and voltage. The power lost in the area w
ill be one half
the base times the amplitude.
)
1
.

1
2 f
DP
Pripple
(4.27)
=

.
2
However, the power lost in the area has units of Watt-seconds and only describes
the power lost
per period. In order to find the total power loss due to the rippling current, s
imply multiplying
the above equation by the frequency of the system will give you the total power
in Watts lost due
to the rippling current and voltage waveforms.
DI .
DV
Pripple =
(4.28)
8
The rippling current and voltage will decrease the frequency increases. This wil
l result in higher
power losses at lower frequencies. The resulting power loss as a function of fre
quency is shown
in Figure 4-8.
Figure 4-8: Power Loss due to Rippling Current and Voltage
In Figure 4-8, the lower the frequency the more power loss there is. Combining a
ll of the power
losses together will yield a curve that is shaped like a U. The curve will shift,
widen, or
sharpen depending on the internal resistance of the inductor and the size of the
inductor. The
bottommost point of the U will indicate the operating frequency for that specific
inductor
which will give you the least amount of power loss. Inductors of higher value re
duce the size of
the rippling current and voltage decreasing the power loss at lower frequencies.
However, a
higher internal resistance is usually associated with a higher inductor value. T
he MOSFET
power losses remain unchanged. The inductors in the following table were conside
red the most
comparable for minimal power loss.
The losses due to the MOSFET were described and analyzed in the previous section
with
the exception that the curve due to the IRL7833 MOSFET will be exclusively used
since it is the
most efficient MOSFET that was found. At low frequencies, the switching losses a
re so
insignificant that the losses are negligible up to about 10 kHz. However, at hig
h frequencies, the
power loss exponentially increases causing the switching losses to become more s
ignificant at
higher frequencies. To generate a figure that describes the total power loss as
a function of
frequency, the power loss due to the MOSFET must be added to the power loss due
to the
inductor.
P =
P +
P +
P (4.29)
TOTAL MOS IND ripple
2
2 (trise +
t fall )VDS If RL DI 2 DVDI
POL =
I rDS +
QGS VGS f +
+
+
I RL +
(4.30)
2 12 8
Since the power loss due to the inductor increases exponentially as the frequenc
y drops and the
power loss due to the MOSFET increases exponentially as frequency increases, A U l
ike
power loss curve should result. The inductor where the bottommost point of the U c
urve has
the least power loss will be the inductor chosen for our design. The total power
loss is shown in
Figure 4-9.
Figure 4-9: Total Power Loss
In Figure 4-9, the 220 H inductor has the smallest power loss at the bottommost p
oint of the U
curve. As a result, the 220 H inductance will achieve the smallest power loss ou
t of all of the
inductors in contention.
4.1.3 Instrumentation Amplifier
The use of the instrumentation amplifier is to amplify the voltage that correspo
nds to the
current from the solar panel. The voltage that is read over the capacitor in the
current sensing
portion of the circuit has a very small range of zero to approximately 200mV, it
is necessary to
amplify this voltage in order to be more accurate when calculating the power and
adjusting the
duty cycle. To get full range and maximum resolution from the microprocessor, th
e voltage over
the cap needs to be amplified in order to extend the zero to 200mV range to a ze
ro to 5 volt
range.
The resistances in the current sensor were designed to be very low resistor valu
es in order
to keep the impedance low. An equally low impedance on the differential amplifie
r
configuration that the instrumentation amplifier is intended to be used for will
cause errors on the
current sensor forcing the voltage over the capacitor to no longer be proportion
al to the current.
The instrumentation amplifier has very large impedance at the inputs of the devi
ce keeping the
voltage difference over the capacitor proportional to the current at all times.
Another convenience of using an instrumentation amplifier over an operational am
plifier
configuration is that only one external resistance is required to set the gain o
f the amplifier. The
internal circuitry of the chosen AD627 instrumentation amplifier can be seen in
Figure 4-10.
Figure 4-10: Internal Circuitry to AD627
The voltage gain of the amplifier can be set by adjusting the external gain resi
stor RG by using
the following equation specified by the data sheet:
200 kW
G =
5 +
(4.31)
RG
Operational amplifier configurations are very similar to the figure above. Howev
er, the
resistances in the figure above are not included inside the operational amplifie
rs. As a result,
numerous resistors are required, which increasing the cost, the size, and due to
the tolerances of
the resistors, the operational amplifier will be less accurate than instrumentat
ion amplifiers. All
of the other circuitry is built inside the instrumentation amplifier with extrem
ely low tolerances
reducing size while increasing overall accuracy.
The three most important features necessary for the instrumentation amplifier to
be ideal
for the MPPT is high common mode voltages, single supply, and rail to rail outpu
t.
The positive pin on the capacitor in the current sensor is connected directly to
the solar
panel. As a result, the voltages that the instrumentation amplifier takes can re
ach values up to
twenty volts. As a result, an instrumentation amplifier that can handle these hi
gh common mode
voltages is required in order for the microprocessor to receive the appropriate
reading for the
current flowing through the solar panel. The AD627 can operate successfully with
a common
mode voltage that is 0.1 volts under the lower supply and one volt above the pos
itive power
supply. Since the instrumentation amplifier will be powered by the battery, whic
h is
approximately 24 volts, the AD627 can handle the high common mode voltages at th
e inputs.
In order for the MPPT to be a self contained system, meaning that all the device
s inside
the circuitry are powered by voltage supplies within the circuit. The battery (a
pproximately 24
volts), the solar panel (varying positive voltage supply), and the 5 volt output
from the voltage
regulator are the only available power supplies in the circuit. Since there are
no negative
supplies anywhere in the circuit, an instrumentation amplifier that can run off
one supply, single
supply, is required for design. The AD627 can run off single or double supply op
eration. The
positive rail can range anywhere between 2.2 V to 36 V in single supply operatio
n, which puts
the battery supply well within suitable range for design.
Instrumentation and operational amplifiers can only swing within a certain range
of the
supply rails. The upper supply is approximately 24 volts, so the output of the i
nstrumentation
amplifier can easily reach the upper limit of five volts to the microprocessor.
However, the
lower supply cannot go any lower than zero volts. At very low currents, the outp
ut of the
instrumentation amplifier will near zero volts. In order for the instrumentation
amplifier to
output the correct voltage that relates to the current, the output needs to be a
ble to swing as close
as possible to the supply rail. The AD627 is capable of swinging to within 70mV
of the supply
rail, which in practical applications; the current will never be small enough to
result in an output
this small.
With the AD627 meeting all the requirements specified for the instrumentation am
plifier,
the AD627 is a feasible choice to be implemented for the MPPT. The pin outs for
the AD627 is
shown Figure 4-11.
Figure 4-11: Instrumentation Amplifier (AD627) Pin Outs
4.1.4 Diode Selection
The idea of this project is to conserve power and to charge a battery as efficie
ntly as
possible. When boost circuitry is implemented, a diode is commonly used. We are
boosting the
voltage of the solar panel up to the battery voltage of 24 volts. The diode allo
ws current to flow
into the battery while eliminating the possibility of any significant reverse cu
rrent flowing out of
the battery due to the battery having a higher potential than the solar panel. A
reverse current
indicates that we are unnecessarily loosing charge back through the boost conver
ter circuitry
reducing the overall efficiency of the design.
Selecting the diode was one of the easier components to select. The diode that w
as
selected was the MBRD1040 Schottky made by Diodes Incorporated and had the speci
fications
required by design. The data sheet can be seen in the appendix, but in summary i
t has a peak
reverse voltage of 40 volts and an RMS reverse voltage of 28 volts, with a curre
nt rating of 10 A.
Both of these specifications are ideal for our project. The solar panel voltage
can vary anywhere
between zero and 20 volts. This results in the possibility of a reverse voltage
over the diode of
30 volts. The maximum current that will flow through the diode at any given time
will be
approximately 3.3 amps. With a maximum reverse voltage of 40 volts and 10 amps,
the diode is
well within design requirements.
The diode is also labeled as low power loss, high efficiency, very low leakage c
urrent,
fast switching speed, and low forward voltage drop. The major factor in selectin
g a diode is the
voltage drop over the diode. The power loss through any device can be described
by the
following equation.
PLOSS =
V .
I (4.32)
With no control over the current flowing through the circuit, a diode with a low
er voltage drop
will induce a lower power loss. In fact, the peak forward voltage drop is only a
half-volt, which
is about 0.2 volts lower than any other common diode.
The diode is in the circuit with only a few connections, but they are a little d
ifferent than
what we are used to seeing. By viewing Figure 4-12 you can see that the diode is
connected with
only three connections, using a standard DPAK molded plastic case. Pins one and
three are
utilized as one connection to the circuit board, while pin four is on the bottom
side of the heat
sink.
Figure 4-12: MBRD1040 Schottky Diode Package
In our actual circuit, pin four is connected to the battery, while pins one and
three are placed
solar panel side, at the node of the inductor and MOSFET.
4.1.5 Voltage Regulator
A supply rail of 5 volts is needed to supply the instrumentation amplifier with
a reference
voltage and power the MOSFET driver. The 5 volts for the MOSFET driver is to out
put a 5-volt
square wave to switch the MOSFET. In order to create 5 volts in the circuit, a v
oltage regulator
was selected. The LM78L05 was chosen to take the voltage from the battery, which
is
approximately 24 volts, and drop it down to a 5-volt supply. The MOSFET driver a
nd the
reference pin of the instrumentation amplifier will draw a current that is much
lower than
100mA, which is the maximum amount of current that can flow through the LM78L05.
The
minimum input for this device to output 5 volts is 6.7 volts, which will always
be supplied by the
24-volt battery. One other important feature of this device is its ripple reject
ion. This is
important because with the nature of the circuit, ripple can be an issue. When r
ipple is present,
this regulator can output a steady 5 volts DC with negligible noise with the add
ition of some
external capacitors. The pin out of the LM78L05 can be seen in Figure 4-13.
Figure 4-13: Voltage Regulator Configuration
4.1.6 MOSFET Gate Driver
The MOSFET gate driver is used to generate the PWM signal going to the gate pin
of the
IRL7833 MOSFET. There are two major benefits when implementing a MOSFET driver.
The
first is that the MOSFET driver itself sources the current that the IRL7833 MOSF
ET will draw.
The second is the MOSFET driver has a higher switching speed than the microproce
ssor can
achieve.
The TC428 MOSFET driver by Microchip was selected due to the high switching spee
d
of 30ns, single supply operation, a low current consumption of 0.4mA when logic
low and 8mA
when logic high, and a low output impedance. In order to decrease power loss thr
ough the
resistance and through the TC428 itself, a low supply voltage of five volts is i
mplemented. The
inverting input of the TC428 is connected to ground and the non-inverting input
is connected to
the PWM signal from the microprocessor. The output of the TC428 MOSFET driver is

connected to the gate of the IRL7833 MOSFET.
Figure 4-14: TC428 MOSFET Gate Driver
4.2 Operating Frequency
The operating frequency of the system mainly depends on the inductor and MOSFET
selected for use. Each pair of different MOSFETS and inductors will have a diffe
rent power loss
curve that is shaped like a U. The information pertaining to why the IRL7833 MOSFE
T and
the 220 H inductor were selected is discussed in the Parts Selection chapter. Fro
m this chapter,
the frequency corresponding to the least power loss occurs at 70 kHz.
The sweet spot of the system, the bottommost part of the U curve, changes with
different power outputs. This means that the optimal operating frequency for the
system moves
with different power outputs from the solar panel. In the Parts Selection chapte
r, the power
output from the solar panel is assumed to be 50 Watts. However, with the 700 wat
t light source
in lab, the solar panel can only achieve a power output of approximately 7 watts
. Table 4.4
includes the variables required to solve for the power loss equations derived in
the MOSFET and
inductor selection sections in the Parts Selection chapter for a solar panel pow
er output of 50
watts, 25 watts, and 7 watts:
50 Watt 25 Watt 7 Watt
Duty Cycle
(max ripple)
50.0 % 50.0 % 50.0 %
VGS 5.0 Volts 5.0 Volts 5.0 Volts
VDS 24.0 Volts 24.0 Volts 24.0 Volts
VMAX 24.0 Volts 24.0 Volts 24.0 Volts
VOC 20.0 Volts 20.0 Volts 20.0 Volts
IMAX 6.0 Amps 3.53 Amps 1.04 Amps
INEG 1.2 Amps 0.71 Amps 0.26 Amps
RTH 5.0 .
8.5 .
23.0 .
ISC 3.3 Amps 1.65 Amps 0.6 Amps
Table 4-4: Power Loss Equation Variables
The duty cycle, VGS, VDS, and VMAX are all values that are independent of the po
wer output of
the solar panel and therefore, remain unchanged. The open circuit voltage of the
solar panel,
VOC, is mainly temperature dependant and therefore remains unchanged. The IMAX,
INEG, RTH,
and ISC variables depend on the amount of light and temperature of the system an
d are derived in
the Boost Converter System Equations section. Since the temperature is constant,
these variables
will depend entirely on the amount of light illuminated on the solar panel. Plot
ting both of
power loss curves associated with the three different power outputs of the solar
panel generates
Figure 4-15.
Figure 4-15: Percent Power Loss with different Power Output
The power loss curves are displayed in percentage of the maximum power output in
order to
demonstrate that the overall efficiency of the system is unaltered by the changi
ng power. In
Figure 4-15, the optimal operating frequency of the system changes as a function
of power
output of the solar panel. As the output power from the solar panel increases, t
he optimal
operating frequency decreases. The percent power loss in each case is relatively
equivalent.
The small deviation seen in the figure above is largely due to the inability to
accurately
determine the maximum power emitted from the solar panel in all three cases.
The actual power output of the solar panel will range around values much closer
to the 25
watt curve than the 7 watt or 50 watt curve. This was viewed during some outdoor
testing of the
solar panel, where the power output ranged around 20 to 30 watts on a bright Feb
ruary afternoon.
The optimal frequency of this curve occurs at approximately 100 kHz. However, th
e
microprocessor loses a lot of resolution at about 100 kHz. As a result, the oper
ating frequency of
the system is designated to be 80 kHz in order to keep some resolution in the du
ty cycle without
adding to any power loss.
4.3 Voltage Sensing
The voltage generated by the solar panel can range anywhere between zero and twe
nty
volts. This voltage range needs to match that of the maximum input voltage range
of the
microprocessor chip, which is zero to five volts. A simple voltage divider conne
cted in parallel
with the solar panel will easily drop the twenty volt maximum output from the so
lar panel to
match the five volt maximum of the microprocessor. The voltage divider set up ca
n be seen in
Figure 4-16.
Figure 4-16: Basic Voltage Divider
The values R1 and R2 must be specified in order to achieve a one quarter drop in
voltage to the
microprocessor. The equation describing the voltage divider in the system shown
in Figure 4-16
is:

R2
VPIC =
VSOLAR .

(4.33)
R +
R

1 2 .
If twenty volts are emitted from the solar panel, then the voltage at the microp
rocessor should be
five volts. Plugging in these values in the equation above and solving for R1 yi
elds the following
expression.
R1 =
3R2 (4.34)
As long as this resistor ratio is kept true, the voltage generated by the solar
panel will always lie
in the range of zero to five volts, which is essential in order to prevent any d
amage to the
microprocessor chip.
The impedance for the two resistors needs to be large in order to minimize the c
urrent
drawn by the voltage divider. However, the impedance cannot be too large due to
the
requirement of an RC filter in order to filter out the rippling voltage generate
d by the solar panel.
If the impedances of the RC filter and the voltage divider are relatively close,
than the RC filter
will draw too much current from the voltage divider causing the voltage divider
to drop a factor
that is not equivalent to one quarter. The resistance of the RC filter needs to
be on the order of
one fifty times greater than the resistors in the voltage divider as to not affe
ct the voltage divider.
A resistor value of 10k.
was selected for R2. In order to keep the resistor ratio for the voltage
divider intact, the resistance for R1 is 30k. Ohms law is used in order to determi
ne the amount
of current drawn by the voltage divider:
V V 20
SOLAR
I ==
==
0.5mA (4.35)
R R1 +
R2 40 k
With a current of 0.5mA drawn, the power loss through the voltage divider is onl
y 10mW and is
relatively insignificant.
The voltage ripple over the voltage divider depends on the switching frequency o
f the
MOSFET and the inductance used in the boost converter. The higher the frequency
and the
larger the inductance, the smaller the ripple will become. However, an inductanc
e of 220 H
inductor at a frequency of 80 kHz was selected to be implemented for this projec
t. These values
cause a voltage ripple from the solar panel of one volt seen in the waveform sho
wn in Figure 4
17.
Figure 4-17: Voltage Ripple at Solar Panel
Figure 4-17 indicates that the voltage from the solar panel ripples approximatel
y one volt.
The voltage divider steps the voltage from the solar panel down by a factor of 4
. As a result, the
one volt ripple in the waveform above should drop down to a 250mV ripple as show
n in Figure
4-18.
Figure 4-18: Voltage Ripple at Voltage Divider
In Figure 4-18, the voltage ripple from the solar panel does in fact drop down t
o approximately
250mV. The actual ripple is 240mV, but the deviation is insignificant due to the
tolerances of
the resistances. Even with a smaller ripple voltage of 240mV, the ripple is stil
l quite significant.
Without filtering this voltage waveform at 80 kHz, the microprocessor will read
voltage levels
that vary significantly.
The affects of this ripple can be easily eliminated by implementing a small RC f
ilter off
of the voltage divider. The voltage sensing configuration with an RC filter can
be seen in Figure
4-19.
Figure 4-19: Voltage Divider with RC Filter
The impedance of the resistor in the RC filter must be at least a factor of ten
times the size of the
resistors in the voltage divider. Since the values of the resistors in the volta
ge divider are 10k.
and 30k, a resistance value of 100k.
was selected. Due to the much larger resistance of the
filter, the filter will have an insignificant effect on the voltage divider.
By taking the inverse of the resolution and multiplying by 5 volts then dividing
by the
ripple at the voltage divider will give us the attenuation required. This is cal
culated from the
following equation:
Vad
Gain =
(4.36)
Re s V
ripple
1
*5
0.00488
1024
Gain =
=
=
.01953 (4.37)
.250 .250
By attenuating the 250mV ripple off the voltage divider by 0.01953 or -34.19dB,
the rippling
voltage off of the voltage divider will be insignificant with respect to the mic
roprocessor. Using
the transfer function of the RC filter the capacitance can be calculated to achi
eve a value of 34.19dB
at 80 kHz:
1
H =
(4.38)
2pfRC
1 1
C ==
=1.04 nF (4.39)
2pfRH (2p)(
100 k )(
80 k )(
19.53 m)
Plugging in the values of 100k, a frequency of 80 kHz and solving for C yields a
value of
1.04nF. However, a higher resistance will attenuate the signal even more but inc
rease the time
constant of the RC filter. The 10% to 90% rise and fall time is related to the r
esistance and
capacitance of the RC filter by the following equation.
.
=
2.2RC (4.40)
With a resistance of 100k.
and a capacitance of 1.04nF, the time constant is calculated to be
0.23ms. The length of the 0.23ms time constant is insignificant in comparison to
the time
constant of the control loop, which is on the order of approximately a 200ms del
ay. As a result,
the capacitance of the filter can be increased, which will further attenuate the
waveform on the
voltage divider. A capacitance of 0.01 F will result in a time constant of 2.2ms
with an
attenuation of -54dB. With this new capacitance, the time constant is still rela
tively small in
comparison to the time constant of the control loop while attenuating the signal
enough so the
rippling voltage will have almost no effect on the microprocessor. The resulting
filtered
waveform can be seen in Figure 4-20.
Figure 4-20: Filtered Voltage Waveform
In Figure 4-20, the ripple of the voltage waveform is approximately 5mV. The 5mV
ripple is so
small that the rippling waveform will not have any impact on the microprocessors
ability to
measure the voltage. The final schematic for the voltage sensor is shown in Figu
re 4-21.
Figure 4-21: Voltage Sensing Schematic
4.4 Current Sensor
As discussed in the background section, a simple RC filter placed in parallel wi
th the
inductor, the voltage over the capacitor will be proportional to the current flo
wing through the
inductor. The circuit in Figure 4-22 was used in order to determine the amount o
f current
produced by the solar panel.
Figure 4-22: Current Sensor
To determine the specified values of the capacitance and resistor values for the
inductor sensing,
the following equation from the Inductor Current Sensing section is utilized.
L
RF CF =
10 (4.41)
RL
Where RF and CF are the capacitance and resistor values of the inductor sensing
portion and L is
the inductance value of the inductor (220 H) and RL is the internal resistance of
the inductor
(40m). The ratio between RF and CF becomes.
10 L
R =
(4.42) F CF RL
Where CF and RF are the only two unknowns in the equation (4.42). If the impedan
ce of any
resistors at the input of the instrumentation amplifier configuration is not muc
h higher than the
impedance of the inductor sensor, than the ratio in the equation above will be a
ltered causing
deviations on the voltage over the capacitor making it extremely difficult to de
termine the
appropriate gain for the system. As a result, the capacitance, CF, should be kep
t high on the
magnitude of 100 F in order to keep the resistance, RF, relatively low. A 100 F ca
pacitance
results in a resistance of 550.
using the ratio designated above.
In order to prove that the differential voltage over the capacitor is in fact pr
oportional to
the current, the RC filter is connected in parallel with the inductor with the v
alues derived above.
The boost converter circuit is used to test the proportionality of the voltage o
ver the capacitor.
To adjust the amount of current flowing from the solar panel, the duty cycle of
the MOSFET
switch is adjusted. The higher the duty cycle, the more current will flow from t
he solar panel.
The solar panel is connected to an amp meter in order to measure the actual curr
ent flowing from
the solar panel and a practical multi-meter was used to measure the voltage over
the capacitor.
The results are shown in Figure 4-23.
Figure 4-23: Capacitor Voltage vs. Current
In Figure 4-23, the voltage difference over the capacitor is proportional to the
current flowing
through the inductor. In order to achieve the full range of zero to five volts t
hat the
microprocessor can handle, the voltage difference over the capacitor needs to be
amplified in
order for the maximum amount of current flowing through the solar panel to match
the five volt
maximum at the microprocessor.
4.4.1 Alternative Methods
There were three different differential amplifier configurations that could be u
sed to
amplify the voltage over the capacitor. A regular differential amplifier as show
n in Figure 4-24
could be used.
Figure 4-24: Differential Amplifier
However, the impedance at the inputs of the operational amplifier was causing th
e
proportionality constant between the voltage over the capacitor and the current
flowing through
the inductor to change. As a result, selecting the appropriate gain for the syst
em was almost
impossible to determine as well as achieve accurate results making the implement
ation of this
configuration undesirable.
Another differential amplifier configuration in contention contained three opera
tional
amplifiers. This configuration is shown in Figure 4-25.
Figure 4-25: Differential Amplifier (3 Operation Amplifiers)
This configuration had the inputs of the differential voltage going straight int
o operational
amplifier. The input impedances of typical operational amplifiers are extremely
high. As a
result, the proportionality constant between the differential voltage over the c
apacitor and the
current flowing through the inductor is unaffected. However, the high common mod
e voltages
going into the positive and negative terminals caused the voltages at certain po
ints in the circuit
to rise above the common voltage that the operational amplifier could handle cau
sing an error at
the output of the entire configuration.
The last setup that was in contention was the use of an instrumentation amplifie
r. An
instrumentation amplifier does not have the bulk of typical differential amplifi
er configurations
using operational amplifiers. Instead, all of the internal circuitry that goes i
nto the design of the
differential amplifier is built right into the instrumentation amplifier with hi
gh precision resistors
greatly increasing the overall accuracy of the circuit. The instrumentation ampl
ifiers simply
adjust the gain of the amplifier by simply changing an external resistor applied
to the pins of the
instrumentation amplifier. The proportionality constant between the differential
voltage over the
capacitor and the current is unaffected due to the very high input impedance of
the
instrumentation amplifier. One major constraint for the instrumentation amplifie
r is that it be
able to handle the high common mode voltage of the differential voltage going in
to the inputs of
instrumentation amplifier.
4.4.2 Gain setting
The voltage range that is going into the microprocessor will be from zero volts,

representing no current, and five volts, representing that the maximum amount of
current is
flowing from the solar panel. As specified by the solar panel, the maximum amoun
t of current
that can flow is 3.3 amps. However, the pins for the microprocessor can only han
dle a maximum
voltage of five volts. The sensitivity of the pins on the microprocessor is so h
igh that if a voltage
slightly higher than five volts can easily damage any of the pins on the micropr
ocessor. If the
pin on the microprocessor chip that detects the amount of current flowing from t
he solar panel is
damaged or blown, then the microprocessor will no longer be able to locate the m
aximum power
point rendering the entire device useless. As a result, careful measures need to
be taken in order
to ensure that the microprocessor is protected from any over voltages that may c
ome from the
voltage and current sensors.
To ensure that there are no over voltages that will occur, it is safer to assume
that the
maximum amount of current flowing from the solar panel is 4.0 amps. The solar pa
nel should
never be able to produce a current of 4.0 amps protecting the microprocessor chi
p from ever
being damaged by the output of the current sensor. The only sacrifice made in ma
king this
assumption is accuracy. Since the zero to five volt range is covering a larger c
urrent range, the
resolution for the microprocessor chip decreases in accuracy. However, accuracy
is a non-issue
in the design of this MPPT. Regardless of what the actual value of the current f
lowing from the
solar panel is, the maximum power point will still occur at the same operating p
oint. As long as
the output voltage of the current sensor is proportional to the changing current
, then the
maximum power point will be achieved.
A current flowing from the solar panel through the inductor will cause a voltage
over the
capacitor, VDIFF that is proportional to the amount of current generated from th
e solar panel.
Changing the duty cycle of the switch controls the amount of current flowing thr
ough the
inductor from the solar panel. The higher the duty cycle, the higher the current
will be. The duty
cycle was adjusted in order to achieve a current of 0.401 amps. A current of 0.4
01 amps flowing
through the inductor induces a voltage over the capacitor of 23.0mV. Since the v
oltage over the
capacitor is proportional to the current, if the current were to increase by a f
actor of 10, then the
voltage over the capacitor would increase by a factor of 10 as well. Due to prop
ortionality, the
following equation can be used to determine the voltage over the capacitor if 4.
0amps were to
flow through the inductor.
I V
1 C1
=
(4.43)
I V
2 C 2
0.401 A 23.0mV
=
(4.44)
4.00 A VCMAX
Where VCMAX refers to the voltage induced over the capacitor due to a current of
4.0 amps
produced by the solar panel. With a current of 4.0 amps flowing through the indu
ctor, a voltage
of 0.229 volts will be induced over the capacitor. A gain is required to boost u
p the voltage over
the capacitor since a current of 4.0 amps should relate to a voltage of 5.0 volt
s at the pin of the
microprocessor. As a result, the 0.229 volts over the capacitor needs to be ampl
ified in order to
reach the 5.0 volt requirement. The gain can be determined using the following e
quation:
G VC =
VPIC (4.45)
Where G is the gain needed to amplify the voltage over the capacitor, VC, to ach
ieve the
appropriate voltage at the microprocessor, VPIC. Rearranging the equation above
yields:
V 5
PICMAX
G =
==
21.8 (4.46)
VCMAX 0.229
In order to 5.0 volts at the microprocessor for a current of 4.0 amps requires t
he voltage over the
capacitor to be amplified by approximately 21.8. Since the AD627 instrumentation
amplifier is
being used as the amplifier, the amplification can be acquired by adjusting a si
mple resistor
value. Stated in the data sheet of the AD627 instrumentation amplifier the gain
can be set
through the following equation:
200 k
Gain =
5 +
(4.47)
RG
Where G is the gain of the instrumentation amplifier and RG is the resistor valu
e is necessary
for the gain, G. With the gain of the system already determined to be 21.8, the
RG associated
with this gain is determined to be:
200 k 200 k
RG ==
=
11.9kohms (4.48)
G -
5 21.8 -
5
A resistance of 11.9k.
will achieve a gain of 21.8. However, a precise resistance of 11.9k.
is
impractical and cannot be accurately achieved. A simple 5% 12k.
resistor will work perfectly
fine for the purposes of this design. The 12k.
resistance corresponds to a gain of 21.67, which
is extremely close to the theoretical gain of 21.8. A 1% tolerant resistance is
recommended for
the use with the AD627 instrumentation amplifier, but a highly precise resistanc
e is not needed
for the purposes of this design. As long as the voltage going into the microproc
essor is
proportional to the current, then the system does not need to be very precise. A
s a result, a 5%
tolerant resistance can be used.
4.4.3 Initial Testing
Due to the simplicity of the design with an instrumentation amplifier, the AD627
was
hooked directly up to the capacitor as shown in Figure 4-26.
Figure 4-26: AD627 Initial Test Circuit
The AD627 is run off a positive 24 volts for the positive supply rail and ground
for the negative
supply. The AD627 is a very good rail to rail swing allowing the output voltage
to swing within
100mV of the positive and negative rails. For the entire circuit to be self cont
ained meaning
there are now external power supplies necessary, the positive terminal will be a
pproximately 24
volts depending on what the actual voltage of the battery is and negative termin
al will be
connected to ground. There will be no negative supplies available so ground is t
he most negative
voltage that can be achieved. However, for testing purposes, the positive supply
is connected to
a 24-volt supply from an external power supply. The reference voltage pin of the
AD627 is also
connected to ground, or zero volts. Adjusting the duty cycle of the switch acqui
res complete
control over the amount of current being generated by the solar panel. Due to th
e restrictions of
the Hewlett Packard 33120A function generator, the duty cycle can only swing fro
m 20 percent
to 80 percent. However, this range will allow a plentiful range of current to te
st the functionality
of the design. A 1k.
load was connected to the output of the AD627 as to have a load at the
output of the instrumentation amplifier. An amp meter is connected from the outp
ut of the solar
panel to the input of the circuit to measure the current and a regular multimete
r is used to
measure the voltages over the capacitor and at the output of the AD627. VEXP is
calculates
simply by amplifying the voltage over the capacitor by the gain of the AD627.
V =
G V (4.49)
EXP CAP
The gain of the system is still 21.67. The duty cycle was changed from 20 to 80
percent with by
increments of 10%. The data obtained is shown in Table 4.6:
Duty Cycle
(%)
Current
(A)
VDIFF
(mV)
VEXP
(V)
VACT
(V)
20 0.139 8.60 0.186 0.110
30 0.265 16.7 0.362 0.350
40 0.490 31.5 0.683 0.795
50 0.526 33.9 0.735 0.897
60 0.563 36.5 0.791 0.94
70 0.592 38.4 0.832 0.951
80 0.600 39.0 0.845 0.931
Table 4-6: Initial AD627 Test Data
In Table 4.6, the actual output of the AD627 is varied from the expected output.
Figure
4-27 gives more insight on the data shown in Table 4.6.
Figure 4-27: Initial Testing of AD627
Figure 4-27 indicates that the AD627 is not functioning properly. The AD627 basi
cally
takes the voltage difference over two points and applies a gain to it. Since the
voltage difference
over the capacitor is proportional to the current flowing through the circuit, t
he output of the
AD627 should be proportional to the current as indicated by VEXP in the figure a
bove.
However, the actual output of the AD627 is not proportional to the current. As a
result, some
aspect in our circuit is causing major errors in the output of the AD627.
4.4.4 Common Mode Voltage
In previous differential amplifier and instrumentation amplifier configurations
tested
previously to the AD627, the common mode inputs were too high for the configurat
ions to
handle causing unexpected outputs. The internal configuration of the instrumenta
tion amplifier
is shown in Figure 4-28.
Figure 4-28: Internal Circuitry of the AD627
In Figure 4-28, the AD627 is an instrumentation amplifier utilizing only two ope
rational
amplifiers whereas the most common configuration utilizes three operational ampl
ifiers.
However, the data sheet indicates that the AD627 would work perfectly for our de
sign. Even
though a large majority of past problems have been due to high common mode volta
ges, the
problem could occur with a differential voltage at high common mode voltages, an
d could be due
to the AC signals going into the inputs of the positive and negative terminals o
f the AD627.
The problem with the common mode of the input comes from the output of the
operational amplifier in the internal circuitry designated as A1. Since the outp
ut of the two
operational amplifiers inside the AD627 cannot swing any higher than the supply
rails of the
AD627. The data sheet of the AD627 provides an equation to determine the output
voltage of
the operational amplifier, A1, as a function of the common mode voltage, VCM, th
e reference
voltage, VREF, the differential voltage at the inputs, VDIFF, and the value of t
he gain resistance,
RG.

25 k
VA1 =
1.25 (VCM +
0.5)-
0.25 VREF -VDIFF .
-
0.625
(4.50)
RG

.
As indicated by the test conditions of the circuit, VREF is set to zero volts an
d can be taken out
of the equation above. When testing to see if the above equation matches actual
testing of the
AD627, the two input terminals will be set equal to each other in order to elimi
nate the
possibility that the differential voltage is causing the errors. As a result, VD
IFF is also set equal
to zero. Canceling out these two variables results in the following equation:
V =
1.25 (V +
0.5)
(4.51)
A1 CM
When testing the common mode voltages of the AD627, we have no control over the
voltage
VA1, but we do have control over the common mode voltage, VCM. As indicated by t
he data
sheet of the AD627, the output of either of the two operational amplifiers as we
ll as the output of
the AD627 can only reach 70mV below the positive rail, which is still a positive
24 volts.
Setting VA1 to 23.3 volts, which is the maximum output the operational amplifier
, A1, can
achieve. Solving for VCM will provide the theoretical value at where the AD627 w
ill no longer
operate properly due to a high common mode voltage.
VA1 23.93
V =
-
0.5 =
-
0.5 =
18.65 Volts (4.52)
CM 1.25 1.25
Any common mode voltage, VCM, under 18.65 volts cause no common mode problems wi
th the
AD627, as the output of the operational amplifier, A1, is below the maximum valu
e it can
achieve. However, once the common mode voltage, VCM, increases above 18.65 volts
, the
output of the operational amplifier, A1, will increase to a value higher than it
can swing causing
the output of the AD627 to be incorrect. However, a test would need to be done i
n order to
confirm that the value found through using the equation provided by the data she
et is correct.
The test circuit in Figure 4-29 was utilized to test the common mode voltage of
the
instrumentation amplifier.
Figure 4-29: Common Mode Voltage Test Circuitry
In Figure 4-29, the reference voltage, VREF, is set to ground and the differenti
al voltage,
VDIFF, is set to zero by connecting the positive and negative terminals together
. Since the
differential voltage is zero, then the output of the AD627 should be approximate
ly zero volts. To
test the common mode voltage, the common mode voltage is slowly incremented from
zero volts
until the output is no longer zero volts. At this point, the common mode voltage
has gone too
high sending the output of the operational amplifier, A1, above its limitation.
This point occurs
at 18.64 volts, which is extremely close to the expected 18.65 volts from the eq
uation provided
by the data sheet. Through constant testing of the solar panel throughout the de
sign process, the
average common mode voltage that the AD627 will see in the test conditions provi
ded in lab is
approximately 17.5 volts. This indicates that the common mode voltage is not the
problem with
the AD627.
4.4.5 Differential Voltage
Another possible issue is the voltage difference at the input terminals. It is e
ntirely
possible that the difference is too small for the AD627 to accurately detect and
amplify giving
the output errors. To test this condition, a DC signal must be input to both ter
minals in order to
eliminate the possibility that the AC could possibly be causing the error. The v
oltage over the
capacitor could range anywhere between 0mV to approximately 200mV. However, with
the
limited lighting provided in the lab, the capacitor voltage can only range in th
e vicinity of 10mV
to 70mV, which is where the error is occurring. As a result, if the small differ
ence is the cause
of the error, then the results from this test should indicate the same results a
s the initial test. The
test configuration is shown in Figure 4-30.
Figure 4-30: DC Input Test Circuitry
The solar panel common mode voltage is well within the 18.65 limit, so the outpu
t of the AD627
will react the same of the common mode voltage is zero or 17 volts. For simplici
ty, the common
mode voltage is set to zero. The negative terminal of the AD627 is connected to
ground to set
the common mode voltage to near zero volts whereas the positive terminal is conn
ected to one of
the power supplies that will adjust the differential voltage, VDIFF from 10mV to
70mV. By using
the power supply to adjust the differential voltage, the DC voltage inputs seclu
de the test from
any errors that may be due to the AC voltages over the capacitor. The output of
the AD627
should be equivalent to the differential voltage, VDIFF, times the 21.67 gain of
the system. Table
4.7 contains the differential input test data.
VDIFF
(mV)
VEXP
(V)
VACT
(V)
10 0.255 0.280
20 0.510 0.533
30 0.765 0.790
40 1.020 1.045
50 1.275 1.295
60 1.530 1.555
70 1.785 1.810
Table 4-7: Differential Input Test Data
In Table 4.7, the actual output is close to the expected output. Figure 4-31 giv
es a better
visualization of the accuracy of the AD627.
Figure 4-31: Differential Input Test
In Figure 4-31, the actual output of the AD627 is nearly on top of the expected
output. This
means the AD627 did exactly what was expected of it indicating that the error se
en in the initial
test of the AD627 is not due to the small differential voltage. With the common
mode voltage
and the small differential input not being the source for the error, the only it
em not tested are the
AC signals going into the input terminals of the AD627.
4.4.6 Common Mode Rejection Ratio (CMRR)
Every operational and instrumentation amplifier has a parameter known as the com
mon
mode rejection ratio (CMRR). This parameter indicates how the operational or ins
trumentation
amplifier rejects common mode noise as a function of frequency. At low frequenci
es, the
CMRR is high; the instrumentation or operational amplifier resulting in consiste
nt and precise
results will easily reject meaning any noise due to the AC signal. However, when
the
frequencies of the AC signals get high, the CMRR of the operational and instrume
ntation
amplifiers significantly drops causing the amplifiers to have a difficult time e
liminating the noise
due to the amplitude and frequency of the rippling inputs. As a result, it is im
portant to maintain
a high CMRR at all times. Figure 4-32 is located in the data sheet indicating th
e CMRR as a
function of frequency for the AD627.
Figure 4-32: AD627 Common Mode Rejection Ratio (CMRR) vs. Frequency
In Figure 4-32, the CMRR is at 84dB at very low frequencies. A high CMRR such as
84dB will
eliminate the common mode noise at the input terminals. However, at higher frequ
encies of
about 10 kHz, the CMRR drops down to approximately 20dB, which relates to a 75%
drop in
CMRR. This is a significant decrease and should be a means for concern consideri
ng the
operating frequency of the microprocessor is at 80 kHz. Due to the low CMRR at 8
0 kHz, the
common mode noise is not completely eliminated, which would cause an inconsisten
t output
explaining the inconsistency with the output of the AD627. An AC signal with hig
her amplitude
will cause more inconsistency at the output than an AC signal with smaller ampli
tude. The noise
associated with the AC signal with higher amplitude will be more significant cau
sing the output
to vary more so than an AC signal with smaller amplitude. Figure 4-33 shows the
rippling
waveforms going into the inputs of the AD627.
Figure 4-33: Voltage Waveforms over Inductor Sense Capacitance
In Figure 4-33, the AD627 has a 1.3V peak to peak voltage at 80 kHz going into e
ach the
positive and negative terminals. An AC signal of this magnitude is most likely t
he cause to the
errors seen in the initial test of the AD627. The trend of the initial test of t
he AD627 indicates
that the trend of the output is approximately correct, but the actual deviates s
ignificantly over this
trend. To prevent this common mode noise from affecting the output of the AD627
simple low
pass RC filters at the input terminals should eliminate the inconsistent output
of the AD627.
The implementation of two RC filters, one on the positive input and one on the n
egative
input of the AD627, will significantly attenuate the AC signal going into the AD
627, which will
essentially cause the CMRR to increase. As a result, any common mode noise going
into the
instrumentation amplifier should be rejected causing the AD627 to produce result
s that are
expected. The configuration to be implemented with the two low pass RC filters i
s shown in
Figure 4-34.
Figure 4-34: AD627 Configuration with Low Pass Filters at Input
In Figure 4-34, there are two simple low pass filters connected to the input ter
minals of the
AD627. R1 and C1 form one low pass filter and R2 and C2 form the other low pass
filter. The
capacitance C3 is needed to maintain common-mode rejection at lower frequencies
as indicated
by the data sheet of the AD627 and acts like a second stage filter. In order to
maintain high
common mode rejection, the filter formed by R1 and C1 must be equivalent to the
filter formed
by R2 and C2; meaning R1 is equal to R2 and C1 is equal to C2. A low pass filter
is typically
characterized by the point where the 3dB frequency occurs.
1
=
(4.53)
f3dB
2pRC
Any noise beyond the 3dB frequency point begins to be attenuated. The further aw
ay the
frequency is from the 3dB point, the more attenuated the noise is from that freq
uency. Since the
common mode noise of the AD627 is a result from 80 kHz, it is a good idea to kee
p the 3dB
frequency well below 80 kHz as to ensure that the noise is negligible. For optim
al performance
while minimizing the size, a ceramic capacitance of 0.01 F will be implemented in
the filter.
The resistance of the low pass filter should be kept to at least 100 times great
er than the
resistance of the resistance in the inductor sensor. To be safe, a resistance of
100k.
is used
making the impedance of the filter 181 times greater than that of the inductor s
ensor. With this
difference in impedance, the filter applied to the AD627 should not have any aff
ect on the
functionality of the inductor sensor. With this resistance and capacitance the 3
dB frequency
should occur at:
1 1
==
=
159.2Hz (4.54)
f3dB
2pRC 2p(100 k )(
0.01 m)
Since the 3dB frequency is much lower than 80 kHz, the noise coming from the 80
kHz AC
signal will be greatly attenuated. The second stage low pass filter formed by th
e capacitance C3
will attenuate the noise more. The data sheet of the AD627 provides the 3dB rela
tionship of this
filter as follows:
1
(4.55)
f3dB =
2p(R1 +
R2 )C3
The values for R1 and R2 are already known values at 100k. The 3dB frequency of t
he second
stage filter should be kept relatively low to keep the size of the capacitor C3
relatively small. To
get an idea of the proximity of an appropriate value of C3, plugging in 200Hz fo
r the 3dB
frequency and solving for C3 yields the following expression:
1 1
C3 =
==
4nF (4.56)
2p(R1 +
R2 )
f3dB 2p(200 k )(
200 )
With a 3dB frequency of 200 Hz, the corresponding capacitance is 4nF. However, 4
nF is not a
typical capacitance value. The nearest capacitance value that is very small in s
ize is a 0.001 F
capacitor. Using the same equation above to solve for the 3dB frequency for the
second stage
filter, yields a 3dB frequency of 800Hz, which is still much lower than 80 kHz.
The two low
pass filters both have a 3dB frequency below 1 kHz, which will greatly attenuate
any noise that
was originally in the 80 kHz signal.
In order to prove that the CMRR was the cause for the error seen in the original
test of
the AD627, the same test configuration as the initial test of the AD627 was used
with the
addition of the low pass filters at the inputs. The inputs to the AD627 will com
e directly from
the terminals of the capacitor. By adjusting the duty cycle of the switch from 2
0 to 80 percent in
increments of 10 percent, the amount of current generated by the solar panel wil
l change. With
the low pass filters on the inputs, the common mode noise should be attenuated r
esulting in the
AD627 producing an output voltage that is proportional to the current. The curre
nt is measured
through an amp meter whereas the voltages over the capacitor and the output of t
he AD627 is
measured using a voltmeter. The expected output of the AD627 is calculated by mu
ltiplying the
theoretical gain of 21.67 to the voltage over the capacitor. The results are sho
wn in Table 4.8.
Duty Cycle
(%)
Current
(A)
VDIFF
(mV)
VEXP
(V)
VACT
(V)
20.0 0.145 8.20 0.209 0.191
30.0 0.269 15.5 0.395 0.392
40.0 0.383 22.5 0.574 0.573
50.0 0.419 24.8 0.632 0.634
60.0 0.455 27.0 0.689 0.693
70.0 0.484 28.9 0.737 0.741
80.0 0.495 29.6 0.755 0.758
Table 4-8: CMRR Test Data
Plotting the expected output and the actual output of the AD627 as a function of
current in
Figure 4-35 gives a better perspective of the meaning in the data shown in Table
4.8.
Figure 4-35: CMRR Test
In Figure 4-35, the actual output of the AD627 lies almost right on top of the e
xpected output.
The most important thing to notice is that as the current increases, the voltage
output of the
AD627 appears to be perfectly linear. As a result, the low CMRR due to the high
frequency
signal going into the input terminals of the AD627 was the source of the error.
4.4.7 Common Mode Range
As proved through tests and the data sheet of the AD627, the high common mode vo
ltage
going into the instrumentation amplifier could still become a problem. The maxim
um common
mode voltage that can be input into the AD627 without error is 18.67 volts where
the solar panel
has the potential to reach up to 20 volts. One way to correct this problem is to
add a reference
voltage to the AD627. The equation for the output of the internal operational am
plifier, A1, of
the AD627 indicates that with a reference voltage, the AD627 can handle a higher
common
mode voltage.

25 k
VA1 =
1.25 (VCM +
0.5)-
0.25 VREF -VDIFF .
-
0.625
(4.57)
RG

.
As you can see from the equation, the application of a reference voltage reduces
the output of
internal operational amplifier, A1. As a result, the common mode voltage, VCM, c
an reach a
higher value before the output of A1 reaches the supply rail. A common voltage a
vailable to us
in our self-contained system is 5 volts. There is already the need for a 5-volt
supply for the
microprocessor chip, so no additional circuitry is needed to apply 5 volts to th
e reference pin of
the AD627. VDIFF will remain very small and can be considered insignificant, VRE
F is 5 volts
and VA1 will be 23.3 volts, which is the maximum the output A1 can reach (70mV b
elow the
supply rail). Solving the above equation for VCM yields:
VA1 +
0.25 VREF 23.93 -
0.25 5
V =
-
0.5 =
-
0.5 =
19.64 Volts (4.58)
CM 1.25 1.25
At a common mode voltage of 19.64 volts and above, the internal operational ampl
ifier will
reach its maximum output causing the output of the AD627 to be false. By setting
the two input
terminals of the AD627 equal to one another can prove that the addition of a ref
erence voltage
will increase the previous clamp of 18.65 volts to 19.64 volts. With both input
terminals
equivalent, the output of the AD627 should remain zero volts. As before, when th
e maximum
common mode voltage is reached, the output will no longer remain zero. By slowly
increasing
the common mode voltage, the output no longer remains zero at 19.66 volts, which
is very close
to what is expected. In actual operation of the MPPT, the solar panel will be op
erated away from
the open circuit voltage and will never be near enough to 19.66 volts to pose a
problem during
operation.
The microprocessor chip can only handle a voltage of zero to 5 volts at its inpu
ts. With a
5-volt reference, the microprocessor chip now will see voltages in the range of
5 to 10 volts.
There are two possible ways to reduce the range from zero to five volts once aga
in. The first is
adding another differential amplifier configuration to subtract the 5 volt bias.
The second is
inverting the output of the AD627 and inverting it again at the microprocessor.
The first method requires another operation amplifier chip with the addition of
four
resistors for the configuration. The addition of another operational amplifier w
ill lower the
accuracy of the current sensing due to the resistor tolerances as well as introd
uce more noise into
the control system. This method increases the overall size of the circuitry, cos
t, and increases the
amount of noise that is introduced to the control system making it an impractica
l approach to
eliminating the 5-volt bias.
The input terminals of the AD627 can be swapped causing a voltage difference tha
t is
negative. However, by implementing this method, the output of the AD627 is now i
nversely
proportional to the current. This can be easily fixed by programming the micropr
ocessor to
invert the input. There is no need for additional components reducing the cost a
nd eliminating
the risk of adding noise to the control system. The microprocessor chip can easi
ly invert the
numbers going in pin calculating voltages that are proportional to the current w
hen they are
actually inversely proportional. Using this method is the most practical way to
implement the
op-amp while increasing the common mode range.
4.4.8 Output Filter
The output waveform of the AD627 instrumentation amplifier has some ripple assoc
iated
to it. The output voltage waveform of the AD627 is shown in Figure 4-36.
Figure 4-36: Unfiltered AD627 Output Voltage Waveform
The rippling waveform is biased up to a DC value depending on the current flowin
g through the
circuit. However, the waveform ripples approximately 60mV, which can cause resol
ution errors
within the microprocessor. A small RC filter off of the output of the AD627 can
easily filter out
the rippling waveform. Filtering the output of the AD627 is designed the same wa
y the output of
the voltage sensor is filtered.
By taking the inverse of the resolution and multiplying by 5 volts then dividing
by the
ripple at the voltage divider will give us the attenuation required. This is cal
culated from the
following equation:
Vad
Gain =
(4.59)
Re s V
ripple
5 5
Gain =
==
0.0814 (4.60)
1024 .
0.06 61.44
By attenuating the 60mV ripple off the voltage divider by 0.0814 or -21.8dB, the
rippling output
voltage of the AD627 will be insignificant with respect to the register values o
f the
microprocessor. In order to keep the time constant and the capacitance of the ou
tput filter as
small as possible, a 10k.
resistor is selected. Using the transfer function of the RC filter the
capacitance can be calculated to achieve a value of -21.8dB at 80 kHz:
1
H =
(4.61)
2pfRC
1 1
C ==
=
2.44 nF (4.62)
2pfRH (2p)(
10 k )(
80 k )(
0.0814 )
Plugging in the values of 10k, a frequency of 80 kHz and solving for C yields a v
alue of
2.44nF. However, a higher resistance will attenuate the signal even more but inc
rease the time
constant of the RC filter. The 10% to 90% rise and fall time is related to the r
esistance and
capacitance of the RC filter by the following equation.
.
=
2.2RC (4.63)
With a resistance of 10k.
and a capacitance of 2.44nF, the time constant is calculated to be
53.7 s. The length of the 53.7 s time constant is insignificant in comparison to t
he time
constant of the control loop, which is on the order of approximately a 200ms del
ay. As a result,
the capacitance of the filter can be increased, which will further attenuate the
waveform on the
output of the AD627. A capacitance of 0.01 F will result in a time constant of 0.
22ms with an
attenuation of -34dB. With this new capacitance, the time constant is still much
smaller in
comparison to the time constant of the control loop while attenuating the signal
enough so the
rippling voltage will have almost no effect on the microprocessor. The resulting
filtered
waveform can be seen in Figure 4-37.
Figure 4-37: Filtered Current Sensing Output
In Figure 4-37, the waveform is filtered well enough to provide the microprocess
or with a clean
enough signal in order to prevent significant quantization noise in the control
loop.
4.4.9 Current Sensing Schematic
The final schematic for the instrumentation amplifier is shown in Figure 4-38.
Figure 4-38: Final Current Sensing Schematic
4.5 Controls
The controller of the MPPT is based on a digital microprocessor chip. The purpos
e of the
controller is to find the maximum power point of the solar panel and output a du
ty cycle to the
boost converter to make the solar panel operate at this point. For any general c
ontroller, the
simplest control system is shown in Figure 4-39.
Figure 4-39: General Controller
The set point is the maximum power point. Unfortunately this power point can mov
e up
and down depending on sunlight conditions and temperature. Instead the controlle
r has to be
designed in order to figure out where the maximum power point is based on where
we are on the
V-I curve of the solar panel.
At the maximum power point, the slope of the power as a function of duty cycle c
urve is
zero. This is the basis of the controller. The set point for the derivative is s
et to zero. This
controller looks at the derivative and tries to adjust the duty cycle until a de
rivative of zero is
reached. The control system will either reduce or increase the duty cycle to sli
de up and down
the V-I curve depending on the derivative. To control the rate or speed at which
the duty cycle
moves, a proportional gain, KP, is introduced. Instead of calculating the duty c
ycle based on each
sample, the difference goes to an integrator. In other words, if the controller
says to add 1%, the
output of the controller should not be 1%, but 1% plus whatever is already being
output.
Therefore, based on the description introduced, the most basic form of the syste
m is shown in
Figure 4-40.
Figure 4-40: General Continuous Controller
The plant is the solar panel. A certain duty cycle comes into the solar panel an
d a power
is outputted. The solar panel model equations predict the expected output. This
then goes to the
derivative in the feedback loop, which converts the power to a derivative dP/dDC
. This is delta
power, over delta duty cycle. The duty cycle input to the derivative block is no
t explicitly shown.
Note that this derivative dP/dDC is not in respect to time, instead with respect
to duty cycle. This
derivative is the slope of the power verse duty cycle curve shown below in Figur
e 4-41.
Figure 4-41: Power and Derivative (dP/dDC) vs. Duty Cycle
Next, the response of this type of system needs to be analyzed. To perform this
analysis,
the transfer function of the system shown in Figure 4-40 must be looked at. With
a slight reordering
of blocks, the new system is shown in Figure 4-42.
Figure 4-42: Re-arrangement of Controller
In this representation the derivative block is moved out of the feedback loop an
d added a
label for dOut and dIn. dOut is the derivative of power with respect to duty cyc
le. KSP is the
transfer function of the solar panel where the input is duty cycle and the outpu
t is power. At this
point KSP is assumed to be some constant. A closer look at the transfer function
of the solar panel
will be performed later on in this section.
Ksp
dOut =
Kp (dIn -
dOut )
(4.64)
s
The constants in equation (4.64) are set equal to some variable, A.
Ksp
A =
Kp
s.
Equation (4.64) simplifies to the following expression:
dOut =
A(dIn -
dOut ) (4.65)
The transfer function of any system is described by the output of the system div
ided by the input.
Solving for dOut/dIn provides the transfer function of Figure 4-42.
dOut A
=
(4.66)
dIn 1+
A
Plugging in the constants A into the basic transfer function in equation (4.66)
yields the
following expression.
H =
dIn
dOut =
+1
s.
1
(4.67)
SP PK K
The open loop gain of the system is simply A.
109
Ksp
A =
Kp (4.68)
s.
The point at which the curve crosses unity gain is shown by the equation
Kp .
Ksp
=
(4.69)
f0dB
2p.
In order to see how the control system reacts to the derivative signal, it is us
eful to look at
the transfer function of the open loop gain. The transfer function of the system
thus far is shown
in Figure 4-43. The gain is the power the controller has on derivatives at that
particular
frequency. The higher the gain at a specific frequency, the more the controller
can react to
changes in the derivative at that frequency. It may appear more efficient for th
e system to react
as quickly as possible to any change; this is actually not the case. Electrical
noise can interfere
and cause the system to move based on a small spike. A system that acts as a low
pass filter is
desired. Therefore the controller does not have any gain at these higher frequen
cies and they only
make a very small impact on the output of the controller. However low frequencie
s have a lot of
gain and move the output of the system a lot as shown in Figure 4-43.

Figure 4-43: Bode Plot of Open Loop Discrete Controller

The controller can control incoming derivatives whose frequency has a positive g
ain
corresponding to it. This curve can be moved up or down depending on the gain of
the controller.
The phase is useful in determining stability of the system. By looking at the ph
ase margin of the
system at the point where the gain crosses 0dB determines the stability of a sys
tem. A system
becomes unstable as this phase margin approaches 180 degrees. The phase of a con
tinuous
controller would be 90
for all frequencies. However, this system is being implemented in a
digital processor and is therefore discrete. The phase then approaches -180
due to the Nyquist
frequency. The system only has one integrator that can cause a phase shift and t
herefore are not
limited to certain gain values to keep the system stable.
4.5.1 Simulation
A simulation of this model was performed in Simulink. The model is shown in Figu
re 4-44.
Figure 4-44: Simulink Simulation Model
The model is similar to the ones presented before. The differences are that this
system is
modeled in discrete time. Therefore the integrator has been changed from a conti
nuous function
to a discrete-time function. A saturation block is also used to guarantee the sy
stem does not go
above a maximum of 1 or 100% duty cycle. The duty cycle then goes to the solar p
anel model.
The output of this is the expected derivative of the power as a function of duty
cycle. The same
point also goes to the solar panel transfer function, which outputs the power as
a function of duty
cycle. The derivative goes to the feedback loop of the controller. The three sco
pes in the model
show where some of the desired signals are located. The gain in the feedback is
a gain that is
found in our algorithm and will not be explained at this point.
Using a combination of Matlab and Simulink the transient responses of the closed
loop
system can be analyzed. Step responses and other input functions can also be app
lied to the
system to find out how the system and the plant operate. In the control setup, a
step response is
not very useful because there are no time delays in the solar panel thevenin mod
el; therefore the
output should directly follow the input signal.
Scaling Down the Thevenin Model
Scaling down the thevenin model allows for a closer simulation of the power outp
ut
achieved in lab. The scaled down thevenin model of the solar system will be used
as the plant.
The output power is related to the input duty cycle by the following equation
PAVG =
I NEG VMAX (1-
D)2 +
D(1-
D)(I MAX VMAX )
(4.70)
In the Boost Converter System Equations section, the values for INEG, IMAX, VNEG
, and
VMAX were obtained. These values were picked to make the maximum power point on
the
thevenin models V-I curve equal to the same power level on the thevenin V-I curve
. The scaled
down version of this allows the maximum power point to be about the maximum powe
r output
obtained with the light sources in lab. A simple table of values is shown in Tab
le 4.9.
50W Solar Panel
INEG = 1.2 IMAX = 6 VNEG = 0 VMAX = 24
Lab Solar Source
INEG = 0.18 IMAX = 0.9 VNEG = 0 VMAX = 24
Table 4-9: Scaled Down Thevenin Model Parameters
A duty cycle sweep of our model is shown in Figure 4-45. Notice how the maximum
power level
is no longer 50W but almost 7 watts, which is more like the power achieved in la
b.
Figure 4-45: V-I Characteristic of Scaled Down Thevenin Model
With a thevenin model of the solar cell the closed loop response can be simulate
d in
Simulink. The integrator needs a starting value otherwise the initial derivative
will be zero and
therefore the model will not do anything. A closed loop system with the scaled d
own thevenin
model as the plant is shown in Figure 4-46.
Figure 4-46: Scaled Down Thevenin Model
Figure 4-47: Power and Duty Cycle vs. Time
The proportional gain used here was 100. This is much higher than the gain that
will be
implemented in the real system due to the difference between the solar panel mod
el and this
thevenin equivalent model.
A bode plot of this system to look at the open loop gain of the system with the
solar panel
model shown in Figure 4-46. Notice the gain above zero dB is extremely low. The
system is
expected to react to only extremely low frequencies, which is a very large time
constant. Again,
this low gain is due to the thevenin solar panel model.
Figure 4-48: Bode Plot of Open Loop System
Improving the Solar Panel Model
In the end, the simulation and real-life results never matched perfectly due to
two
reasons. First the closed loop response depends very much on the accuracy of the
model of the
plant. Secondly, a decrease in signal to noise ratio makes it hard to approach t
he maximum
power point as the derivative value becomes smaller and smaller. Any noise in th
e voltage and
current sensing gives false derivatives. To improve the solar panel model, the n
on-linearity of the
solar panel must be accounted for.
Sweeping the duty cycle from 0 to 100% will show the non-linearity of the solar
panel in
the power and derivative of the power as a function of duty cycle. The power as
a function of
duty cycle can be seen in Figure 4-49.
Solar Panel Duty Cycle Sweep
0
1
2
3
4
5
6
7
8
9
0 20 40 60 80 100 120
Duty Cycle (%)
Power
(
Watts)
Figure 4-49: Solar Panel Duty Cycle Sweep
Notice this is not similar to the thevenin model shown previously. To better sim
ulate this
curve, a lookup table was generated based on the derivative values. The lookup t
able was limited
to 16 points with more points concentrated around the peak to more accurately re
present the
curve in Figure 4-49. The 16 points contained averages of the surrounding deriva
tive points. The
resulting look-up tables for the power and derivative curves as a function of du
ty cycle are
shown in Figure 4-50.
0 0.2 0.4 0.6 0.8
Lookup Table of Derivative vs Duty Cycle
Lookup Table of Power vs Duty Cycle
0
1
2
3
4
5
6
7
8
9
0 0.2 0.4 0.6 0.8 1
Duty Cycle
Power
(
Watts)
Derivative
(dP/
dD)
50
40
30
20
10
0
1
Figure 4-50: Lookup Table of Solar Panel Power and Derivative
Notice again, how this derivative model looks nothing like the linear line obtai
ned with
the thevenin model. The derivative peaks up to 40W/D in the lookup table at a du
ty cycle of
approximately 40%, which is very close to the maximum power point. In the linear
model, the
derivative is very close to zero at the maximum power point. This difference in
plant functions
could be one of the main reasons why the real-life results differ from the initi
al simulation
results.
By replacing the plants in the control system in Figure 4-46 with the look up ta
bles
generated in Figure 4-50, a closer resemblance to real-life conditions can be si
mulated. The
closed loop response of the system then changes dramatically in simulation. A pr
oportional gain
of 100 was previously used with the thevenin model. With the addition of the loo
k up tables, the
proportional gain changes to 10.
-10
-20
Duty Cycle
Figure 4-51: Simulation of Controllers Closed Loop Response
The actual system uses a proportional gain of 3, not 10 as shown above. As tempe
rature
and light conditions change, the V-I characteristic can change drastically. With
out providing
pages of extra graphs and figures, slightly higher derivative have often been se
en at lower duty
cycles then the one chosen to include in this paper. These models bring the cont
roller up to the
maximum duty cycle in a shorter amount of time, due to the derivatives extra gain
at lower duty
cycles.
Quantization Noise
With the addition of the look-up tables in the simulation model, the results sti
ll do not
match the real-life results very closely. The problem is due to the signal to no
ise ratio of the
derivative. As the derivative curve approaches the maximum power point, the deri
vative
approaches zero. Eventually, this signal falls under the quantization noise of t
he A/D sampling.
In other words, if a constant duty cycle in the input of the system, the derivat
ive output will not
be zero, but instead bouncing up and down.
The power is calculated on the PIC microcontroller by sampling the voltage and c
urrent
inputs and multiplying the two together. The voltage and current is sampled on t
he PIC with 10
bit resolution. Multiplying the voltage and current samples together obtains a p
ower with 20-bit
resolution. Due to the memory and time constraints of the PIC microprocessor, th
e sizes of the
register values have to be constantly tracked. To minimize this affect, the powe
r resolution was
dropped from a 20-bit resolution to 16-bit resolution eliminating the four least
significant bits.
Further, when the derivative is calculated, the processor uses the PWM value in
10-bit
resolution. When doing any discrete sampling and or math functions, quantization
noise is
typically a major concern.
If a voltage of 10 volts (half the maximum voltage expected) is applied to the v
oltage
sensor, then the corresponding register value for this would be 512. The resolut
ion of the A/D is
19.5mV. If the voltage level was above 10 volts, but not high enough to make a s
ample value of
513, such as a voltage 10.010 V then the A/D sample would bounce between 512 and
513. The
difference of one register value at 512 does not appear to be significant since
it is only a change
of 0.2%. However, the variation of one register value is also occurring in the c
urrent samples as
well. When the varying voltage and current values are multiplied together, the v
arying power
values are much more significant greatly. The varying power values are the main
cause of the
quantization noise in the derivative. The idea of quantization is shown in Figur
e 4-52.

!
"#

!
"# $

%&
( &
Figure 4-52: Quantization Effect on Voltage, Current, and Power
' !&&
' !&&
Calculating the derivative will demonstrate how significantly the quantization n
oise
affects the derivative signal. The derivative is calculated as follows:
Power
Derivative =
(4.71)
Duty Cycle
Power is defined to be the product of the voltage and current, both in 10-bit re
solutions,
and then shifted right 4 bits, to obtain a 16-bit power resolution. The first bi
t is the sign bit and
therefore does not hold any numeric data. As a result, this integer can be thoug
ht of as a 15 bit
signed number. To convert from derivative in watts over duty cycle to register v
alues the
following conversions can be used.
P P
REG REG
P =
.
P =
80 (4.72)
REAL 15 MAX 15
2 2
DC REG
DC REAL =
(4.73)
1024
Plugging in PREAL from equation (4.72) and DCREAL from equation (4.73) into equa
tion (4.71)
yields the following expression.
DP
REG 80
215 DP
Derivative =
=
2.5 REG (4.74)
DDC REG DDC REG
1024
The quantization noise in the derivative resulting from the voltage and current
samples
can be qualitatively expressed using the relationship between real and register
values of the
derivative in equation (4.74).
The first power sample, P1, is calculated assuming that the voltage and current
values are
both half their maximum, the corresponding voltage and current A/D samples are b
oth 512. The
power is calculated by multiplying the voltage and current samples and converted
to 16 bits by
dividing by 32.
512 .
512
P1 =
=
8192 (4.75)
32
To describe the difference in power due to the quantization noise in the voltage
and current
samples, the A/D samples are both assumed to increase by one register value to 5
13. The second
power sample, P2, is:
513 .
513
P2 =
=
8224 (4.76)
32
The difference in the two power samples is 32 rather than the quantization of 1
from the voltage
and current samples. Calculating the derivative gives more insight into the affe
ct of the
quantization noise in power. The derivative is calculated as follows.
DP P2 -
P1 8224 -
8192 32
Derivative ===
=
(4.77)
DDC DDC DDC DDC
This means that one bit change in current and voltage will create a derivative o
f 32 /
DDC. This derivative in register value equals 0.078 watts / duty cycle. This wil
l get worse as the
voltage or current moves up towards their maximum value.
A problem exists if the duty cycle does not move at all. A change in duty cycle
of zero
would create an error in the division. On the PIC however, a value of 1 results w
hen this occurs.
To eliminate this problem, an if statement is inserted to check whether or not t
he duty cycle
changed. In this case, the derivative defaults to a fixed value with the sign be
ing the last
derivatives sign. Therefore quantization can make the duty cycle falsely appear t
o not have
moved, and the derivative then has to default to some fixed value.
To test this quantization on our system, a steady duty cycle is applied to the i
nput of the
system while measured the changing voltage and current samples. This setup is sh
own in Figure
4-53.
Figure 4-53: Test Setup to Measure Quantization and Noise
The resulting voltage and current quantization noise is shown in Figures 4.54 an
d 4.55.
Note the values are in 10 bit register values.
Quantization on Voltage
838.4
838.6
838.8
839
839.2
839.4
839.6
839.8
840
840.2
1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52
Sam ple Num be r
Voltage
Register
Value
Figure 4-54: Quantization of Voltage Register
Quantization on Current
77.4
77.6
77.8
78
78.2
78.4
78.6
78.8
79
79.2
1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52
Sample Number
Current
Register
Value
Figure 4-55: Quantization on Current Register
Multiplying the voltage register and the current register produces a 20-bit numb
er. As
explained before, the power is shifted down 4 bits to acquire a 16-bit register.
The resulting
power quantization is shown in Figure 4-56.
Quantization on Pow er
2030
2035
2040
2045
2050
2055
2060
2065
2070
2075
2080
1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52
Sam ple Num be r
Product
of
V
and
I
(
16
bit
RegisterValue)
Quantization on Pow er
2030
2035
2040
2045
2050
2055
2060
2065
2070
2075
2080
1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52
Sam ple Num be r
Product
of
V
and
I
(
16
bit
RegisterValue)
Figure 4-56: Quantization of Power Register
Note the peaks in Figure 4-56 coincide with the current peaks in Figure 4-55. Th
is is
because the current values have more of a quantization effect due to their low v
alue compared to
the high voltage values. If a small value is shifted one, it gets multiplied by
the large voltage
value and creates a large difference. The voltage has much less of an affect, bu
t is still noticeable
on the graph where the power drops down slightly. The large peaks in the graph a
re 26 register
values, which correspond to 63mW whereas the voltage quantization noise is so sm
all it can be
considered insignificant. This value is close to the 78mW calculated earlier wit
h both voltage
and current registers at a value of 512.
To show the effect of quantization each value can be represented by the actual v
alue plus
the amount the values shift described in equation (4.78).

Dv

Di
Power = (V +
Dv)( I +
Di) =
V 1+
I1+

(4.78)

V .

I .
1 1
Where Dv =
and Di =
because both of the registers are 10 bit. Factoring out the V and I
210 210
and multiplying through obtains equation (4.79).

Dv Di DvDi

Power =
V .
I
1+
+
+

.
(4.79)
V IV .
I
Insignificant
When the system is in full operation, the derivative signal is a little noisier
than what was
calculated just from quantization noise alone. In Figure 4-57, a solar panel swe
ep that was done
before is shown. The coinciding derivative as a function of duty cycle is shown
in Figure 4-58.
Solar Panel Duty Cycle Sweep
0
1
2
3
4
5
6
7
8
9
0 20 40 60 80 100 120
Duty Cycle (%)
Power
(Watts)
Figure 4-57: Solar Panel Duty Cycle Sweep
Duty Cycle Sweep -Derivative
-200
-100
0
100
200
300
400
500
0 20 40 60 80 100
Duty Cycle (%)
Derivative
(RegisterValues)
Figure 4-58: Derivative of P/ DC during Solar Panel Duty Cycle Sweep
According to the simulation, a derivative is expected that starts out at zero at
a low duty
cycle, goes to a large positive value and then crosses zero at the maximum duty
cycle. The only
resemblance to a distinguishable positive duty cycle is at just below 40%. The d
erivative goes
slightly negative beyond the maximum power point, which is expected. However, th
is is much
noisier than predicted by simulation. A closer view of the section from 20% to 2
5% duty cycle is
shown in Figure 4-59.
Duty Cycle Sweep -Derivative Zoomed In
-100
-50
0
50
100
20 21 22 23 24 25
Duty Cycle (%)
Derivative
(RegisterValues)
Figure 4-59: Derivative Zoomed In
At 20%-25% duty cycle, the derivative should be largely positive. While it is cl
ear that
there are a larger number of positive derivatives than negative. However, the va
rying derivative
will slow the transient of the control system taking longer to reach the maximum
power point.
The derivative peaks range from about +60 to 40. This corresponds to about 24W/DC
and
16W/DC. This is quite high, and makes the controller make a lot of wrong decisio
ns in which
way to increment the duty cycle. However, by the transfer function of the filter
, the filter is
designed to filter out these high frequency noises. Unfortunately at this point,
the control system
could not filter out the noise enough to operate correctly. The noise floor was
so high, that as the
derivative approached zero, the signal would fall under the noise floor. There w
as a large steady
state error in the derivative that was due to the signal to noise ratio of the d
erivative dropping.
This created a steady state error. Originally instead of doing any signal proces
sing on the
derivative, the implementation of a P-I (proportional integral) controller was u
tilized to eliminate
the steady state error. This basically added a second integrator in parallel wit
h the proportional
gain. The P-I controller pushed the duty cycle past the steady state error howev
er had large slow
oscillations that seemed impossible to tune.
After exhausting all other options to decrease the noise, it was decided to impl
ement an
additional low pass filter on the derivative signal. A simple IIR filter was imp
lemented to filter
out more of the high frequencies. The IIR filter takes the current derivative sa
mple and adds it to
a derivative IIR accumulator. After the addition the accumulator variable is the
n divided by two.
This gives a decaying weighting on each derivative sample. The decaying weightin
g is infinite
until it falls under the LSB of the variables register when it can then be assum
ed to be zero. In
other words the last derivative sample is weighted with a weight of 0.5. The der
ivative sample
before that would have a weight of 0.25 and the one before that 0.16. This keeps
decreasing by a
factor of two. All the past derivative weightings add up to a total gain of 1.
The IIR filter made the system work well, however there is certainly room for
improvement. By improving this derivative signal, the system would respond to su
nlight and
temperature differences closer to what the model simulates. In other words, the
controller would
make much less wrong decisions and therefore find the maximum power point quicke
r.
The current Simulink simulation model this far is in discrete time, but is conti
nuous along
the register values. In other words the model does not quantize any values to th
e registers least
significant bit. To model this it is easier to view all the values in register v
alues and then convert
them back to real values to suit the solar panel transfer functions. This model
is shown in Figure
4-60.
Figure 4-60: Simulation adding Quantization and Register Values
125
Some gains in the system, such as the two in the feedback loop are obviously in
series
and are not combined simply to show that the gains are independent of each other
. Starting with
the feedback loop there is a 0.4 gain. This is the gain calculated earlier for c
onverting real
derivative values from the output of the solar panel function to 15 bit register
values. The next
gain is to increase the resolution of the derivative calculation and is describe
d in more detail in
the algorithm section. Next comes the quantization block. This block simply quan
tizes any
decimals to whole numbers only. Note that this still will not act as the A/D con
verter oscillates
between two values. Next the signal gets compared to our set point of a zero der
ivative and
multiplied by some proportional gain. This then gets integrated as before. To ge
t the duty cycle
in decimal form the shift 5 block divides by the maximum register value. This du
ty cycle is
stored in 15-bits and therefore it must be divided by 215. The duty cycle is the
n in decimal form
and goes to the solar panel derivative function and repeats the loop. In order t
o look at power
values in watts, a solar panel function was added which outputs power verses an
input duty
cycle.
The block diagram in Figure 4-60is how the algorithm is designed. In the beginni
ng of
this section a simpler model was presented with out a lot of these additional ga
ins. Instead, we
simply added a gain in the feedback loop and said we would explain it later. The
reason for this
gain is that the system is implemented exactly as shown in Figure 4-60. The gain
, KP, then is not
the gain of the loop. Instead it is just one of many gains in series with anothe
r. The gain of the
loop can be found by the following.
1
Open Loop Gain = 0.4 .
4 .
K P .
(4.80)
25
Therefore in the simpler model of the system the gain used in the feedback loop
was actually the
constants of this equation. KP was still shown externally.
4.6 Microprocessor
The controller will be converted from theory to an algorithm, which will be exec
uted by a
microprocessor. The design of the controller on a PC would be much simpler becau
se it is much
quicker to implement and test different control methods. However, in order to ha
ve a self-
contained system, a microprocessor was selected. To simplify programming, the us
e of a high
level language such as C is utilized instead of assembly. A C compiler by Forest
Electronic
Developments called Wiz-C was used to program the processor. By implementing thi
s C
compiler, the math functions were easier and faster to program. However, a high
level language
such as C has speed and memory constraints that give reason for concern. In orde
r to alleviate
these concerns, the registers were all limited to 16-bit numbers in order to spe
ed up the process
as well as leave plenty of room for memory. Multiplying two 16-bit numbers resul
ts in a 32-bit
number. A 32-bit number takes up 4 bytes of available bytes of RAM. Creating arr
ays of past
samples can easily use up all the available memory.
Next a general block diagram description of how the algorithm is set up is shown
in
Figure 4-61. A brief description of each block is shown on the side. Finally, th
e small details line
by line in code lies in the comments found in the C file in Appendix C. When the
processor is
first turned on, it will be initialized to set all the registers and functions.
During this initialization
it will configure Timer 1 to 26.2mS. This timer counts down to zero and on zero
an interrupt
occurs. This interrupt will trigger the entire sampling algorithm and then the c
ontrol algorithm.
The algorithm is set up as shown in Figure 4-61.

26mS Timer 1 interrupt

Samples voltage and current values in 10bit

Samples voltage and current values 4
times before moving on to the control
algorithm

Stop timer 1 because the rest of the
algorithm will not run before a new
interrupt occurs

Delay to wait for the slow current sensor
transient

Average 4 voltage samples and 4 current
samples into a 16-bit value


Control algorithm takes in voltage and
current sample and computes new PWM
signal
Output PWM signal to boost converter

Output any data via serial port to capture
on PC

Turn Timer 1 back on to repeat
Figure 4-61: Block Diagram of Algorithm for Microprocessors Controller
Initialization
The first step in initialization is setting up the PWM module. To do this, the f
requency
and the maximum resolution for this particular frequency are set. The block diag
ram of the PWM
module is shown in Figure 4-62.
Figure 4-62: PWM Module Block Diagram
The PWM module operates by having a counter run down on Timer 2, denoted by
TMR2. Timer 2 starts at the value defined by PR2. Adjusting Timer 2 or PR2 will
adjust the
frequency of the PWM. Once the timer is equal to the 10-bit word stored in the r
egister CCPR1H
and CCPRIL the timer will reset and flip the flip-flop.
The period of the PWM module is given by equation (4.81).
PWM Period =
[(P )+1].
4 T .
(TMR 2 Pr escale Timer ) (4.81)
R2 OSC
The PWM frequency is designated to be 80 kHz in the Operating Frequency section.
The period
of 80 kHz is 12.5mS. Timer 2 pre-scale value is set to be 1. TOSC is 1/FOSC. FOS
C is 20 MHz;
therefore TOSC is 5 x 10-8. Using equation (4.81), PR2 is equal to 61.5. PR@ is
rounded up to a
value of 62 because it is not possible to put 61.5 into a register. A 62 decimal
is equivalent to 3E
hex. Next the resolution of the PWM will be solved. This is necessary because th
e PWM output
must be scaled to this resolution for it to output correctly. The PWM resolution
is shown by
equation (4.82).

FOSC
log .

F

PWM
PWM Resolution =
bits (4.82)
log(2)
FOSC is 20 MHz, FPWM is 80 kHz. Solving the equation the PWM resolution is found
to be
7.9657. This is a hard number to scale by. It is almost 8-bit which is an easy s
cale factor simply
by shifting the digits left or right. Therefore, solving for FPWM when the PWM r
esolution is 8
bits, obtains an operating frequency of 78.12 kHz. Re-doing the PWM period calcu
lation, PR2
should be 63 hex instead of 62. The pre-scalar remains the same at 1. To convert
to 8-bit PWM
resolution, the 10-bit number on the output of the controller needs to be shifte
d two bits to the
right.
Next the A/D module needs to be initialized. First the bi-directional ports need
to be set
to inputs. Next, port A needs to be set to accept analog inputs instead of digit
al. Figure 4-63 is an
excerpt from the PIC microprocessor data sheet.
Figure 4-63: A/D Module Port Selection
Earlier channel 1 and channel 3 was chosen for the voltage and current inputs. T
herefore
a column needs to be selected from the table above where AN1 and AN3 are specifi
ed as A, or
analog inputs. The fourth row down is chosen, because of the fact that both AN1
and AN3 are
analog inputs and that it needs no additional VREF+ or VREF-beyond the rails of
the processor.
Therefore the PCFG is set to 0100 binary or 04 hex. The A/D module also needs to
be set to right
or left justify the 10 bits in the two 8-bit registers ADERSH and ADERSL as show
n in Figure 464
from the datasheet.
Figure 4-64: A/D Result Right Justified in 16-bit Register
It does not matter which way the 10-bit result is justified as long as the algor
ithm
correctly accesses it in its right location later. Lastly, the A/D converter is
turned on.
Next Timer 1 is set up to trigger an interrupt every 26.2mS. Timer 1s block diagr
am
taken from the data sheet is shown in Figure 4-65.
Figure 4-65: Timer 1 Block Diagram
The FOSC/4 clock is used, as an external clock to synchronize the timer is undes
irable,
therefore the TMR1CS bit is set low. Next a pre-scalar of 1 is chosen. This then
bypasses the
synchronization block and goes to the AND gate. The AND gate simply turns the ti
mer on or off.
The timer starts with the value given in the 16-bit word TMR1H:TMR1L. The timer
will
overflow on the next clock cycle after FFFF hex causing an interrupt. The interr
upt routine is
then called which parses through the interrupt table determining which device ca
used the
interrupt.
Now that all the modules have been initialized, Timer 1 is immediately running.
After the
first 26.2mS an interrupt is triggered. This calls the voltage and current sampl
ing routine. This
routine is fairly simple. It takes the voltage sample and current sample separat
ely and places
them in a 4-position single dimension array, incrementing the array pointer each
time. The
routine then either quits and the program waits for the next interrupt or after
the 4th placement,
the function allows the delay routine to be called. This routine runs a delay lo
op for 100mS
simply waiting for the long current sensor transient. After this delay the algor
ithm is ready to
average the 4 samples of voltage and current together. This routine is also quic
k and easy,
however, the first sign of extensive memory usage is seen. This routine will tak
e the average of
the 4 samples by adding them together and dividing by four. Each sample is store
d in a 16-bit
register, therefore it has to add 4 16-bit registers and divide by 4. Fortunatel
y the divide by four
is a simple bit wise left shift by two bits. This is why 4 samples are chosen as
opposed to 3 or 5.
4.6.1 Algorithm
The algorithm that controls the duty cycle was programmed in a C compiler. The
algorithm for the controller is outlined below.
1.
Save last power sample
Copy current power sample to a saved location in order to keep the last sample.
Power is a 15-bit value.
2.
Save last derivative value
Copy current derivative value to a saved location in order to keep the last valu
e.
Derivative is a 16-bit value with sign.
3. Calculate power from product of voltage and current
Voltage and current are held in a 16-bit register value. These need to get cast
to a
temporary 32-bit variable, multiplied together and then shifted back to 16-bit a
nd stored
in the power array.
4. Calculate Power Difference between current power value and last value.
Power Difference = Current Power Sample Saved Power Sample
Power difference is a 16-bit signed integer.
5. Calculate Duty Cycle Difference between current duty cycle value and last val
ue.
DC Difference = Current DC value Saved DC value
DC difference is a 16-bit signed integer.
6. Calculate Derivative
Power Difference
Derivative is calculated by Derivative=
. Power difference is a 16-bit
DC Difference
value, however the MSB is the sign bit. Therefore the numerical number is held i
n 15
bits. The duty cycle is held in a 16-bit register, again with the MSB being a si
gn bit.
Therefore this is dividing two 15-bit registers with signs. However, the maximum

resolution of the PWM is 10-bit and is what the controller was designed for, eve
n though
our PWM is actually 8-bit. Therefore shifting the denominator 5 bits to the righ
t to make
an 11-bit signed duty cycle difference is required. An extra gain of 4 in the nu
merator is
also presented. This extra multiplication is done before the division to increas
e the
accuracy of the calculation. This is why what seems like a random gain of 4 is i
ncluded in
the complete Simulink simulation.
7.
IIR Filter
The IIR filter is implemented. By simply adding the current derivative to the II
R filter
accumulator and dividing by 2 a simple infinite impulse filter is created. The o
utput is
then saved in the derivative variable.
8.
Save Duty Cycle value
Copy the current duty cycle (which has not been over-written yet) to a saved loc
ation to
keep the last value. This is saved as a 15-bit value.
9.
Proportional Gain
Multiply the derivative value by the proportional gain as defined by the control
ler design.
10.
Check if the duty cycle did not move enough to calculate a derivative
If the derivative of the system is zero, then the duty cycle will not change. Th
erefore if
the duty cycle does not change, the system never moves. To prevent this from hap
pening
if else checks were implemented. If the numerator is zero then the derivative wi
ll be zero
and the duty cycle will never change. This is actually allowed to happen because
of the
check on the denominator. The denominator is the duty cycle difference. If the d
uty cycle
is zero, the derivative before the one just calculated to see if it was positive
or negative is
looked at. Then force the derivative to a fixed value with the sign being the sa
me as the
last derivative. This guarantees the duty cycle always changes and never gets st
uck as the
derivative goes to zero. Therefore if the power diff is zero then the derivative
will be
zero. This is allowed the first time. When the derivative is zero, the duty cycl
e does not
change. Therefore the next time the controller algorithm is called, the program
notices the
duty cycle did not move and forces the duty cycle either positive or negative de
pending
on the sign of the last derivative that was valid.
11.
Check if duty cycle register rolled over or under.
The last thing the control algorithm does is check that the duty cycle is not ro
lling around
creating overflows. While this should never happen, it is just a safety check. I
f the duty
cycle goes up to 100% the program is never allowed to add any more to this maxim
um
duty cycle. The same is true for rolling backwards from 0%.
After the control algorithm completes, some of the variables contents are dumped
over
the RS232 port. To do this a pre-built SDK function is called that converts a he
xadecimal
number to ASCII characters. Then another pre-built SDK function is called that s
ends each
character one at a time. The format is as follows
Duty Cycle Register <space> Power Register <space> Voltage <space> Current <spac
e>
Derivative <CR> <LF>
4.7 Self Powering
4.7.1 24-Volt Supply
The instrumentation amplifier requires a 24 volt supply due to the high common m
ode of
voltages at the inputs of the AD627. This supply will come directly from the 24
volt battery
source. However, while charging the battery the actual voltage of the battery os
cillates forcing
the output of the AD627 to oscillate. Figure 4-66 shows the voltage waveform ove
r the battery
while the MPPT is in operation.
Figure 4-66: Battery Voltage Waveform
The AC portion of the battery voltage is only shown to better demonstrate and vi
ew the rippling
waveform of the battery voltage. In Figure 4-66, when the duty cycle goes low, c
harge is being
pumped into the battery causing the voltage to shift up and slowly decrease whil
e the duty cycle
remains low. The slow decrease in voltage is proportional to the decreasing curr
ent flowing into
the battery, which is due to the inductor. The battery voltage ripples approxima
tely 100mV. A
100mV is insignificant to some applications. However, a 100mV ripple on a power
supply rail
will cause major problems to devices that are powered by this noisy rail.
Inserting a simple RC filter off of the battery to the supply rail of the AD627
will provide
a constant 24 volt supply to the instrumentation amplifier as shown in Figure 4-
67.
Figure 4-67: 24-Volt Supply Filter
We came up with a general requirement that we wanted a ripple of about 1mV at th
e output of
the RC filter to supply the AD627. With a 100mV input, the voltage drop over the
resistor is
approximately 100mV. The AD627 is specified to draw 86 A so the resistance is def
ined to be:
V 100 m
R ==
=
1.16 k.
I 86
A more practical resistance of 1k.
is used for the filter. The transfer function of the RC filter
will help determine the approximate capacitance required to have a 1mV ripple at
80 kHz.
V 1
H =
OUT =
(4.82)
VIN 2pfRC
The input voltage is 100mV, the frequency is 80 kHz, and the resistance is 1k. Wi
th a desired
output of 1mV, the capacitance is calculated to be 0.199 F. The closes capacitanc
e value to
0.199 F is 0.1 F. With these resistance and capacitance values, the output will be
34dB down
from the input, which is plenty of filtering to filter out the rippling waveform
of the battery
voltage. At 80 kHz, 1mV waveform should be expected at the output of the filter.
The output of
the capacitance is shown in Figure 4-68.
Figure 4-68: 24-Volt Battery Supply
In Figure 4-68, the battery voltage is filtered down to a 4.8mV rippling wavefor
m. The variation
is due to the difference of capacitance value used as compared to the calculated
as well as
tolerances of the capacitance and resistance and the small noise in the system.
However, a
4.8mV ripple is small enough to properly supply the AD627 instrumentation amplif
ier without
causing any errors in the device.
4.7.2 5-Volt Supply
Generating a 5-volt supply for the instrumentation amplifier and MOSFET driver w
as
straightforward using the LM78L05. The LM78L05 outputs 5-volts DC as long as the
input is
above 6.7 volts. A capacitor is connected to the input and output pins of the vo
ltage regulator in
order to settle the voltages as specified by the data sheet of the LM78L05. The
battery voltage
waveform going to the input pin of the LM78L05 is shown in Figure 4-69.
Figure 4-69: Battery Voltage Waveform
The datasheet suggest the use of a 0.33F on the input if the regulator is located
more than 3
inches from the power supply filter. It also suggests the use of at least a 0.1F
capacitance to
limit the high frequency noise at the output. The actual values used in the volt
age regulators
implementation were both 1F capacitors because the values had to be at least the
suggested
values in the datasheet. The voltage waveform at the output pin of the voltage r
egulator is shown
in Figure 4-70.
Figure 4-70: 5-Volt Supply Waveform
The output voltage is biased at +5 volts with a barely visible ripple waveform.
Since the output
of the voltage regulator is supplies the MOSFET driver and the reference pin of
the
instrumentation amplifier with 5 volts, than the ripple of the waveform must be
small. The
configuration for the 5-volt supply can be seen in Figure 4-71.
Figure 4-71: Voltage Regulator Configuration
5.0 Power Loss Analysis
5.1 Operating Losses
The operating power loss associated with the MPPT system pertains to the MOSFET
losses, inductance losses, and the losses due to the rippling of the current and
voltage waveforms.
All of these losses were derived in order to select the appropriate MOSFET, indu
ctance, and
operating frequency that would provide the most efficient results for the MPPT.
These equations
are derived in the MOSFET and Inductance Selection sections.
The power losses in the MOSFET are due to the current flowing through the intern
al
resistance, rDS, the charging and discharging of the gate to source capacitance,
and the rise and
fall times of the MOSFET. The power loss through rDS is not dependant on frequen
cy and
remains constant. This relationship can be seen in the equation below:
P =
I 2r (5.1)
rDS DS
Where I is 3.3 amps due to the current flowing from the 50 watt output of the so
lar panel and rDS
is specified by the data sheet of the IRL7833 MOSFET, which is 4.5m. The power lo
ss
associated with the gate to source capacitance of the IRL7833 depends on how oft
en the
capacitor charges and discharges, and the amount of charge required to fill the
capacitor. This
relationship is described in the equation below:
P =
QV f (5.2)
CGS GS GS
Where QGS is specified to be 32nC by the data sheet of the IRL833, the VGS volts
is specified to
be 5 volts, and this power loss increases as a function of frequency. As MOSFET
switches from
on to off and off to on, there is a power loss associated with the time it takes
for the current to
rise and the voltage to fall. This relationship can be described in the equation
below:
(trise +
t fall )VDS If
rise (5.3)
P -
fall =
2
The voltage drop over the MOSFET, VDS, is equivalent to the battery voltage (24
volts), trise
(6.9ns) and tfall (50ns) are specified by the data sheet and I is 3.3 amps due t
o the 50 watt output
of the solar panel. Summing the three power losses gives the total power loss du
e to the
MOSFET.
PMOS =
PrDS +
PCGS +
Prise -
fall (5.4)
2 (trise +
t fall )VDS If
PMOS =
I rDS +
QGS VGS f +
(5.5)
2
As the operating frequency of the system increases, the power loss due to the MO
SFET
increases.
The losses through the inductor are due to the current flowing through the inter
nal
resistance of the inductor. However, due to the functionality of the boost conve
rter, the current
flowing through the inductance ripples. Due to the relationship P=IV, a larger r
ippling current
results in a larger power loss. The power loss through the internal resistance o
f the inductor is
described below.
RL DI 2
2
PIND =
+
I RL (5.6)
12
Where, RL is specified by the manufacturer of the inductor, I is 3.3 amps, and I
is inversely
proportional to the frequency and derived in the Boost Converter System Equation
s section. As
the frequency of the system decreases, the larger the rippling current becomes r
esulting in a
larger power loss.
The final power loss associated with the operating losses of the system is due t
o the
rippling of the current and voltage off of the maximum power point of the system
. Due to the
relationship:
dI
VL =
L (5.7)
dt
As the current increases the voltage will decrease and vice versa. The point whe
re the two
waveforms intersect when superimposed is the point where there is maximum power.
The larger
the rippling voltage and current waveforms are, the larger the power loss is. Th
is power loss is
described by the equation below:
DVDI
=
Pripple 8
(5.8)
I and V are both described in the Boost Converter System Equations and are both in
versely
proportional to the frequency indicating that the power loss of the system incre
ases as the
frequency decreases.
The total operating power loss becomes the sum of the MOSFET losses, the inducta
nce
losses, and the rippling losses.
P =
P +
P +
P (5.9)
OL MOS IND ripple
2
(t +
t )V If R DI DVDI
2 rise fall DS L 2
P =
I r +
Q V f +
+
+
I R +
(5.10)
OL DS GS GS L
2 12 8
Figure 5-1 was obtained describing the overall power loss due to the operating l
osses of the
system using equation (5.10).
Figure 5-1: Operating Power Losses
At an operating frequency of 80 kHz, the operating power loss is approximately 0
.8 watts.
5.2 Diode Losses
The power loss through the diode is related to the voltage drop over the diode a
nd the
current flowing through it. Due to the MOSFET switching on and off, current will
never be
flowing through the diode continuously. Rather current will only flow through th
e diode when
the MOSFET switch is off or open making the exact power loss through the diode d
ependant on
the duty cycle of the PWM signal generated by the microprocessor, which can be s
een in Figure
5-2.
Figure 5-2: Simple Boost Converter Circuit
When the duty cycle is high, the MOSFET switch is open allowing no current to fl
ow through
the diode and vice versa. The following formula describes the power loss through
the diode.
P =
V I (1 -
D)
(5.11)
Diode D
VD is the voltage drop over the diode, I is the average current flowing from the
solar panel, and
(1-D) represents the percentage of time in which the MOSFET switch is off forcin
g current
through the diode. Since the power loss analysis of the system is relative to a
50 Watt output for
the solar panel, the average current flowing through the system is expected to b
e 3.3 amps.
Specified by the data sheet of the diode, the voltage drop over the diode in for
ward bias mode is
0.55 volts. With the current and voltage drop over the diode specified as consta
nt values, the
power loss of the diode becomes a function of duty cycle. Figure 5-3 demonstrate
s the power
loss of the diode as a function of duty cycle.
Figure 5-3: Diode Power Loss vs. Duty Cycle
The actual duty cycle of the system at depends entirely on where the maximum pow
er point of
the system occurs. The maximum power point will occur at a duty cycle somewhere
between
zero and 100 percent, rather somewhere in the middle. As a result, a duty cycle
of 50% is
assumed to describe the point where the maximum power is obtained with a 50 watt
output from
the solar panel. The power loss through the diode simply becomes:
P =
V I (1 -
D)
=
0.55 .
3.3 .
0.5 =
0.91 watts (5.12)
Diode D
The power loss through the diode with a 50 watt output from the solar panel is e
xpected to be
approximately 0.91 watts.
5.3 IC Losses
The IC losses of the system are due to the amount of power drained by the integr
ated
circuits in the circuitry. The PIC (PIC16F873A), the voltage regulator (LM78L05)
, the
instrumentation amplifier (AD627), and the MOSFET driver (TC428) all contribute
to the IC
losses of the system. Each device requires a certain amount of power in order to
keep the device
powered on.
The power consumed by the PIC varies depending on the oscillator frequency runni
ng the
device. Figure 5-4 is located in the data sheet of the PIC16F873A and describes
the amount of
current drawn by the PIC to keep the device powered depending on the oscillator
frequency and
the supply voltage.
Figure 5-4: PIC16F873A Current Consumption
The higher the oscillator frequency and supply voltage of the PIC, the more curr
ent that the PIC
draws. The frequency oscillator for the PIC is 20MHz with a supply voltage of 5
volts. From
these values, the figure above indicates that the PIC draws a current of approxi
mately 5.5mA.
Knowing the current and voltage drawn by the PIC, the power consumption is deter
mined using
ohms law.
P =
VI =
(5)(5.5m)
=
27.5mW (5.13)
With an oscillator frequency of 20 MHz at a supply voltage of 5 volts, the PIC16
F873A
consumes a power of approximately 27.5mW.
The voltage regulator (LM78L05) consumes power due to the drop of 24 volts down
to 5
volts. The current drawn through the voltage regulator remains constant and depe
ndant on the
two devices pulling current through the voltage regulator. The PIC and MOSFET Dr
iver both
require 5 volt supplies, so the current flowing through the voltage regulator si
mply becomes the
sum of the current drawn by both devices.
I =
I +
I =
5.5m +
8.0m =13.5mA (5.14)
VR PIC TC 428
The current flowing through the voltage regulator is 13.5mA. The power consumed
by the
voltage regulator becomes the difference between the power going into the voltag
e regulator and
the power going out.
PVR =
PIN -
POUT =
VIN I -
VOUT I =
I (VIN -
VOUT )
(5.15)
PVR =13.5m(24 -
5)
=
256.5mW
The power consumed by the voltage regulator is due to the huge voltage drop from
24 volts
down to 5 volts. This results in a power loss of 256.5mW.
The power consumed by the instrumentation amplifier (AD627) and the MOSFET Drive
r
(TC428) are determined through the use of ohms law. The instrumentation amplifier
draws a
maximum current of 86 A as specified by the data sheet of the AD627 instrumentati
on amplifier
while being supplied with a voltage of 24 volts. The MOSFET Driver is supplied w
ith 5 volts
while drawing a maximum current of 8mA. Through ohms law:
PAD 627 =
VI =
(24 )(86 m)
=
2.06 mW (5.16)
PTC 428 =
VI =
(5)(8m)
=
40.0mW (5.17)
The power loss associated with the instrumentation amplifier (AD627) is approxim
ately
2.06mW, whereas the power loss of the MOSFET Driver (TC428) is approximately 40m
W.
The total IC losses of the system simply become the sum of all of power consumed
by the
IC devices in the system.
=
P +
PIC PPIC +
PVR +
AD 627 PTC 428 (5.18)
=
27.5m +
256.5m +
2.06 m +
40.0m =
326.1mW
PIC
The total IC losses due to PIC (PIC16F873A), the voltage regulator (LM78L05), th
e
instrumentation amplifier (AD627), and the MOSFET Driver (TC428) is approximatel
y
326.1mW.
5.4 Overall MPPT Efficiency
The overall efficiency of the system is determined by the amount of power consum
ed by
the circuit with respect to the amount of power generated by the solar panel. Th
e power losses
due to the operating losses, the diode losses, and the IC losses are all determi
ned with the
assumption that the solar panel is generating 50 Watts of power.
The total power loss of the system becomes the sum of all three major power loss
es in the
system.
P =
P +
P +
P (5.19)
LOSS OL Diode IC
The operating losses of the system, POL, are 0.8 Watts due to an operating frequ
ency of 80 kHz
with the IRL7833 MOSFET and a 220 H inductor. The power loss due to the diode, PD
iode, is
0.9 Watts at a duty cycle of 50% and a voltage drop of 0.55 volts over the diode
. The IC power
loss is 326.1mW due to the amount of power consumed by the IC devices in the sys
tem.
=
0.8 +
0.91 +
0.326 =
2.04 Watts
PLOSS
The total power loss in the system is 2.04 Watts.
The overall efficiency of any device can be defined by the output power of the s
ystem
over the input power of the system.
POUT
l=
(5.20)
PIN
The output power, POUT, is simply the input power, PIN, reduced by the power los
s in the system,
PLOSS. The above equation becomes:
P -
P 50 -
2.04
IN LOSS
l=
=
=
0.959 (5.21)
PIN 50
With a power loss of 2.04 Watts with an input power of 50 Watts, the efficiency
of the system
becomes 95.9%.
6.0 Results
This section includes the analysis of the operation of the MPPT system. The over
all goal
of this project is to efficiently track the maximum power point of the solar pan
el. The sun
intensity, angle, and ambient conditions during any given day define the locatio
n of the
maximum power point. Any changes in sun intensity and other conditions that caus
e the
maximum power point to move are expected to occur very slowly. The use of a thev
enin
equivalent source, indoor lighting on the solar panel, and outdoor testing will
prove that the
control system precisely tracks the maximum power point.
6.1 Thevenin Equivalent
The use of a thevenin equivalent source in place of the solar panel isolates the
test of the
control system from the nonlinearity and complications associated with the semic
onductor
physics of the solar panel. The set up shown in Figure 6-1 was used to test the
control system
with a thevenin equivalent source.
Figure 6-1: Thevenin Equivalent Source
In the Boost Converter System equations section, the thevenin equivalent voltage
is 30 volts with
a thevenin resistance of 5.
in order to obtain a maximum power of approximately 50 watts to
match the maximum power of the solar panel. However, the voltage sensor is desig
ned to handle
a maximum of 20 volts in order to prevent any damage to the PIC. As a result, th
e thevenin
voltage is specified to 20 volts. Due to the amount of wattage the thevenin resi
stors are required
to handle with the thevenin equivalent, power resistors are required. Due to the
limitations of
our particular power supplies, the maximum current achievable is 2.5 amps. As a
result, the
power resistors must be able to handle a power of 50 watts. The closest thevenin
resistance
achievable with this power requirement is 6.
Since the thevenin equivalent source is a much more simplistic source than the s
olar
panel, the control system should find it relatively easy to find the maximum pow
er point.
Performing a duty cycle sweep from zero to 100 percent calculating the current,
voltage, and
power every 0.1%, will give enough insight to determine what the maximum power i
s and what
duty cycle the maximum power is located at. As the duty cycle increases from zer
o percent, the
current should linearly increase due to the thevenin equivalent source. Due to t
he inductance in
the boost converter circuitry, the voltage should decrease linearly with linearl
y increasing
current. This can be seen in Figure 6-2.
Figure 6-2: Thevenin Voltage and Current vs. Duty Cycle
Between 20 and 80%, both the current and voltage increase and decrease linearly
as expected. If
the solar panel were connected, these curves would be non-linear causing non-lin
earity in the V-I
characteristic increasing the difficulty for the controller to locating the maxi
mum power point.
However, since both the voltage and current are linear and the thevenin voltage
source is a linear
source, the V-I characteristic should be relatively linear. This can be seen in
Figure 6-3.
Figure 6-3: Thevenin V-I Characteristic
As predicted, the V-I characteristic of the thevenin source is linear. Due to th
e linear V-I
characteristic, the power versus duty cycle from the duty cycle sweep should dem
onstrate a very
clean and well-behaved inverted parabola. This can be seen in Figure 6-4.
Figure 6-4: Thevenin Power vs. Duty Cycle
The power vs. duty cycle curve is a very well behaved inverted parabola as expec
ted above a
duty cycle of 20%. The difficulty in the controller at duty cycles lower than 20
% duty cycle seen
in the voltage and current vs. duty cycle curves is also seen in the power vs. d
uty cycle curve.
However, this phenomenon does not affect the overall functionality of the contro
l system. As
indicated by the figure above, the maximum power of approximately 21 watts occur
s at a duty
cycle of around 64%. Due to the wide and clean shape of the peak of the parabola
in the figure
above, small deviations in duty cycle off of the peak value will result in very
small drops in
power away from the maximum power point.
The control system operates by changing the duty cycle depending on the derivati
ve of
the curve in the power vs. duty cycle figure above. Since the power vs. duty cyc
le curve is so
well behaved, the control system should be able to locate the maximum power poin
t and remain
very close to within the maximum power point deviating minimally. Closing the co
ntrol loop
and allowing the control system to locate the maximum power point with an initia
l start of 25%
duty cycle, Figure 6-5 was generated. Note that the control system was not tuned
for the
thevenin equivalent. Instead we simply used the same parameters we found for the
solar panel.
Figure 6-5: Control Loop Thevenin Duty Cycle
Due to the linearity of the thevenin source, the control system takes approximat
ely 40 seconds to
reach the maximum power point. The oscillations about the 64% maximum power poin
t, range
anywhere from zero to 5% off of the maximum power point. The circled portion of
the graph
highlights one of the locations where the duty cycle deviates off by 4% from the
maximum
power point. However, due to the large power output of the thevenin equivalent s
ource, these
deviations should not be very noticeable. This can be seen in Figure 6-6.
Figure 6-6: Control Loop Thevenin Power
The highlighted section of Figure 6-6 indicates where the duty cycle deviates of
f of the
maximum power point. Due to the peak of the power vs. duty cycle curve being wid
e, the small
deviation in duty cycle results in a very small decrease in power. The power dro
ps
approximately 0.1 volts off of the 21-volt maximum power indicated in the figure
above,
resulting in a drop of 0.5% that lasts for no more than 5 seconds in length. The
most noticeable
detail in the figure above is how cleanly the control system is operating around
the maximum
power point. With the control system locating the maximum power point of a linea
r thevenin
equivalent source producing results as accurately as indicated above, the contro
l system should
function very well when a solar panel source is attached. Another noticeable poi
nt is the slight
increasing power over time. This is because of the slight decrease in resistance
of the power
resistors due to their temperature increasing resulting in an increase in power.

6.2 Indoor Testing
The indoor testing included the use of two light bulbs that illuminated the sola
r panel
with 700 Watts worth of light. A 200W and 500W photoflood light were used to pro
vide the
solar panel with enough illumination in order to achieve a relatively high power
output from the
solar panel. The configuration for this test is shown in Figure 6-7.
Figure 6-7: Indoor Solar Panel Testing Set-up
The power output of the solar panel is highly unpredictable because the output p
ower depends on
the light intensity, angle, temperature of the solar panel, along with many othe
r ambient
conditions. The only true way to determine the maximum power output possible is
by sweeping
the duty cycle of the system. To generate a duty cycle (DC) sweep of the system,
the PIC is
programmed to sweep the duty cycle from zero to 100%, calculating the power, vol
tage, and
current outputs of the solar panel at every 0.1%. At zero percent duty cycle, th
e current is at a
minimum while the voltage is at a maximum. Due to the voltage to current relatio
nship of the
dI
inductor, VL =
L , as the duty cycle increases allowing more current to flow, the voltage will
dt
decrease. This scenario can be visualized in Figure 6-8.
Figure 6-8: Duty Cycle (DC) Sweep of Voltage and Current
The current increases as expected and the voltage decreases as the duty cycle in
creases. The
voltage appears to be linear much like the thevenin equivalent source. However,
the current
definitely indicates non-linearity as expected from the solar panel. This will r
esult in a nonlinear
V-I characteristic as shown in Figure 6-9.
Figure 6-9: Indoor Solar Panel V-I Characteristic
Due to the nonlinear V-I characteristic of the solar panel, the power vs. duty c
ycle curve will no
longer be a nice well behaved inverted parabola as seen with the thevenin equiva
lent source. As
a result, the control system will have some more difficulty in locating the maxi
mum power point.
The maximum power point can be more clearly seen in the DC sweep of the power sh
own in
Figure 6-10.
Figure 6-10: Duty Cycle (DC) Sweep of Power
One major difference between the thevenin equivalent source and the solar panel
source is the
peaks of the power versus duty cycle curves. The peak for the solar panel source
is much
sharper than the thevenin equivalent source. As a result, there is a greater cha
nce when operating
at the maximum power point of the solar panel that the control system jumps off
of the
maximum power point. The maximum power point of the system occurs at a duty cycl
e of
approximately 41% as expected. The maximum power output of the solar panel with
two light
bulbs of 700 watts shinning on the solar panel is 7.6 watts.
The idea of the Solar Panel Peak Power Tracking is to find the duty cycle where
the
maximum power point occurs, which is 41% in this case. The initial duty cycle of
the control
system starts at 20%. From this point, the control system will recognize that th
e slope of the
power vs. duty cycle is not zero indicating that the power is not at a maximum a
nd slowly ramp
up until the derivative finally reaches zero. The control loop will detect the m
aximum power
point at approximately 41% and begin to oscillate around this point as shown in
Figure 6-11.
Figure 6-11: Solar Panel Control Loop Duty Cycle
In the first few points after start, the control system is unaware which way to
start shifting the
duty cycle. After a few points, the control system has enough information in ord
er to send the
duty cycle in the proper direction in order to reach the maximum power point. Th
e duty cycle
reaches the maximum power point at 41% after about 32 seconds. The oscillations
are about the
same as the thevenin equivalent source. However, due to the sharper peak on the
power vs. duty
cycle curve, the power should drop more so than with the thevenin equivalent sou
rce. At about
250 seconds, the duty cycle jumps off the maximum power point slightly up to 45%
. However,
small changes in duty cycle of approximately 2% or 3% cause very little changes
in maximum
power, which can be seen in Figure 6-12.
Figure 6-12: Solar Panel Control Loop Power
As the duty cycle oscillates around 41%, the changes in power output from the so
lar panel are
minor. At 250 seconds, when the control system loses the maximum power point bri
efly
reaching a duty cycle of 45%. The power difference at this point is 200mW, which
corresponds
to a 2.6% loss in power when the maximum power is 7.7 watts and lasts for a shor
t period of 5
seconds. This drop in power is about twice as large as the drop in the same shif
t in duty cycle for
the thevenin equivalent source. However, the peak of the power vs. duty cycle cu
rve is much
sharper for the solar panel, which will result in the larger drop in power. Over
a 500 second
period, the power very rarely jumps off the maximum power point proving that the
control
system works extremely well.
The reason for these small errors is due to the controller acting upon false der
ivatives as
explained in the Control section 4.5. When generating the duty cycle sweep as sh
own in Figure
6-10, Figure 6-13 was also generated showing the derivative as a function of dut
y cycle.
Duty Cycle Sweep -Derivative
-200
-100
0
100
200
300
400
500
0 20 40 60 80 100
Duty Cycle (%)
Derivative
(RegisterValues)
Duty Cycle Sweep -Derivative
-200
-100
0
100
200
300
400
500
0 20 40 60 80 100
Duty Cycle (%)
Derivative
(RegisterValues)
Figure 6-13: Derivative Values vs. Duty Cycle Sweep
Note how the derivative passes through the zero derivatives very commonly. This
is a very noisy
derivative that the controller operates on. However, due to the low pass transfe
r function of the
controller, the controller is able to distinguish between these high frequency c
hanges and
disregard them. This derivative is due to the fact that the derivatives signal to
noise ratio drops
below a ratio where the controller can distinguish the derivative signal from qu
antization and
electrical noise. While the derivative signal looks very noisy on the graph, the
controller still
deals with it well and find the maximum power point.
These tests were performed numerous times in order to examine the reliability of
the
control system. All of the tests showed similar results as the one shown above p
roving the
control system to be reliable and precise. With a larger output power from the s
olar panel, this
small deviation off of the maximum power point will be less significant as indic
ated by the
thevenin equivalent source results.
6.3 Outdoor Testing
The one major problem with performing outdoor testing is the inability to contro
l the test
conditions. The output power is completely dependant on how direct the sunlight
is at that time
of day, the angle in which the solar panel is aimed at the sun, the temperature
of the solar panel,
and the visibility level of the sky. As a result, it is very difficult to accura
tely determine the
maximum power and its operating point. However, the thevenin equivalent source a
nd the
indoor solar panel tests provide enough information proving that the control sys
tem does find the
maximum power point. The outdoor testing demonstrates that the maximum power and
its
operating point shifts due to different lighting conditions. It also proves that
the transient of the
control system is fast enough to remain at the maximum operating point as the po
wer decreases
due to the sun dropping to the horizon.
Performing a duty cycle (DC) sweep of the power indicates the maximum power able
to
flow from the system and its optimal operating point. This specific test was per
formed in the
early afternoon hours. This DC sweep is shown in Figure 6-14.
Figure 6-14: Outdoor Power vs. Duty Cycle
Superimposed in the figure above is the power vs. duty cycle curve from the indo
or testing. By
superimposing the two DC sweeps on to the same graph, it becomes visible that th
e maximum
power and its optimal operating point shifts depending on the amount of light en
ergy striking the
panel. When placing the solar panel outside the amount of power output increases
by
approximately 20 watts, while shifting the optimal operating duty cycle from 41%
up to 55%.
One noticeable glitch in the power vs. duty cycle curve for outdoor testing is t
he portion
of the curve that is highlighted by the circle. At this point the power does not
change along with
the duty cycle indicating that either the voltage or current is remaining consta
nt as duty cycle
increases causing the derivative of the power vs. duty cycle curve to be zero at
a point other than
the maximum power point. This can be seen in Figure 6-15.
Figure 6-15: Outdoor Current and Voltage vs. Duty Cycle
The relative behavior of both the voltage and current curves vs. duty cycle show
a behavior as
expected. The voltage decreases with increasing duty cycle and the current incre
ases. However,
the current does not increase as the duty cycle increases for a brief period aro
und 40%, which is
where the glitch occurs. This glitch did not occur in either the thevenin equiva
lent source or the
indoor solar panel tests indicating that the glitch has to do with the semicondu
ctor physics of the
solar panel.
This brief stage where the derivate is zero at a point other than the maximum po
wer point
could cause major problems for the control system. The control system is searchi
ng for a point
on the power vs. duty cycle curve where the derivative is zero. The derivative s
hould only be
zero at the maximum power point of the system. However, the derivative is zero i
n two separate
locations. As a result, the control system is fooled into thinking the maximum p
ower point
occurs at a duty cycle of approximately 40% when the actual maximum power point
is 55%. In
order to eliminate such a scenario, the control system forces the duty cycle lef
t or right when the
derivative is zero depending on what the previous derivative is. As a result, th
e control system
should have no problem overcoming the glitch at 40% duty cycle. This can be seen
in the closed
loop duty cycle in Figure 6-16.
Figure 6-16: Outdoor Closed Loop Duty Cycle vs. Time
As indicated by the duty cycle vs. time in Figure 6-16, the duty cycle does in f
act obtain the
optimal power point of approximately 55% duty cycle. The actual maximum power po
int within
the first 100 or so seconds is slightly larger than 56%. This is due to the cons
tantly changing
ambient conditions of the sunlight during the outdoor tests. Adding a trend line
to the duty
cycle, the duty cycle is visibly decreasing indicating that the maximum power po
int is changing.
This can more clearly be seen in the closed loop power vs. time curve shown in F
igure 6-17.
Figure 6-17: Outdoor Closed Loop Power vs. Time
Over time, both the maximum power output and the maximum power point are shiftin
g down.
The power is more clearly dropping in the power vs. time than in the duty cycle
vs. time figure.
The power is expected to drop with increasing temperature and decreasing sunligh
t. As soon as
sunlight begins to shine on the solar panel, the solar panel begins to quickly h
eat up, decreasing
the open circuit voltage of the system. As the sun begins to drop from the sky,
there is less direct
sunlight striking the solar panel resulting in less current. Viewing the current
and voltage vs.
time will demonstrate which of the two scenarios is causing the slowly dropping
power. This
can be seen in Figure 6-18.
Figure 6-18: Outdoor Closed Loop Voltage and Current vs. Time
Figure 6-18 indicates that the voltage is remaining constant over time around 14
volts, whereas
the current is slowly decreasing from approximately 1.75 amps down to 1.6 amps a
fter
approximately 500 seconds. At this point, the middle of the day has already pass
ed being
approximately 2 p.m. on a February afternoon. At this time during the day, the s
un is already
well on its way to setting, which would cause a decrease in current output from
the solar panel as
indicated in the figure above. This demonstrates that with decreasing sunlight o
ver the course of
the day, the maximum power output drops faster than the optimal maximum power po
int.
To further demonstrate this point, another test was performed at 3 p.m. and run
for 15
minutes allowing the power to clearly show how much the power output begins to d
ecrease as
the sun gets closer and closer to the horizon shown in Figure 6-19.
Figure 6-19: Power and Duty Cycle vs. Time (Sun Setting)
In Figure 6-19, as the sun gets closer and closer to the horizon, the power begi
ns to drop
significantly reaching a power output of approximately 10 watts after about 1000
seconds, which
occurs at about one to two hours before sun set. As expected, the duty cycle whe
re the
maximum power point is located, is constantly decreasing along with the power in
dicating that
with less light intensity striking the solar panel, the lower the maximum power
point will be.
One significant detail from the figures above is that there are no major deviati
ons off of
the constantly decreasing power and duty cycle. As originally expected, the maxi
mum power
point moves very slowly over the course of the day giving the control system ple
nty of time to
accurately track it, meeting the goal of the project.
7.0 Future Recommendations
This section will include the current issues that relate to our current design t
hat we have
discovered over the course of the project, which is recommended to have a fully
functional
system. All recommendations are a result of a shortage of time.
Minimize Noise
The electrical and quantization noise adds a small change in derivative that thr
ows the
controller off as described in the controls section. While the signals were filt
ered to minimize
this noise, it still has a small effect on the derivative signal. When the deriv
ative signal is not
large enough compared to the noise, the signal to noise ratio drops where the co
ntroller makes
wrong decisions. However, with the natural filter response of the closed loop co
ntroller and the
addition of the IIR filter, the controller works well even with this noise by di
sregarding these
high frequencies. However, slight improvement of this noise will make the contro
ller react faster
to different maximum power points and therefore more reliable.
Monitor Battery Voltage
An excessively discharged battery can cause high voltage spikes that can go beyo
nd the
maximum voltage range of some components. In order to properly recharge the batt
ery, research
needs to be done to find the exact cause of the problem and perhaps run in a spe
cial low battery
voltage mode. Further, if the battery voltage is extremely low, the instrumentat
ion amplifier used
for currents sensing may not work, and the microprocessor should default to a fi
xed duty cycle
when the processor detects erroneous current samples.
Outdoor Testing
The system was extensively tested in lab with many different variables. The cont
roller
worked well during the one day we took it outside. However, this is far from a g
uarantee that the
system works in all outdoor sunlight conditions. The system should work in all c
onditions;
however testing should be run for a full days length, verifying the system moves
accordingly
with different sunlight intensities and angles, as well as how the system reacts
to passing clouds.
8.0 Conclusions
To complete this project in an effective manner a thorough understanding of sola
r
technology and important aspects of it is essential. A variety of different appl
ications were
researched and determined whether or not they are even feasible at the current s
tate of solar
technology. The most feasible application for solar power is for remote location
s requiring small
quantities of power to run lighting, pumps, and other low power applications. Th
e sun has the
ability to give off lots of energy; however solar panels can only convert a smal
l amount of solar
energy to electrical energy due to inefficiency in solar panel technology.
Simply connecting a solar panel to a battery or a load can further decrease the
available
efficiency. Solar power systems benefit from an MPPT device in order to extract
the maximum
available power from the solar panels in the system. The MPPT is a charge contro
ller that
compensates for the changing Voltage vs. Current characteristic of a solar cell.
By monitoring
the voltage and current output of the solar panel, the MPPT tracks the always-ch
anging operating
point in order to draw the maximum amount of power available during all periods
of the day.
The Maximum Peak Power Tracking System was designed with efficiency being of mai
n
concern. To meet this main design requirement, many components and operating con
ditions
were selected based on an efficiency analysis that was performed in order to min
imize the power
loss through the circuitry. A thorough power loss analysis proved our design to
be greater than
90% efficient. A circuit that would monitor the solar panels power output and adj
ust the
operating conditions based on a control system in order to maximize the power ou
tput was
successfully designed. A unique current sensing idea was implemented that minimi
zed the power
loss compared to other designs researched.
Over the course of this project a number of practical problems were encountered
that a
typical engineer would run into. Working with and for two different advisors tha
t helped us solve
these types of problems provided us with a solid basis for what to expect in a b
usiness
environment. This form of project gave us a unique for of experience that would
not be available
in a typical classroom.
References
Aldous, Scott. How Solar Cells Work. How Stuff Works. Nov. 2, 2002.
<http://fitness.howstuffworks.com/solar-cell.htm?printable=1>.
Bogus, Klaus and Markvart, Tomas. Solar Electricity. Chichester, New York.
Wiley Press, 1994.
Distributed Power Solutions Home Page. 2003. Minneapolis, Minnesota.
<http://www.distributedpowersolutions.com/education/support.asp>.
Nation Center for Photovoltaics. Turning Sunlight into Electricity. 20 Oct. 2002.
<http://www.eren.doe.gov/pv/siatomic.html>.
National Solar Supply Home Page. 2003
<http://www.nationalsolarsupply.com/page.asp?id=18>
Neville, Richard C. Solar Energy Conversion. The Netherlands: Elsevier Science,
1995.
Optima Batteries Home Page. 1996-2004. Johnson Controls Inc.,
<http://www.optimabatteries.com/faq.asp>.
Rincn-Mora, Gabriel and Zadeh, Hassan. Current Sensing Techniques for DC-DC
Converters. 2002. <http://users.ece.gatech.edu/rincon
mora/publicat/journals/mwscas02/isense.pdf>.
Sayigh, A.A.M., ed. Solar Energy Engineering. New York, USA:
Academic Press, 1977.
Ziemer, Rodger. Signals and Systems: Continuous and Discrete 4th Ed.
New Jersey, USA: Prentice Hall, 1998.
Appendix
A:
Schematic
Appendix B: Datasheets
AD627
IRL7833
MBRD1040CT
PIC16F87XA
Appendix C: MPPT Code
#include <P16F873A.h>
#include <datalib.h> // RS232 Routines
#include <Strings.h> // iPrtString Function
#include <delays.h>
#asmline __CONFIG 0x393A
// Enable Quick Interrupts
const int QuickInt=1;
enum {T1Overflow=1, ADConversion=2}; // Timer 0 Overflow, A/D Conversion Complet
e
unsigned char IntFlags; // Interrupt Flags
unsigned int DutyCycle[8]; // PWM Duty Cycle (0 to 1024)
unsigned int Voltage[4]; // Total amount of Voltage samples ([0] counts as one)
unsigned int Current[4]; // Total amount of Current samples ([0] counts as one)
unsigned long Vavg;
unsigned long Iavg;
unsigned long varlong;
unsigned char SampleNum; // Current Sample Number
signed int Power[8]; // Current Power Sample
signed int Powerdiff; // Difference between Power samples
signed int DCdiff; // Difference between DutyCycle samples
signed int Derivative;
signed int DerivativeZ1;
signed int der_acc;
char SerString[7];
void main(void); // Main loop
void initialize(void); // Initial Setup
void interrupt(void); // Interrupt Handler
void ADSample(void); // Converts 2 A/D channels to Voltage and Current values
void AverageVC(void); // Averages voltage and current A/D samples
void PWMout(void); // Update PWM duty cycle
void PWMSweep(void); // Sweep PWM Duty Cycle from 0 to 100%
void RS232Display(void); // Display PWM -Power
void RS232Out(void);
void Control(void); // Control algorithm
const long SERIALRATE_IN=19200;
const int BITTIME_IN=(APROCFREQ)/SERIALRATE_IN/4;
const unsigned char SERIALPORT_IN=&PORTC;
const unsigned char SERIALBIT_IN=7;
// Set up Serial Port Out on Port C Bit 6
const long SERIALRATE_OUT=19200;
const int BITTIME_OUT=(APROCFREQ)/SERIALRATE_OUT/4;
const BYTE SERIALPORT_OUT=&PORTC;
const BYTE SERIALBIT_OUT=6;
//
// USER DEFINED PARAMETERS
//
char Kd=4; // Derivative gain Kd of control system
const unsigned char bksamp=1; // Back sample to sample number bksamp
const unsigned char MODE=1;
// MODE=0 Controller specifies DC
// MODE=1 Sweep DC
// MODE=2 Constant DC
const unsigned char DEBUG=1;
// DEBUG=1 Debug mode (RS232 Out)
// DEBUG=0 Production mode (No debug info)
//
// -----------------------------------------------------------------------------
-------------------------------------------------------------------//
//********MAIN PROGRAM**********//
void main(void)
{
initialize();
while(1)
{
if (IntFlags&=ADConversion); // A/D Interrupt Occured (26.2ms)
{
ADSample(); // Sample the V and I inputs
if (SampleNum==4) // Takes 4 samples of V and I
{
INTCON=0x00;
// Disable all interrupts
RS232Display();
// Display information through RS232
#if MODE==1 // MODE = Sweep DC
PWMSweep(); // Change RS2323 Display to DutyCycleZ (not Z1)
PWMout();
#endif
#if MODE==2 // MODE = Constant DC
DutyCycleZ=0x01AE;
PWMout();
#endif
Wait(50); // Delay 50ms
AverageVC();
Control();
#if MODE==0 // MODE = Derivative Controller
PWMout();
#endif
INTCON=(1<<GIE)|(1<<PEIE); // Enable all interrupts
}
IntFlags&=~ADConversion; // Reset A/D Flag
}
} // End While Loop
} // End Main Function
void ADSample(void)
// Sample RIGHT justified in ADRESH:ADRESL
{
unsigned int Chan1; // Channel 1 of A/D (Left Justified 10 bits)
unsigned int Chan3; // Channel 3 of A/D (Left Justified 10 bits)
217
if (~ADCON0&(1<<CHS1)) // If A/D conversion is Channel 1
{ // Chan 1 = Voltage
Chan1=ADRESH; // Place high and low byte of AD sample into Chan1
Chan1<<=8;
Chan1|=ADRESL;
#asmline BSF ADCON0, CHS1 ; Clear Channel 1, Set Channel 3
Voltage[SampleNum]=Chan1; // Set voltage value to chan1 A/D
}
else // If A/D conversion is Channel 3
{ // Chan 3 = Current
Chan3=~ADRESH&0x03; // Place high and low byte of AD sample into Chan3 for curre
nt
Chan3<<=8; // Invert ADRESH and ADRESL since hardware is inverted
Chan3|=~ADRESL;
#asmline BCF ADCON0, CHS1 ; Clear Channel 3, Set Channel 1
Current[SampleNum]=Chan3; // Set current value to chan3 A/D
SampleNum++; // Increment Sample Number
}
} // End of ADConv function
void AverageVC(void)
{
for(SampleNum=1; SampleNum<=3; SampleNum++) // 1 to (Total Samples -1)
{
Voltage[0]+=Voltage[SampleNum]; // Add up 8 samples and put in Voltage[0]
Current[0]+=Current[SampleNum]; // Add up 8 samples and put in Current[0]
}
SampleNum=0;
Voltage[0]>>=2; // Divide by 8
Current[0]>>=2; // Divide by 8
}
void Control(void)
{
// Conversions:
// Voltage: 20 volts = 1024 * x x = 1 / 51.2
// Current: 4 Amps = 1024 * y y = 1 / 256
// Power = V * I x * y = 1 / 13056
unsigned long varlong;
unsigned char i;
for (i=7; i!=0; i--)
{
Power[i]=Power[i-1]; // Copy samples to memory
}
DerivativeZ1=Derivative; // Copy sample to old sample for when Der is zero
Vavg=Voltage[0]; // Copy integer to long
Iavg=Current[0]; // Copy integer to long
varlong=Voltage[0]*Current[0];
varlong=Vavg*Iavg; // Multiply long types
Power[0]=0;
Power[0]|=varlong>>5; // PowerZ is 15 bits
Powerdiff=Power[0]-Power[bksamp]; // Diff is full 15 bit integer. 4A * 20V = 80W

DCdiff=DutyCycle[0]-DutyCycle[bksamp]; // DC Diff = 15 bit
//Derivative = ((Powerdiff<<2)/(DCdiff>>5));
Derivative=((Powerdiff<<2)/(DCdiff>>5));// PowerDiff is 15 bit<<2=17bit, DCdiff
is 10 bit
// DC is shifted to 10 bit because that is max resolution of PWM out
// Max derivative is 20W/1DC
der_acc+=Derivative; // IIR Filter
der_acc>>=1; // Divide by 2
Derivative=der_acc;
//DutyCycle[1]=DutyCycle[0]; // Before writing new DC, save current DC to old DC

for (i=7; i!=0; i--)
{
DutyCycle[i]=DutyCycle[i-1];
}
//#if MODE==0
Derivative *= Kd; // Derivative GAIN
if (DCdiff==0)
{
if (DerivativeZ1&(1<<15)) Derivative=-128;
else Derivative=128;
}
DutyCycle[0] += Derivative; // DC 15 bit
if (DutyCycle[0]&(1<<15)) DutyCycle[0]-=Derivative;
// If Duty Cycle rolled around either forward or backwards -subtract that deriva
tive back out
//#endif
}
void PWMout(void)
{
unsigned varint;
varint=DutyCycle[0]; // Get the 15 bit version of Duty Cycle
varint>>=7; // Make 15bit DC to 8 bit PWM out
CCPR1L=(varint>>2); // Set the PWM 8 MSB from DutyCycle (10 bit)
CCP1CON&=~0x30; // Clear bits 4 and 5 of CCP1CON (2 LSB of PWM)
CCP1CON|=((varint&0x03)<<4); // OR 2 LSB of DutyCycle into 2 LSB of PWM
}
void PWMSweep(void)
{
//DutyCycle[0]=DutyCycle[0]+32;
DutyCycle[0]=0x4000;
if (DutyCycle[0]&(1<<15)) DutyCycle[0]=0x00; // if DutyCycle = 1024 (max resolut
ion)
}
void RS232Display(void)
{
SerString=0;
#if MODE==0 // Mode = Controller
iPrtString(SerString, DutyCycle[1]);
#else // Mode = PWM Sweep OR Constant DC
iPrtString(SerString, DutyCycle[1]);
#endif
RS232Out();
#if MODE==0
SerString=0;
iPrtString(SerString, Power[0]);
RS232Out();
#else
SerString=0;
iPrtString(SerString, Power[0]); // PowerZ1 = PowerZ in Control Function
RS232Out();
#endif
SerString=0;
iPrtString(SerString, Voltage[0]); // Voltage[0]
RS232Out();
SerString=0;
iPrtString(SerString, Current[0]); // Current[0]
RS232Out();
SerString=0;
iPrtString(SerString, Derivative); // Derivative of sweep is before Kd and Shift

RS232Out();
pSerialOut(0x0D); pSerialOut(0x0A); // New Line
#if DEBUG==1
if (~PORTA&(1<<4))
{
pSerialOut(0x3E);
Kd=pSerialIn();
Kd-=0x30;
pSerialOut(0x0D; pSerialOut(0x0A);
}
#endif
}
void RS232Out(void)
{
unsigned char i;
i=0;
while(SerString[i]!=0) // While String still has characters in it
{
pSerialOut(SerString[i]);
// Send them out one by one
i++; // Increment character counter
}
pSerialOut(0x09); // Tab between fields
}
void initialize(void)
{
// Configure the PWM Module
PR2=0x3F; // Set the PWM period to 19.53kHz (max resolution 10.0 bits) PR2=3F (7
8.12k)
CCP1CON&=~0x03; // Clear 2 LSB of Duty Cycle
CCPR1L=0x00; // Set inital PWM to 0%
TRISC&=~(1<<2); // Set PWM pin for output (RC2/CCP1)
T2CON=0x04; // Turn PWM Module ON; Turn Timer2 On; Set prescale to 1
TMR2=0x00; // Timer2 (PWM) prescale value=1
CCP1CON|=0x0F; // Set CCP1 Mode Select Bits to PWM
// Set RS232 Out Pin
TRISC&=~(1<<6));
// Configure the A/D Module;
PIR1&=~1<<ADIF; // Clear ADIF bit
PIE1|=1<<ADIE; // Set ADIE bit
ADRESH=0; // Clear A/D Registers
ADRESL=0;
TRISA|=0x1B; // Set PORTA<0,1,3,4> to inputs
ADCON0 = 0x89;
// Fosc/16 for 10Mhz. Set A/D on Channel 1 (RA1) A/D Module powered up
ADCON1=0x84; // Set up Port A for Analog: DDDDADAA with Vref+/-to Vdd and Vss
// Set Format: Right Justified 10bits to ADRESH:ADRESL
ADCON0 |= ADON; // Start A/D Converer module (ADON Bit)
// Configure Timer 1 for A/D conversion triggering (using Timer 1 so Timer 0 can
be used for WDT)
PIR1&=~1<<TMR1IF; // Clear Timer 1 Interrupt Flag
PIE1|=1<<TMR1IE; // Set Timer 1 Interrupt Enable
T1CON=0x10; // Timer 1 Prescale = 1 (Speed set to 1/Fosc*4 * Prescale * 65535) =
26.2mS
// 20Mhz T1CON=0x10 10Mhz T1CON=0x00
TMR1H=0x00;
TMR1L=0x00;
T1CON|=0x01; // Turn Timer 1 On
INTCON=(1<<GIE)|(1<<PEIE);
// Enable Interrupts
// GIE: General Interrupts
// PEIE: Peripheral Interrupt Enable
#if MODE==0 // Mode = Controller
Power[0]=0x00C8;
Power[1]=0x00C8;
Power[2]=0x00C8;
Power[3]=0x00C8;
Power[4]=0x00C8;
Power[5]=0x00C8;
Power[6]=0x00C8;
Power[7]=0x00C8;
DutyCycle[0]=0x2000;
221
DutyCycle[1]=0x2000;
DutyCycle[2]=0x2000;
DutyCycle[3]=0x1810;
DutyCycle[4]=0x1810;
DutyCycle[5]=0x1810;
DutyCycle[6]=0x1810;
DutyCycle[7]=0x1810;
#else // Mode = PWM Sweep
DutyCycle[1]=0x0000;
DutyCycle[0]=0x0000;
#endif
} // End of Initialize function
//
//*******************INTERRUPT HANDLER***********************//
//
void Interrupt() // An interrupt occured. Find out what it was
{
if (PIR1&(1<<TMR1IF)) // Timer 1 to trigger an A/D Conversion
{
// Automatically resets TMR1H/TMR1L to 0
PIR1&=~1<<TMR1IF; // Clear Timer 1 Interrupt Flag
//IntFlags|=T1Overflow;
ADCON0|=1<<GO; // Trigger an A/D Conversion
}
if (PIR1&(1<<ADIF)) // A/D Conversion is complete
{
PIR1&=~(1<<ADIF); // Clear the interrupt flag
IntFlags|=ADConversion; // Set user defined interrupt flag
}
} // End of Interrupt function