Recent Developments in CMOS RF

Integrated Circuits

Prof. Thomas H. Lee

Stanford University
tomlee@ee.stanford.edu
http://www-smirc.stanford.edu

Recent Developments in CMOS RF Integrated Circuits

T. Lee, Paul G. Allen Center for Integrated Systems

Introduction
Digital CMOS is hardly the ideal medium for RF ICs.
But is it hopelessly inferior?
Interesting question: How well can one do in such a
technology if one tries very hard?
Scaling delivers faster devices every year; eventually, theyll
be fast enough.
Is the substrate really so big a problem that good inductors
(and capacitors) simply cannot be realized?
Is device noise so large that CMOS LNAs will always be
HNAs?
Does the inferior 1/f noise of CMOS transistors doom the
close-in phase noise performance of oscillators?

Can you really build credible RF ICs in standard digital

CMOS?
Recent Developments in CMOS RF Integrated Circuits
T. Lee, Paul G. Allen Center for Integrated Systems

Outline
A few brief words on scaling trends
The patterned ground shield spiral inductor
Capacitors
Fractal capacitors
Accumulation mode varactors

Passive mixers
Broadband noise models for the deep submicron regime
Power-constrained LNA design
A new phase noise theory and its implications for 1/f
noise upconversion
Putting it all together: A 115mW single chip GPS receiver in 0.5m CMOS
Recent Developments in CMOS RF Integrated Circuits
T. Lee, Paul G. Allen Center for Integrated Systems

Scaling Trends in Brief

CMOS fT (and fmax) are in the range of 30GHz now, and
double roughly every three years.
Devices with ~75nm Leff have been demonstrated, and
exhibit ~150GHz fT!
CMOS suffers from large source/drain parasitics, compared with other technologies.
Gate-drain overlap capacitance is also large.

Series gate resistance is also an increasingly serious

problem as gate lengths continue to shrink, but can be
accommodated by using narrower unit devices.
Salicided gates help, too.

Interconnect layers increasing at ~0.75 to 1 level per generation (5 layers are now relatively common).
Recent Developments in CMOS RF Integrated Circuits
T. Lee, Paul G. Allen Center for Integrated Systems

Passive Elements: Planar Spiral Inductors

Planar spirals in Si technology are infamous for poor Q
(typically well below 10).
Conductor resistance, exacerbated by skin and proximity effects, typically accounts for about half the loss.
Applies to both bulk and epi technologies.

The remaining loss is primarily due to currents flowing

in the substrate.
Getting rid of the substrate would work wonders (e.g., postfab etch, SOA, etc.), but requires deviation from ordinary
process technology.
Next-best choice is to use a high-resistivity substrate, but
cant do so without sacrificing other CMOS characteristics.
Next next-best choice is to construct a pseudo-substrate out
of existing interconnect layers.
Recent Developments in CMOS RF Integrated Circuits
T. Lee, Paul G. Allen Center for Integrated Systems

Passive Elements: Planar Spiral Inductors

Most of the substrate loss is not due to the flow of magnetically induced eddy currents, contrary to widespread
superstition.
Main mechanism is simply current flow into the substrate through the parasitic capacitance between inductor and substrate.
Grounded shield interposed between inductor and substrate diverts this current into ground.
Slots cut into ground shield prevent loss in shield due to
eddy currents.
Drawback is a reduction in self-resonant frequency due to
increase in parasitic capacitance (can mitigate this by using
higher-level metal layers).

Recent Developments in CMOS RF Integrated Circuits

T. Lee, Paul G. Allen Center for Integrated Systems

http://holst.stanford.edu/~CPYue

yuechik@holst.stanford.edu

Model Description
Cs
Ls
Cox
Rsi

Csi

Rs
Cox
Csi

Rsi

http://holst.stanford.edu/~CPYue

yuechik@holst.stanford.edu

Model Description
Physical Model of Inductor on Silicon

C
R

si

R
ox

C
C

si

Effects
L s : Greenhouse Method Mutual
Couplings
Eddy
l
R s = ----------------------------------------- t - Current
w (1 e
)
ox
Feed-Through
2
C s = n w ----------------Capacitance
t ox M1-M2
C ox

ox
1
= -2- l w -----t ox

Oxide
Capacitance

C si

1
= -2- l w C Sub

Si Substrate
Capacitance

R si

2
= ------------------------l w G Sub

Si Substrate
Ohmic Loss

http://holst.stanford.edu/~CPYue

yuechik@holst.stanford.edu

Contour Plots of Q
Measured Q
4.0
5.2

10
Inductance (nH)

1.6 GHz 1
8

Measured Q
6.1
4.0
4

3.0 GHz 1 4

7
9

0
0

100 200 300 400 0

Outer Dimension (m)

100 200 300 400

Outer Dimension (m)

http://holst.stanford.edu/~CPYue

yuechik@holst.stanford.edu

Patterned Ground Shield Design

Pattern

- Orthogonal to spiral
(induced loop current)

Resistance

- Low for termination of

the electric field

- Avoid attenuation of
the magnetic field

Ground Strips
Slot between Strips
Induced Loop Current

http://holst.stanford.edu/~CPYue

yuechik@holst.stanford.edu

Parallel LC Resonator at 2 GHz

Magnitude of Z (k)

1.50
1.25

~30%

Zmax at fc

Q RESONATOR

1.00

fC
= ----f

0.75
0.50
Patterned
Polysilicon

0.25
0.00
1.0

1.5

2.0
2.5
Frequency (GHz)

3.0

None
(11 -cm)

http://holst.stanford.edu/~CPYue

yuechik@holst.stanford.edu

Noise Coupling Measurement

HP 8720B

G
S
G

P
R
O
B
E

Probe Station

G
S
G

P
R
O
B
E

http://holst.stanford.edu/~CPYue

yuechik@holst.stanford.edu

Effect of Polysilicon GS on Isolation

-40

|s21| (dB)

-50

Patterned
None
(19 -cm)

-60
-70

None
(11 -cm)

-80

Probes up
-90
0.1

1
Frequency (GHz)

10

Passive Elements: Capacitors

Ordinary parallel plate structures dont scale with technology because the vertical spacing is held roughly constant to keep interconnect capacitance small.
Bottom-plate parasitics are large (e.g., 30% of main capacitance).
Gate capacitors are area efficient, but impose bias constraints, and are not as linear as MIM structures.
Traditional varactor options (e.g., p+ in n-well) have
poor Q
Gate capacitors in accumulation-mode are an attractive alternative (Q values in excess of 100 at 1GHz are potentially realizable)

Recent Developments in CMOS RF Integrated Circuits

T. Lee, Paul G. Allen Center for Integrated Systems

Vertical vs. Lateral Flux

Lateral flux increases the total amount of capacitance.

Reduction of the Bottom-Plate Capacitance

Area is smaller.
Some of the field lines terminate on the adjacent
plate instead of the substrate.
First Terminal

Second Terminal

Second Terminal

First Terminal

Substrate

Die Micrograph

Horizontal spacing=0.6 m
Vertical spacing=0.8m
Area=24,000 m2

Boost Factor vs. Lateral Spacing

20.0

Ctotal / Cparallel

15.0

D=1.8
D=1.6
Area=24000 m2

10.0

Vertical metal spacing=0.8 m

Metal thickness=0.8 m
Fabricated
fractal

5.0
2.3
0.0
10

0.6

Minimum horizontal spacing (m)

0.1

Measurements
Magnitude of Y12 (siemens)

100
fres = 3.7 GHz
+ Measurements

10-1

Best-Fit RLC Model

10-2
108

109
Frequency (Hz)

1010

High-frequency two-port measurements

Measurements
rs

Cb

Ls

C = 5.5 pF
C b = 0.3 pF
L s = 0.34 nH
r s = 1.3
Best-Fit Parameters

Cb

Passive Elements: Capacitors

Accumulation-mode varactor (ref. Soorapanth et al.,
VLSI Circuits Symposium, June 1998):

n+

n+
n-well
p-substrate

Compatible with standard CMOS processing

Practical capacitance range exceeds 150%

Recent Developments in CMOS RF Integrated Circuits

T. Lee, Paul G. Allen Center for Integrated Systems

Passive Mixers
Gilbert multiplier performs mixing in current domain
because bipolar transistors are not good voltage switches.
Penalty: V-I conversion costs power and linearity

CMOS voltage switches are excellent, so mixers made

out of them work well:
LO

LO
vIF
LO

LO

@1.6GHz: 3.6dB loss, +10dBm IIP3 achieved at 200W

Recent Developments in CMOS RF Integrated Circuits
T. Lee, Paul G. Allen Center for Integrated Systems

Simple CMOS Noise Model

vg2

Cgd

Rg

Channel
Thermal Noise

Cgs

vgs

gmvgs

id2

ro

Channel thermal noise is dominant.

i = 4 kTBg d 0
2
d

Gate resistance minimized by good layout.

Stanford University

LNA Input Stage

gm
1
Ls T Ls
+
Zin = s Ls + Lg +
sCgs Cgs

G m ,eff

g m1
= g m1Qin =
C gs ( Rs + T Ls )

T
=
=
T Ls 2 Rs
Rs 1 +

Rs

Note: Gm,eff is independent of gm1!

Stanford University

Zin

Lg

Vbias

M2
M1
Ls

Induced Gate Effects

Vgs

Ig
G

D
Gate Noise Current
Real Component of Zg

Stanford University

Vds

Equivalent Gate Circuit

_

+
+
Vgs
_

+
ig2

gg

Cgs

-OR-

Vgs
_

vg2

rg
Cgs

2 2

Cgs
1
1
2
2
gg =
rg =
v g = 4 kTB rg
ig = 4 kTB g g
5 gd 0
5 gd 0
Blue Noise
White Noise
( 4/3) modified by hot electron effects

ig2 partially correlated with id2 (c = 0.395j)

ig2 and gg not modeled in HSPICE
Stanford University

LNA Design Procedure

Select device width roughly equal to (500m-GHz)/f0
(for a 50 system)
Adjust bias to obtain desired power dissipation
Keep VDSVDSAT as small as practical to minimize hot-electron effects (say, under half a volt or so)

Select source degeneration inductance (assuming equalsized cascoding and main devices) according to:
LS

R S [ 1 + 2 ( C gd C gs ) ]
T

Add enough gate inductance to bring input to resonance

Noise factor bound is 1 + 2.4(/)(/T), so scaling continues to help directly
Recent Developments in CMOS RF Integrated Circuits
T. Lee, Paul G. Allen Center for Integrated Systems

C IRCUITS : LNA / M IXER

LNA

Mixer

Measured LNA Noise Figure

LOp

LOm

3.0

NF = 2.4dB @ 1575MHz

IFA

Vb
RFp

RFm
Ibias

Noise Figure (dB)

2.8

Ibias = 4.9mA

2.6

2.4

2.2

2.0
1550

1560

1570
1580
Frequency (MHz)

1590

1600

Shahani, Shaeffer and Lee, A 12mW Wide Dynamic Range CMOS GPS Receiver, ISSCC 1997

http://smirc.stanford.edu/papers/Orals98s-ali.pdf

Email: hajimiri@smirc.stanford.edu

Oscillators Are Time-Variant Systems

i(t)

(t )

i(t)

Vout

Impulse injected at the peak of amplitude.

Vout

Impulse injected at zero crossing.

t

Even for an ideal LC oscillator, the phase response is Time Variant.

http://smirc.stanford.edu/papers/Orals98s-ali.pdf

Email: hajimiri@smirc.stanford.edu

Phase Impulse Response

The phase impulse response of an arbitrary oscillator is a time varying step.
i(t)
i(t )

h ( t, )

(t )

The unit impulse response is:

( o )
h ( t , ) = ------------------- u ( t )
q max
( x ) is a dimensionless function periodic in 2, describing how much
x
phase change results from applying an impulse at time: t = T -----2

http://smirc.stanford.edu/papers/Orals98s-ali.pdf

Email: hajimiri@smirc.stanford.edu

Impulse Sensitivity Function (ISF)

LC Oscillator

Ring Oscillator

V out ( t )

V out ( t )

Waveform
t

( 0 t )

ISF

( 0 t )

The ISF quantifies the sensitivity of every point in the waveform to perturbations.

http://smirc.stanford.edu/papers/Orals98s-ali.pdf

Email: hajimiri@smirc.stanford.edu

Phase Response to an Arbitrary Source

( 0 )
h ( t , ) = ------------------- u ( t )
q max

i (t )

(t )

Superposition Integral:

(t ) =

1
h ( t , ) i ( ) d = ---------------q max

( 0 ) i ( ) d

Equivalent representation:
( 0 t )
i(t )
---------------q max

Phase
Modulation

Ideal
Integration
(t )

V (t )

(t )

cos [ 0 t + ( t ) ]

http://smirc.stanford.edu/papers/Orals98s-ali.pdf

Email: hajimiri@smirc.stanford.edu

Noise Contributions from no

1
( t ) = ------------- c 0
q max
2

in
------- ( )
f

i ()d +

n=1

cn

i ( ) cos ( n ) d

1
--- Noise
f

c0

S ()

Sv ()

2 0

c1

c2

3 0

c3

PM

2 0

3 0

http://smirc.stanford.edu/papers/Orals98s-ali.pdf

Email: hajimiri@smirc.stanford.edu

Effect of Symmetry
c0

1
= -----2

( x ) dx
0

Symmetric rise and fall time

V out ( t )

Asymmetric rise and fall time

V out ( t )

(t )

(t )

The dc value of the ISF is governed by rise and fall time symmetry, and
controls the contribution of low frequency noise to the phase noise.

http://smirc.stanford.edu/papers/Orals98s-ali.pdf

1/f

Email: hajimiri@smirc.stanford.edu

Corner of Phase Noise Spectrum

The 1/f3 corner of phase noise is NOT the same as 1/f corner of device noise

c 0 2

-
3 = 1 f ------------
1f
rms

c0
L ( )
c1
c3
c2

1
----2f

----3
f

1
--f

log(-o)

By designing for a symmetric waveform, the performance

degradation due to low frequency noise can be minimized.

http://smirc.stanford.edu/papers/Orals98s-ali.pdf

Email: hajimiri@smirc.stanford.edu

A Symmetric LC Oscillator
Vdd
WP/L

WP/L
L

Adjust ratios
for symmetry

WN/L

WN/L

Possible to Adjust Symmetry Properties of the Waveform

http://smirc.stanford.edu/papers/Orals98s-ali.pdf

Email: hajimiri@smirc.stanford.edu

Complementary Cross-Coupled VCO

Phase noise below carrier at 600kHz offset

f0=1.8GHz, 0.25m Process

Vdd

112

L
C

114
116
118

bias

120

Itail
Gnd

122
124

f0=1.8GHz

126
3
2.5
2

Vdd

1.5
16

14

12

10

Itail (mA)

x 10

P=6mW
-121dBc/Hz@600kHz

GPS OVERVIEW : T YPICAL R ECEIVER A RCHITECTURES

Dual-Conversion
2

Distinguishing Features:

Typical on-chip PD

is 100mW 500mW

PLL

- OR 1

Off-Chip

Off-chip LNA or
active antenna

Single-Conversion

Off-chip IF filtering

1 or 2 bit quantization
PLL
Off-Chip

A RCHITECTURE : L OW-IF R ECEIVER

Primary Goal: Make choices to minimize PD , maximize integration.

Low-IF On-chip

1.57542GHz

2.036MHz

active channel filter.

I[n]

Image in GPS band

Relaxed I/Q matching.

Eliminate PLL prescaler

Saves power / noise.
1-bit quantization
for simplicity.

Q[n]
Band
Gap

/2

Signal Path

PLL
APD
N*M*f0
=1.573384GHz

M*f0 (M=17)
f0=4.024MHz

APD

N*f0 (N=23)

C IRCUITS : IFA
Low input capacitance, high linearity.
Load resistors terminate the active filter input.
Simulated IFA Voltage Gain
30

Ibias Ibias

Outp

M2

Inp Inm
M1

M4

M3

Outm

Voltage Gain (dB)

20
10
0
-10
-20
-30
-40
-0.2

-0.1
0.0
0.1
DC Input Voltage (V)

0.2

C IRCUITS : G M -C F ILTER (T RANSCONDUCTOR )

Use two square-law transconductors to build a linear, class-AB transconductor.
A little positive feedback (M10) compensates for mobility degradation in M1.

Simulated Gyrator Transconductance

M10

1.10

Ibias

1.05

Outp

Inp

M1

M2

M6

Inm

Outm

Relative Gm

M5

With Positive FB (M10)

Without Positive FB
+/- 10% M10 Variation

1.00

0.95

0.90
-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2
DC Input Voltage (V)

0.3

0.4

E XPERIMENTAL R ESULTS : N OISE F IGURE

Coherent Receiver Spot Noise Figure
(Pre-Limiter)
12.0

Noise Figure (dB)

Fine Quantization
1-bit Quantization
9.0

6.0

3.0
1.0

1.5

2.0
2.5
3.0
IF Frequency (MHz)

3.5

4.0

E XPERIMENTAL R ESULTS : L INEARITY

Signal Path 3rd Order Intermodulation

Output Voltage (dBVrms)

40
20
0
-20

=3

e
lop

-40
-60
-80
-45

-40

-35
-30
-25
-20
Input Power (dBm)

-15

-10

E XPERIMENTAL R ESULTS : B LOCKING P ERFORMANCE

Receiver 1-dB Blocking De-Sensitization
(No Front-End RF Filter)

Blocking Source Power (dBm)

-20

-30

-40

INMARSAT
Uplink Band

-50

-60

10

20
30
40
50
Offset Frequency (MHz)

60

E XPERIMENTAL R ESULTS : PLL S PURIOUS

PLL Spurious
10

Relative Power (dBc)

0
-10

INMARSAT
Uplink

-20
-30
-40

f1

f2
f1-f2

-50
-60
-70
-80
1475

1525

1575
1625
Frequency (MHz)

1675

P ERFORMANCE S UMMARY

Signal Path Performance

LNA Noise Figure
LNA S11
Coherent Receiver NF
IIP3 (Filter-limited)
Peak SFDR
Filter Cutoff Freq.
Filter PB Peaking
Filter SB Atten.

G
A

Pre-Filter p
Pre-Filter v
Total p
Total v
Non-Coherent Output SNR

G
A

2.4dB
-15dB
4.1dB
-16dBm @ -43dBm
57dB
3.5MHz
1dB
52dB @ 8MHz
68dB @ 10MHz
19dB
32dB
82dB
107dB
15dB

Ps

PLL Performance
Loop Bandwidth
Spurious Tones
VCO Tuning Range
VCO Gain Constant
LO Leakage @ LNA

5MHz
-42dBc
240MHz ( 7.6%)
240MHz/V
-53dBm

Power/Technology
Signal Path
PLL / VCO
Supply Voltage

79mW
36mW
2.5V

Die Area
Technology

2
11.2
0.5 m CMOS

mm

Closing Thoughts
CMOS is not ideal, but much more than adequate for
many applications.
Scaling trends will continue to improve CMOS.
RF CMOS is not an oxymoron anymore.

Recent Developments in CMOS RF Integrated Circuits

T. Lee, Paul G. Allen Center for Integrated Systems

Acknowledgments
Many slides were prepared, and generously supplied,
by the following Stanford Ph.D. candidates:
Hirad Samavati (fractal capacitors)
Patrick Yue (spiral inductors)
Ali Hajimiri (oscillator phase noise)
Derek Shaeffer and Arvin Shahani (LNA work and GPS
receiver)

Recent Developments in CMOS RF Integrated Circuits

T. Lee, Paul G. Allen Center for Integrated Systems