INTRODUCTION TO IC TECHNOLOGY

The growth of electronics started with invention of vaccum tubes and associated
electronic circuits. This activity termed as vaccum tube electronics, subsequently the evolution of
solid state devices and consequent development of integrated circuits are responsible for the
present status of communication, computing and instrumentation.
The first vaccum tube diode was invented by john ambrase fleming in 1904.
The vaccum triode was invented by lee de forest in 1906.
n 194! the first point contact transistor was invented by john barden and walter H !rattain at
bell laboratories. "accum tubes ruled in first half of #0
th
century with large e$pensive, power%
hungry, unreliable. nvention of transistor is the driving factor of growth if the "L#I technology.
Integrated $ir$%it
t is a circuit where all discrete components such as passive as well as active elements are
fabricated on a single crystal chip.
The first semiconductor chip held two transistors each.
The first integrated circuits hels only a few devices, perhaps as many as ten diodes,
transistors, resistors, and capacitors, ma&ing it possible to fabricate one or more logic
gates on a single device.
's on increasing the number of components(or transistors) per integrated circuit the
technology was developed as
#mall s$ale integration&##I' The technology was developed by integrating the number of
transistors of 1%100 on a single chip. *$+ ,ates,flip%flops,op%amps.
(edi%m s$ale integration&(#I' The technology was developed by integrating the number of
transistors of 100%1000 on a single chip. *$+-ounters,./0, adders, 4%bit microprocessors.
Large s$ale integration&L#I' The technology was developed by integrating the number of
transistors of 1000%10000 on a single chip. *$+1%bit microprocessors,23.,2'..
"er) large s$ale integration&"L#I' The technology was developed by integrating the number
of transistors of 10000%1.illion on a single chip. *$+16%4# bit
microprocessors,peripherals,complimentary high .35.
Ultra large s$ale integration&UL#I' The technology was developed by integrating the number
of transistors of 1.illion%10 .illions on a single chip. *$+ special purpose processors.
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Giant s$ale integration&G#I' The technology was developed by integrating the number of
transistors of above 10 .illions on a single chip. *$+*mbedded system, system on chip.
"er) large s$ale integration&"L#I' vlsi is the process of created integrated circuits by
combining thousands of transistors into a single chip. "L#I begins in the 19!06s when comple$
semiconductor and communication technologies were being developed. The microprocessor is a
"L#I device.
Uses of "L#I
5implicity of operataion.
3ccupies a relatively smaller silicon area.
.anufacturing process is simple requires fewer processing steps.
7igh component density(i.e., microprocessors and microcontrollers are constructed).
"85 systems are high performance and cost effective systems.
-onsume less power than discrete components.
5maller in si9e.
*asier to design and manufacture.
7igher reliability.
7igh operating speed.
:esign fle$ibility.
7igh productivity.
7igher functionality.
:esign security.
"L#I chips are widely used in various branches of engineering li&e
:igital signal processing.
.ultimedia information systems%;T*2;*T
"oice and data communication networ&s.
<ireless 8';
2
2econfigurable computing.
=luetooth
5onnet.
=us interface via >-,/5=.
-ommercial electronics+ T" sets, :":.
-omputers and computer graphics.
'utomobiles,toys.
Medicine: Hearing aids, implalnts for human body.
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Moores Law
In 1965, Gordon Moore, an industry pioneer, predicted that the number of transistors
on a chip doubled every 18to 24 months
!e also predict that semiconductor technolo"y #ill double its effectiveness every 18
months
Many other factors also "ro# e$ponentially those are
% cloc& fre'uency
% processor performance
In$rease in Transistor Co%ntoore6s 8aw+ ;umber of transistors of a chip doubles every1.?
to# years
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Transistor
' transistor is a semiconductor device used to amplify and switch electronic signals and
power. t is composed of a semiconductor material with atleast three terminals for connection to
an e$ternal circuit. ' voltage or current applied to one pair of the transistor6s terminals changes
the current flowing through another pair of terminals. =ecause the controlled (output) power can
be much more than the controlling (input) power, a transistor can amplify a signal. Today, some
transistors are pac&aged individually, but many more are found embedded in integrated $ir$%its.
Transistors are mainly of two types bipolar transistors and field effect transistors.
!i*olar transistor &!+T'
The bipolar transistor(=@T) is a three terminal device consisting of either twon n% and one
p%type layers of material called npn transisitor or two p% and one n%type layers of material
called pnp transistor.
( =ipolar transistors are so named because the controlled current must go through two types
of semiconductor material+ > and ;. The current consists of both electron and hole flow,
in different parts of the transistor.=@T is a current controlled device.
The base current of =@T controls the emitter current and thereby collector current.
The functional difference between a >;> transistor and an ;>; transistor is the proper
biasing (polarity) of the Aunctions when operating. Bor any given state of operation, the
current directions and voltage polarities for each &ind of transistor are e$actly opposite
each other.
Transistors function as current regulators by allowing a small current to control a larger
current. The amount of current allowed between collector and emitter is primarily
determined by the amount of current moving between base and emitter.
n order for a transistor to properly function as a current regulator, the controlling (base)
current and the controlled (collector) currents must be going in the proper directions+
meshing additively at the emitter and going against the emitter arrow symbol.
,ield effe$t transistor&,ET'
The field%effect transistor(B*T) is a three terminal unipolar device depending only either
electron(n%channel) or hole (p%channel) conduction.
B*T6s are more temperature stable than =@T6s, and B*T6s are usually smaller than =@T6s,
ma&ing them particularly useful in integrated%circuit(-) chips.
There are three types of B*T6s are available mainly Aunction field effect
transistor(@B*T)
,.etal semiconductor field%effect transistor(.*5B*T).
.etal%o$ide%semiconductor field%effect transistor(.35B*T)
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0
The .35B*T transistor has become one of the most important devices used in the design
and construction of integrated circuits. ts thermal stability and other general
characteristics ma&e it e$tremely popular in computer circuit design.
The basic principle of the .35B*T is that the source%to%drain current(5: current) is
controlled by the gate voltage, or better, by the gate electric field. The electric field
indices charge (field effect) in tahe semiconductor at the semiconductor Co$ide interface.
Thus the .35B*T is a voltage%controlled current source.
!asi$ (O# transistors with the doping concentration of transistor two types of
.35 transistors are available as ;.35 transistor and >.35 transistor. <ith their mode
of operation further they are classified as depletion mode transistor and enhancement
mode transistor.
N(O# enhan$ement mode transistor
n.35 devices are formed in a p%type substrate of moderate doping level. The
source and drain regions are formed by diffusing n%type impurities through suitable
mas&s into these areas. Thus source and drain are isolated from one another by two
diodes and their -onnections are made by a deposited metal layer. The basic bloc&
diagrams of n.35 enhancement mode transistor is shown in figure.
f the gate terminal is connected to a positive voltage(a minimum voltage level of
threshold -oltage) with respect to the source, then the electric field established between
the gate and the substrate which gives a charge inversion region in the substrate under the
gate insulation and a $ond%$tion *ath or $hannel is formed between source and drain,
but no current flows between source and drain("
ds
D0) .
<hen current flows in the channel by applying a voltage "
ds
between source and
drain there must bea voltage(2) drop D "
ds
along the channel.
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1
This results that the voltage between gate and channel varying with distance along
the channel with the voltage being a ma$imum of "
gs
at the source end. The
effective gate voltage is "
g
D "
gs
% "
t .

To invert the channel at the drain end there will be voltage is available upto when
"gs%"t E "ds.
Bor all voltages "
ds
F "
gs
% "
t
the device is in the non.satr%rated region.
<hen "
ds
is increased to a level greater than "
gs
% "
t,
, if the voltage drop D "
gs
%
"
t
ta&es place over less than the whole length of the channel near the drain, there
is insufficient electric field available to give rise to an inversion layer to create
the channel. Then the voltage is called G*in$h.off6 voltage.
(
't this stage the diffusion current completes the path from source to drain and the
channel e$hibits a high resistance and behave as constant current source, This
region is &nown as Gsat%ration6 region.
n(O# de*letion mode transistor
The basic bloc& diagram of n.35 depletion mode transistor is shown in
figure. n depletion mode transistor the $hannel is established even the voltage "
gs
D 0
by implanting suitable impurities in the region between source and drain during
manufacture and prior to depositing the insulation and the gate.
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2
't this stage the source and drain are connected by a conducting channel, but the channel
may now be closed by applying a suitable negative voltage to the gate. n both
enhancement and depletion mode cases, variations of the gate voltage allow control of
any current flow between source and drain.
n(O# ,/!RIC/TION
fabrication is the process to create the devices and wires on a single silicon chip.
The process starts with a silicon substrate of high purity into which the required p%
impurities are introduced.
' layer of silicon dio$ide(sio
#
) is grown all over the surface of the wafer to
protect the surface and acts as a barrier to dopants during processing and provide
a generally insulating substrate onto which other layers may be deposited and
patterned.
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3
The surface is now covered with a photoresist which is deposited onto the wafer
and spun to achieve an even distribution of the required
thic&ness.
The photoresist layer is then e$posed to ultraviolet light through a mas& which
defines those regions into which diffusion is to ta&e place together with transistor
channels.
These areas are subsequently readily etched away together with the
underlying silicon dio$ide so that the wafer surface is e$posed in the
window defined by the mas&.
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The remaining photoresist is removed and a thin layer of sio
#
is grown
over the entire chip surface and then polysilicon is deposited on top of this
to form the gate structure.
The polysilicon layer consists of heavily doped polysilicon deposited by
chemical vapour deposition(-":),
Burther photoresist coating and mas&ing allows the polysilicon to be
patterned and then the thin o$ide is removed to e$posed areas into which
n%type impurities are to be diffused to form the source and drain.
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:iffusion is achieved by heating the wafer to a high temperature and
passing a gas containing the desired n%type impurity over the surface.
Thic& o$ide (sio
#
) is grown over all again and is then mas&ed with
photoresist and etched to e$pose selected aareas of the polysilicon gate
and the drain and source areas where connections area to be made.
The who&e chip then has metal deposited over the surface to a thic&ness
typically of 1Hm. This metal layer is then mas&ed and etched to form the
required interconnection pattern.
$(O# fabri$ation
-.35 Technology depends on using both ;%Type and >%Type devices on the same chip.
The two main technologies to do this tas& are+
1

>%<ell (Will discuss the process steps involved with this technology)
The substrate is ;%Type. The ;%-hannel device is built into a >%Type well
within the parent ;%Type substrate. The >%channel device is built directly
on the substrate.
;%<ell
The substrate is >%Type. The ;%channel device is built directly on the
substrate, while the >%channel device is built into a ;%type well within the
parent >%Type substrate.
Two more advanced technologies to do this tas& are+
=ecoming more popular for sub%micron geometries where device performance and
density must be pushed beyond the limits of the conventional p I n%well -.35 processes.
Twin Tub
=oth an ;%<ell and a >%<ell are manufactured on a lightly doped ;%type
substrate.
5ilicon%on%nsulator (53) -.35 >rocess
53 allows the creation of independent, completely isolated n.35 and
p.35 transistors virtually side%by%side on an insulating substrate.
The simplified process sequence for the fabrication of -.35 integrated circuits on a p% type
silicon substrate is shown.
The process starts with the creation of the n%well regions for p.35 transistors, by
impurity implantation into the substrate.
Then, a thic& o$ide is grown in the regions surrounding the n.35 and p.35
active regions.
The thin gate o$ide is subsequently grown on the surface through thermal
o$idation.
These steps are followed by the creation of nJ and pJ regions (source, drain and
channel%stop implants).
Binally the metalli9ation is created (creation of metal interconnects).
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!
n.well *ro$ess
The n%well -.35 process starts with a moderately doped (impurity concentration
~10
16
/cm
3
) p%type silicon substrate. Then, an initial thic& KfieldL o$ide layer (5000A) is
grown on the entire surface.
The first lithographic mas& defines the n%well region. :onor atoms, usually phosphorus,
are implanted through this window in the o$ide. 3nce the n%well is created, the active
areas of the n.35 and p.35 transistors can be defined.
Bollowing the creation of the n%well region, a thic& field o$ide is grown around the
transistor active regions, and a thin gate o$ide (01/) is grown on top of the active regions
The polysilicon layer (3000A) is deposited using chemical vapor deposition (C"D) and
patterned by dry *lasma et$hing. The created polysilicon lines will function as the gate
electrodes of the n.35 and the p.35 transistors and their interconnects
/sing a set of two mas&s, the nJ and pJ #o%r$e and Drain regions are implanted into the
substrate and into the n% well, respectively.
The ohmic contacts to the substrate and to the n%well are implanted in this process step
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"
'n insulating silicon dio$ide layer is deposited over the entire wafer using C"D
(5000A). This is for passivation, the protection of all the active components from
contamination.
The contacts are defined and etched away to e$pose the silicon or polysilicon contact
windows. These contact windows are necessary to complete the circuit interconnections
using the metal layer, which is patterned in the ne$t step.
.etal (aluminum, >5000A) is deposited over the entire chip surface using metal
evaporation, and the metal lines are patterned through etching.
5ince the wafer surface is non%planar, the quality and the integrity of the metal lines
created in this step are very critical and are ultimately essential for circuit reliability.
The composite layout and the resulting cross%sectional view of the chip, showing one
n.35 and one p.35 transistor (built%in n%well), the polysilicon and metal
interconnections.
The final step is to deposit a full 5i3
#
passivation layer (5000A), for protection, over the
chip, e$cept for wire%bonding pad areas.
M
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#
*.well *ro$ess
2.well on N.s%bstrate
;%type substrate
3$idation, and mas& (.'5N 1) to create >%well (4%?)m deep)
>%well doping
>%well acts as substrate for n.35 devices.
The two areas are electrically isolated using thic& field o$ide (and often
isolation implants Onot shown hereP)
2ol)sili$on Gate ,ormation
2emove p%well definition o$ide
,row thic& field o$ide
>attern (.'5N #) to e$pose n.35 and p.35 active regions
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,row thin layer of 5i3
#
(Q0.1)m) gate o$ide, over the entire
chip surface
:eposit polysilicon on top of gate o$ide to form gate structure
>attern poly on gate o$ide (.'5N 4)
n.35 >J 5ourceR:rain difusion C self%aligned to >oly gate
mplant >
J
n.35 5R: regions (.'5N 4)
( p.35 ;J 5ourceR:rain difusion C self%aligned to >oly gate
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( mplant ;
J
p.35 5R: regions (.'5N ? C often the inverse of .'5N 4)
p.35 ;J 5ourceR:rain difusion, contact holes I metallisation
3$ide and pattern for contact holes (.'5N 6)
:eposit metal and pattern (.'5N !)
>assivation o$ide and pattern bonding pads (.'5N 1)
>%well acts as substrate for n.35 devices.
Two separate substrates + requires two separate substrate connections
:efinition of substrate connection areas can be included in .'5N 4R.'5N?
Twin.T%b &Twin.3ell' C(O# 2ro$ess
This technology provides the basis for separate optimi9ation of the n.35 and p.35 transistors,
thus ma&ing it possible for threshold voltage, body effect and the channel transconductance of
both types of transistors to be tuned independently. ,enerally, the starting material is a nJ or pJ
substrate, with a lightly doped epita$ial layer on top. This epita$ial layer provides the actual
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2
substrate on which the n%well and the p%well are formed. 5ince two independent doping steps are
performed for the creation of the well regions, the dopant concentrations can be carefully
optimi9ed to produce the desired device characteristics. The Twin%Tub process is shown below.
$n the con%entional p & n'(ell )M*+ process, the doping density of the (ell region
is typically about one order of magnitude higher than the substrate, (hich, among
other e,ects, results in unbalanced drain parasitics. -he t(in'tub process a%oids
this problem.
#ili$on.on.Ins%lator &#OI' C(O# 2ro$ess
2ather than using silicon as the substrate material, technologists have sought to use an insulating
substrate to improve process characteristics such as speed and latch%up susceptibility. The 53
-.35 technology allows the creation of independent, completely isolated n.35 and p.35
transistors virtually side%by%side on an insulating substrate. The main advantages of this
technology are the higher integration density (because of the absence of well regions), complete
avoidance of the latch%up problem, and lower parasitic capacitances compared to the
conventional p I n%well or twin%tub -.35 processes. ' cross%section of n.35 and p.35
devices using 53 process is shown below.
The 53 -.35 process is considerably more costly than the standard p I n%well -.35
process. Set the improvements of device performance and the absence of latch%up problems can
Austify its use, especially for deep%sub%micron devices.
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3
!er4ele) n.well *ro$ess
There are a number of p%well and n%well fabrication processed and , in order to loo& more closely
at typical fabrication steps, we will use the =er&eley n%well process an e$ample. This process is
illustrated as follows+
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,abri$ation
Babrication is the process of creating or ma&ing number of devices and wires on a single
chip(-). Babrication of devices involves the following operations
<afer processing
.>hotolithography
3$ide growth and removal
:iffusing and ion implantation
'nnealing
5ilicon deposition
.etalli9ation
>robe testing
.ncapsulation
Wafer processing
>ure silicon is melted in a pot (1400
0
-) and a small seed containing the desired crystal
orientation is inserted into molten silicon and slowly pulled
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5
The silicon crystal is manufactured as acylinder &ingot) with a diameter of 1%1# inches.
This cylinder is carefully sawed into thin dis&s called wafers. <hich are later polished
and mar&ed for crystal orientation.
2hotolithogra*h)
8ithography process used to transfer patterms to each layer of the -.
:raw the KlayerL patterns on a transparent glass mas&
Transfer the mas& pattern to the wafer surface.
The surface to be patterned is spin% coated with a light sensitive organic polymer
called photoresist.
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>hotoresists are of two types
i) ;egative photoresist hardems in the areas e$posed to light
ii) >ositive photoresist hardens in the area not e$posed to light
The mas& pattern is developed on the photoresist, with /" light e$posure.
:epending on the type of photoresist (negative or positive), the e$posed
or une$posed parts become resistant to certain types of solvents.
The soluble photoresist is chemically removed.
The developed photoresist acts as a mas& for patternimg of underlying layers and
then is removed.
O5idation
3$ide can be grown from silicon through heating in an o$idi9ing atmosphere.
i) ,ate o$ide, device isolation
ii) 3$idation consumes silicon
5io
#
is deposited on materials other than silicon through reaction between gaseous
silicon compounds and o$idi9ers.
nsulation between different layers of metalli9ation
Et$hing
3nce the desired shape is patterned with photoresist, the etching process allows
unprotected materials to be removed.
(
i) <et etching+ /ses chemicals
ii) :ry or plasma etching+ /ses ioni9ed gases.
2!
Diff%sion and Ion im*lantation
:oping materials are added to change the electrical characteristics of silicon
locally through
i' Diff%sion dopants deposited on silicon move through the lattice by
thermal diffusion (high temperature process).
ii' Ion im*lantation highly energi9ed donor or acceptor atoms impinge
on the surface and travel below it
Thermal annealing is a high temperature which allows+
allows doping impurities to diffuse further into the bul&.
repairs lattice damage caused by the collisions with doping ions.
(etalli6ation deposition of metal layers by evaporation.
En$a*s%lation :uring *ncapsulation, lead frames are placed onto mold plates and heated.
.olten plastic material is pressed around each die to form its individual pac&age. The mold is
opened, and the lead frames are pressed out and cleaned.
2"