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546 vizualizări50 paginiNotes on Boolean Algebra

Jul 26, 2014

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Notes on Boolean Algebra

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546 vizualizări50 paginiNotes on Boolean Algebra

© All Rights Reserved

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The decision which results

into either YES (TRUE) or

NO (FALSE) is called a

Binary Decision.

Boolean algebra derives its name

from the mathematician George

Boole. Symbolic Logic uses values,

variables and operations :

True is represented by the value 1.

False is represented by the value 0.

Variables are represented by

letters and can have one of two

values, either 0 or 1.

LOGICAL OPERATORS

AND is represented by X.Y (LOGICAL

MULTIPLICATION )

OR is represented by X + Y (LOGICAL

ADDITION )

NOT is represented by X' (COMPLEMENT)

NOT operations have the highest

precedence, followed by AND operations,

followed by OR operations.

TRUTH TABLES

Truth table is a table which

represents all the possible values of

logical variables/statements along

with all the possible results of the

given combination of values.

I will buy a car If I get a salary increase or I win

the lottery

This statement explains the fact that the

proposition "buy a car" depends on two other

propositions "get a salary increase" and "win the

lottery".

Any of these propositions can be either true or

false hence the table of all possible situations:

Salary

Increase

Win Lottery

Buy a car = Salary Increase or

Win Lottery

False False False

False True True

True False True

True True True

Y X or Y X and Y not X

OR

X Y F = X + Y

0 0 0

0 1 1

1 0 1

1 1 1

AND

X Y F = X

.

Y

0 0 0

0 1 0

1 0 0

1 1 1

NOT

X NOT X = X'

0 1

1 0

EVALUATION OF BOOLEAN

EXPRESSIONS USING TRUTH TABLE

X+(YZ)+Z

XY+XY

XYZ+XYZ

X(Y+Z)+XY

XY(Z+YZ)+Z

A[(B+C)+C]

BASIC LOGIC GATES

A logic gate is an elementary building

block of a digital circuit . Most logic

gates have two inputs and one output.

At any given moment, every terminal is

in one of the two binary conditions low

(0) or high (1), represented by different

voltage levels.

There are three types of logic gates:-

NOT GATE

OR GATE

AND GATE

LOGIC GATES

The NOT gate or inverter is a gate

with only one input and one output

signal; the output state is always the

opposite of the input state.

NPUT

A

OUTPUT

NOT A

0 1

1 0

The OR gate has two or more input signals

but only one output signal. If any input

signal is 1(high), the output signal is 1(high)

INPUT

A B

OUTPUT

A + B

0 0 0

0 1 1

1 0 1

1 1 1

The AND gate can have two or more

input signals and produce an output

signal. When all the input signal are 1

(high) then the output is 1 otherwise

output is 0.

INPUT OUTPUT

A B A AND B (AB)

0 0 0

0 1 0

1 0 0

1 1 1

PRINCIPLE OF DUALITY

This states that starting with a boolean relation ,

another boolean relation can be derived by

1. Changing each OR sign (+) to an AND sign(.)

2. Changing each AND sign (.) to an OR sign(+)

3. Replacing each 0 by 1 and each 1 by 0

X.Y+Z = (X'+Y').Z

Find dual of the following:-

1. X+XY

2. XY+XY+XY

3. (A+0).(A.1.A)

4. AB+AB

5. ABC+ABC+ABC

LAWS AND THEOREMS OF BOOLEAN ALGEBRA

1. Properties of 0 and 1

If result of any logical statement or expression is always

TRUE or 1, it is called Tautology and if the result is

always FALSE or 0 it is called Fallacy.

2. Idempotence law

3. Involution law:

( X' ) ' = X

1. X + 0 = X 1D. X 1 = X

2. X + 1 = 1 2D. X 0 = 0

3. X + X =X 3D. X X = X

LAWS AND THEOREMS OF BOOLEAN ALGEBRA

5. Laws of complementarity

6. Commutative laws:

7. Associative laws:

8. Distributive laws:

5. X + X' = 1 5D. X X' = 0

6. X + Y = Y + X 6D. X Y = Y X

7.(X + Y) + Z = X + (Y + Z)

=X + Y + Z

7D. (XY)Z = X(YZ) = XYZ

8.X( Y + Z ) = XY + XZ 8D. X + YZ = ( X + Y ) ( X + Z )

LAWS AND THEOREMS OF BOOLEAN ALGEBRA

9. Absorption laws

10. Some Other rules of Boolean Algebra

9. X + XY = X 9D. X ( X + Y ) = X

10. ( X + Y ) X = XY 10D. XY + X = X + Y

DEMORGANS THEOREM

Proof:- Algebric and Truth table

(X+Y)=XY

(X.Y)=X+Y

DEMORGANIZATION

Complement the entire function

Change all the ANDs(.) to ORs(+) and all

the Ors (+) to ANDs(.)

Complement each of the indivodual

variables.

DERIVATION OF BOOLEAN EXPRESSION

Boolean expressions which consist of a single variable or its

complement e.g. x or y or z are known as literals.

MINTERMS

Mintermis a product of all the literals (with or without the

bar)within the logic.

Mintermcan easily be formed e.g. X=0, Y=1, Z=0 then the

mintermwill be XYZ.

A minterm must have every variable present. If a boolean

product term does not have every variable present, then it can be

expanded to its minterm representation.

F(A,B,C) = AB + C neither AB, or C are minterms

To expand AB to minterms, use the relation:

AB = AB(C+ C) = ABC + ABC

To expand C to minterms, do:

C = C(A+A) = AC+ AC = AC(B+B) + AC(B+B)

= ABC + ABC + ABC + ABC

F = AB +C = ABC + ABC + ABC + ABC + ABC

= 001 + 011 + 101 + 110 + 111

= m

1

+ m

3

+ m

5

+ m

6

+ m

7

F(A,B,C) = m(1,3,5,6,7)

DERIVATION OF BOOLEAN EXPRESSION

A maxterm is sum of all the literals(with or without the bar)

within the logic system.

If the values of variable are X=0, Y=1and Z=1 then its maxterm

will be :- X+Y+Z

A maxterm must have every variable present. If a boolean

sum term does not have every variable present, then it can be

expanded to its maxterm representation.

F(A,B,C) = (A+B) (C) neither (A+B), or C are maxterms

To expand (A+B) to maxterms, use the relation:

(A+B) = (A+B+CC) = (A+B+C)(A+B+C)

To expand C to minterms, do:

C = C+AA = (A+C)(A+C) = (A+BB+C)(A+C+BB)

= (A+B+C)(A+B+C)(A+B+C)(A+B+C)

F = (A+B)(C) =

(A+B+C).(A+B+C).(A+B+C).(A+B+C).(A+B+C)

(000) . (001) . (010) . (100) . (110)

M

0

. M

1

.M

2

. M

4

. M

6

F(A,B,C) = M(0,1,2,4,6)

CANONICAL EXPRESSION

Boolean expression composed entirely either of

Minterms or Maxterms is referred to as Canonical

Expression

Canonical expression can be represented in the

following two forms:-

Sum-of-Products (S-O-P) form

When a boolean expression is represented purely as sum of

minterm , it is said to be in Sum-of Product from

Product-of-sums(P-O-S) form

When a boolean expression is represented purely as product of

maxterms, it is said to be in Product-of-sum form of expression.

MINTERM, MAXTERM NOTATION

Each line in a truth table represents both a Minterm

and a Maxterm

TRUTH TABLE TO SOP FORM

Can write SOP form of equation directly from truth

table.

TRUTH TABLE TO POS FORM

Can write POS form of equation directly from truth

table.

F(A,B,C) = (A+B+C) (A+B+C)(A+B+C)

F(A,B,C) = ABC + ABC + ABC + ABC + ABC + ABC

SOP form. If a product term has all variables present, it

is a MINTERM.

F(A,B,C) = (A+B+C) (A+B+C)(A+B+C)

POS form. If a sum term has all variables present, it is

a MAXTERM.

All Boolean functions can be written in terms of either

Minterms or Maxterms.

MINIMIZATION OF BOOLEAN EXPRESSION

Algebraic Method

Karnaugh Maps

It is a pictorial form of a truth table and

could handle up to 6 variables.

It is used to reduce or simplify a

Boolean function.

It is an array of cells/squares in which

each cell represents a binary value of

the input variables.

MAP SET-UP (SOP Reduction)

The number of cell/square in a K-map is equal

to 2

n

where n is the number of input variables.

The map is drawn to show the relationship

between squares and input variables.

Variables are assigned to row and column.

Binary marking are placed in each row and

column using reflected code sequence.

Each cell in the map represents a

combination of input variables in a given

truth table.

GRAY CODE

It is arranged so that every transition from one value

to the next value involves only one bit change.

MAPPING OF 0S AND 1S IN THE KARNAUGH

MAP

1s are placed in the squares of a K-map to

represents minterms of a Boolean function in

canonical SOP (Sum-of-Minterm) form. The number

of 1s in the K-map is equal to the number of product

terms in the Boolean function. The cells that do not

have a 1 are the cells for which the expression is 0.

All 1s and 0s in the output column of the truth

table can be mapped directly onto a Karnaugh

map into the cells corresponding to the values of

the associated input variable combinations.

GROUPING OF 0S AND 1S

Always group adjacent cell containing 1s in powers of 2 {1,

2, 4, 8, 16, 32 or 64 1s in a group}. Start by combining the

maximum number of adjacent cell containing 1s.

Reduction of pair

Remove the variable which changes its state from complemented

to uncomplemented or vice versa. Pair removes one variable only.

Reduction of Quad

Removes two variables which changes their state.

Octet Reduction

Remove the three variables which change their states.

Map rolling

Consider the map as if its left edges are touching the right edges

and top edges are touching bottom edges.

Overlapping groups

Overlapping means same 1 can be encircled more than once

Overlapping always leads to simpler expression

Redundant Group

A group whose all 1s are overlapped by other groups.

Removal of redundant group leads to much simpler expression.

Reduce the following Boolean expression using K-map.

F (A, B, C, D) = (0,2,7,8,10,15)

Pair is M7+ M15

And Quad is M0+M2+M8+M10

Reduced expression for pair (M7+ M15) is BCD as A is removed. Reduced

expression for quad (M0+M2+M8+M10) is B`D` as for horizontal corners

C is removed and for vertical corners A is removed.

Thus final reduced expression is BCD + B`D

P-O-S REDUCTION USING K-MAP

The 0s placed in the squares of a K-map

represents the maxterms of a Boolean function in

canonical POS (Product of Maxterm) form. The number

of 0s in the K-map is equal to the number of sum terms

in the Boolean function. The cells that do not have a 0

are the cells for which the expression is 1.

Example: F(A,B,C) =

(A+B+C)(A+B+C)(A+B+C)(A+B+C)

F(A,B,C,D) = (A + B + C')(A' + B' + C +D)(A' + C' + D')

MORE ABOUT LOGIC GATES

AND , OR and NOT gate are known as basic gates.

NOR and NAND gate are known as universal

gates.

NOR gate (NOR = Not OR)

The NOR gate has two or more input signal but only

one output signal. If all the inputs are 0 (i.e. low),

then the output signal is 1(high)

Input A Input B

0 0 1

0 1 0

1 0 0

1 1 0

NAND gate (NAND = Not AND)

The NAND gate has two or more input signal but

only one output signal. If all the inputs are 1 (i.e.

high), then the output signal is 0 (low )

Input A Input B

0 0 1

0 1 1

1 0 1

1 1 0

XOR (eXclusive-OR) gate

The XOR gate have two or more inputs but produces

one output signal. OR gate produces output 1 for

any input combination having one or more 1s, but

XOR gate produces output 1 for only those

input combination that have odd 1s

Input A Input B

0 0 0

0 1 1

1 0 1

1 1 0

XNOR (eXclusive-NOR) gate

The XNOR Gate is logically equivalent to an

inverted XOR i.e., XOR gate followed by a NOT

gate. Thus XNOR produces 1 output when the

input combination has even number of 1s.

Input A Input B

0 0 1

0 1 0

1 0 0

1 1 1

REALIZATION OF BASIC LOGIC GATES USING

NAND GATES

Implementing an inverter using NAND gate

Input Output Rule

(X.X)' = X' Idempotent

Implementing AND using NAND gates

Input Output Rule

((XY)'(XY)')' = ((XY)')' Idempotent

= (XY) Involution

Implementing OR using NAND gates

Input Output Rule

((XX)'(YY)')' = (X'Y')' Idempotent

= X''+Y'' DeMorgan

= X+Y Involution

REALIZATION OF BASIC LOGIC GATES USING

NOR GATES

Implementing an inverter using NOR gate

Input Output Rule

(X+X)' = X' Idempotent

Implementing AND using NOR gates

Input Output Rule

((X+X)'+(Y+Y)')' =(X'+Y')' Idempotent

= X''.Y'' DeMorgan

= (X.Y) Involution

Implementing OR using NOR gates

Input Output Rule

((X+Y)'+(X+Y)')' = ((X+Y)')' Idempotent

= X+Y Involution

DESIGN RULE FOR NAND-TO-NAND

LOGIC NETWORK ( ONLY FOR 2- LEVEL)

Derive simplified SOP expression

Draw circuit diagram using AND OR Not gates

Replace all basic gates (AND, OR, NOT) with NAND

gates.

For e.g. Consider the following SOP expression

F = W.X.Y + X.Y.Z + Y.Z.W

DESIGN RULE FOR NOR-TO-NOR LOGIC

NETWORK ( ONLY FOR 2- LEVEL)

Derive simplified POS expression

Draw circuit diagram using AND OR Not gates

Replace all basic gates (AND, OR, NOT) with NOR

gates.

For e.g Consider the following POS expression

F = (X+Y) . (Y+Z)

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