Warp Release 6.

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Release Notes
Warp Known Problems and Solutions
Active-HDL Sim Known Problems and Solutions
Warp Professional/Enterprise Known Problems and Solutions
Warp Release 6.3
Release Notes:
WKPS.63 Page 1 of 16 July 8, 2002
Warp Release 6.3 (Warp R6.3) is an update to Warp Release 6.2. The 6.3 release adds the ability
to specify timing constraints for all of the Delta39K, Quantum38K and PSI devices; it also adds
more report file bookmarks in Galaxy for the Delta39K, Quantum38K and PSI devices. Signifi-
cant run-time improvements have been made to the Warp FE language parsers and Warp compila-
tion run in the Professional/Enterprise design flow manager. The Auto User Code preference can
now be set on a user basis and a per installation basis.
On the PC platform, Warp Release 6.3 includes the post-synthesis timing simulator Active-HDL
Sim
TM
version 3.3 and the finite-state machine editor Active-HDL FSM
TM
, from Aldec Inc.
Active-HDL Sim 3.3 is a full-featured VHDL post-synthesis timing simulator, which supports
simulation of VHDL and Verilog files compiled to Cypress devices. This simulator supports all
Cypress PLDs including the Delta39K and Quantum38K families, except for the PSI device fam-
ily. Customers wishing to simulate PSI devices must obtain Warp Professional, Warp Enterprise,
or use a separate third party simulator that supports fs resolution.
Application notes are available in the doc folder in the installation directory for Active-HDL Sim
and Active-HDL FSM. All Programmable Logic related application notes, including those specif-
ically for designs specifically targeting Delta39K/Quantum38K and PSI devices, Delta39K/
Quantum38K CPLD Device I/O Std. and Configurations and Designing with the Programmable
Serial Interface (PSI) for High-Speed Solutions, are available at http://www.cypress.com/pld/
pldappnotes.html.
NOTE: If you already have the Active-VHDL product from Aldec Inc. installed, do not install the
Active-HDL Sim shipped with Warp Release 6.3. Instead, update the primitive library. If you
have Active-HDL Sim installed with a different version of Warp, you need to re-install Active-
HDL Sim to get the library updates shipped with this version of Warp.
This release also includes Warp Professional and Warp Enterprise products. Warp Professional
and Enterprise editions are a seamless integration of Warp and Aldec's Active-HDL products.
The Warp Professional edition includes all the features available in Warp, plus the following:
design flow manager, a block diagram editor with all of the Cypress LPM symbols, and a
language assistant. A full-featured post-synthesis timing simulator is provided, and supports a
maximum of 5msec simulation cycles in a given simulation run. The simulator included in this
edition also supports PSI device simulation.
The Warp Enterprise edition includes all the features available in the Warp Professional edition,
plus the following: Code2 graphics, source level simulation with debugging capability, testbench
generation and unlimited simulation time.
Warp Release 6.3
Release Notes:
WKPS.63 Page 2 of 16 July 8, 2002
Platforms
The download contains releases for Warp on the PC platforms. The following is a summary of
the Hardware/Software platform support currently available in this release.
PDF file documentation
The Warp documentation is available in .pdf format in the doc folder in the installation direc-
tory and through the Help menu in Warp.The files can be viewed using Adobe Acrobat Reader
4.0 or later. The documentation includes three documents: the Users Guide called uguide.pdf,
the Reference Manual called refmanl.pdf and a Getting Started Manual called gs.pdf. The
Getting Started Manual contains a set of tutorials which show the user how to create a project
and compile and synthesize a design. Versions of the Active-HDL FSM editor application
note, the Active-HDL Sim application note, and the JEDEC Translator documentation are
also included in the doc directory in the PC version.
Preliminary Timing Numbers
The timing associated with Delta39K, Quantum38K and PSI and as reported by Warp is prelimi-
nary. Once full characterization and timing forecasts have been validated, the timing will move
from preliminary to production. Warp and the data sheets will be updated at that time.
Product to platform cross reference
Platforms Product
PC Windows platforms Warp
PC Windows platforms Warp Professional
PC Windows platforms Warp Enterprise
Sun/Solaris Warp
Warp Release 6.3
Known Problems and Solutions:
WKPS.63 Page 3 of 16 July 8, 2002
The following are known problems and their work-around solutions at the time of Warp Release
6.3. These problems will be addressed in upcoming releases.
Problem When I try to compile a design, I get the following warning (W460) and the com-
pilation stops.
Solution Increase the number of warnings allowed by selecting Project -> Compiler Options,
then recompile the project.
Problem When I try to compile a project with a Quantum38K, Delta39K, or PSI device, I
get a routing failure with the following type of error: (ERT009): CLUSTER(2,1),
LOGIC BLOCK D PIM routing failed.
Solution Select Tools -> Architecture Explorer to search for the affected signals going in or out
of the logic block. Create a control file and use a placement or grouping attribute on
the affected signals.
Problem Warp has limited support for ternary operators in complex expressions. If you
get an error message that says: (E625) Unsupported use of ternary operator, you
have run into a case where Warp support is limited.
Solution Reduce the complexity of your expression by breaking it up into simpler subexpres-
sions with temporary values.
Problem Installation is unsuccessful when upgrading to a new version of Warp. I get the
following error message: Not enough space in the TEMP folder. Decompression
failed.
Solution The Installshield project for Warp 6.3 might have deposited several read-only files in
temporary folders on your computer. The files will prevent future installations from
succeeding. Please find and delete these directories from your computer:
On Windows NT/2000:
\WINNT\TEMP\_ISTMP?.DIR\*.*
\WINNT\TEMP\ALDEC\*.*

On Windows 95/98/SE/ME:
\WINDOWS\TEMP\_ISTMP?.DIR\*.*
\WINDOWS\TEMP\ALDEC\*.*
Warp Release 6.3
Known Problems and Solutions:
WKPS.63 Page 4 of 16 July 8, 2002
Problem I have a Verilog design that includes a bus with at least 1 portion of the bus
having negative number indexes. When I attempt to compile the post-synthesis
VHDL netlist, I get the following errors: Value -1 out of range.
Solution Negative indices are not valid for VHDL std_logic_vector type buses. If you are
crossing language domains, make sure that you use the positive indices that are legal
in VHDL and Verilog. Please change the range to positive numbers, re-generate the
post-synthsis netlist file and re-compile.
Problem For 39K/38K/PSI devices, I am not able to specify whether or not I want bus-hold
disabled for unused I/Os.
Solution Unused I/Os for Delta39K, Quantum38K, and PSI devices are always assigned high-
impedance ('Z') and will have bus-hold enabled. If different behavior is desired, the I/
Os must be specified in the design. Then you can use the I/O Standards dialog box in
Warp to disable the bushold. Note that if you do this, you must externally drive the IOs
to a valid logic level to avoid floating CMOS inputs. Here's a VHDL example:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY top IS
PORT( unused:OUT std_logic_vector (285 downto 0));
END top;
ARCHITECTURE arch of top IS
BEGIN
-- use the next line if you want to deactivate bus-hold on unused
-- IOs.
-- To assign these IOs to 'Z without bushold', use the IO Standards
-- dialog box in Warp.
unused <= (others => 'Z');
-- Use the following line to drive your "formerly unused" IOs to 1:
unused <= (others => '1');
-- Use the following line to drive your "formerly unused" IOs to 0:
unused <= (others => '0');
END arch;
Warp Release 6.3
Known Problems and Solutions:
WKPS.63 Page 5 of 16 July 8, 2002
Problem Warp gives the message "Bad operand types 'std_logic' and 'std_logic' for opera-
tor '&'" when parsing an expression that combines a concatenation operator of
scalars and an arithmetic operation.
Solution Add parentheses to the expression to avoid scalar-scalar concatenations in an expres-
sion with arithmetic operators.
Problem When I compile a Verilog design, I get the following error: : (E88) Operation not
supported.
Solution This error occurs when you use concatenation to set the value of a parameter. The
workaround is to use wires instead of parameters or avoid using concatenation on the
right-hand side of the assignment statement for the parameter
Problem When I change the default settings for an I/O standard in the I/O standards
dialog box in Galaxy, the slew_rate and bus_hold changes are not written to the
control file during project compilation.
Solution Open the control file in any editor and enter the slew_rate and bus_hold values. Refer
to the Synthesis Directives chapter in the Users Guide for the appropriate syntax.
Problem When browsing to a directory for the Warp installation, the installation stops.
Solution Do not press the browse button when entering a path. Enter the desired path manually.
There is also more information on this problem at the following website:
http://support.microsoft.com/support/kb/articles/q192/2/49.asp
Problem My design doesnt fit after back-annotation.
Solution If your design has vectors in the top level, combine the pin_numbers attributes into
one statement in the control file after back-annotation.
For example, if you have:
fixedattribute pin_numbers of datab(0) is p1;
fixedattribute pin_numbers of datab(1) is N1;
Change the two statements to read like this one statement:
fixedattribute pin_numbers of <entity-name>:entity is
datab(0):P1 & datab(1):N1 .
Reminder: The space before each end quote must be present. This space must be
present to generate valid VHDL after concatenation.
Warp Release 6.3
Known Problems and Solutions:
WKPS.63 Page 6 of 16 July 8, 2002
Problem I expected a later signal assignment to take precedence over an earlier signal
assignment under the reset condition inside the behavorial description of a DFF.
Solution Warp doesn't properly handle multiple assignments to the same signal under a reset
condition for a DFF. It always assigns the first value and ignores the subsequent val-
ues. Always include only one assignment per signal under the reset condition for a
DFF. Other clauses assigning values to a bus should occur after all specific bit assign-
ments have been made.
Problem When I use Verilog escaped identifiers in the top level port names and attempt to
compile the post-synthesis netlist file, I get the following error: Undefined signal.
Solution The Verilog escaped identifiers in the top level port names are not currently supported.
Please change the top level port names to simple identifiers and re-run Warp. Another
workaround is to write a wrapper that hides the top level escaped identifier names.
Problem When I compile a Verilog project, I get an error: (E26) Poly_read(Object *): Not
an object or ->object.
Solution Implement the following 4 steps to correct this problem: 1) verify that all modules in
a file that are used by other modules in that same file should appear (in the file) before
they are used, 2) delete the lc directory and the .wde and .hie files in the project
directory, 3) verify that all the files are in the right order (top-level at bottom), 4) ver-
ify that all modules are in the correct order within each file, and 5) compile the project.
Problem If you place an instance of a component in the architecture for that component (a
recursive instantiation) Warp will crash.
Solution Don't place an instance of a component in the architecture defining that component.
Problem When I attempt to do post-synthesis simulation of any PSI device targeted design,
I get the following error from the simulator: No actual (value) specified for local
port .
Solution This occurs when your design does not have an instantiated SERDES component and
you target a PSI device. Make sure that you target a non-PSI device if your design
does not have a SERDES component.
Warp Release 6.3
Known Problems and Solutions:
WKPS.63 Page 7 of 16 July 8, 2002
Problem Warp is not synthesizing the correct logic when I have variable assignment state-
ments which involve user defined type variables.
Solution This is a limitation in Warp with user defined types. User defined types work only with
signal assignments. Use signal assignments instead.
Problem Name collisions may occur when using VHDL post-synthesis models created from
a Verilog file.
Solution Verilog is case sensitive, VHDL is not. Therefore, if two different names in Verilog
differ only in case, the names will conflict in VHDL. Use names that are distinct with-
out regard for case - use clock or CLOCK, but not both.
Problem Warp gives Can't handle expression 'X' in the final equation error.
Solution If you initialized a variable used in the case/if-else statement to 'X', move that initial-
ization statement to the default or last else branch of the case and if/else statement
respectively.
Problem When using the pin_avoid attribute, I specified the values by concatenating sev-
eral strings. I get a parse error from Warp.
Solution While using the pin_avoid attribute, make sure that all the values are included within
one string on one line.
Problem When I try to compile a design, Warp corrupts the VIF filename and gives a com-
pilation fail message.
Solution This happens when the design has long file names. Rename the files to be short names
and recompile.
Problem When I use a trailing underscore on signals with the pin_numbers attribute in the
control file, Warp ignores the placement constraint and assigns the signals to
whatever pins it desires. Warp also ignores lab_force or any other attribute
applied to signals with trailing underscore characters in their names.
Solution If you want to place an attribute on a signal, make sure that the signal name does not
have a trailing underscore.
Warp Release 6.3
Known Problems and Solutions:
WKPS.63 Page 8 of 16 July 8, 2002
Problem When I instantiate madd_sub/mparity/mcompare LPMs and target a Delta39K/
CYP25G01K100 device, I get the following error: (E122) Invalid connection to
formal of non-input mode. Must be a SIGNAL.
Solution This happens when the portmap of the cy_25g01serdes component instantiated has
constants. Change the constant to a signal and recompile the design.
Problem Warp is ignoring attributes that contain hierarchical names.
Solution This is a result of adding more support for extended identifiers. Hierarchical names are
represented using extended identifiers. The way of accessing the names deep in the
hierarchy inst_signalname has been changed to \inst:signalname\. If you have
hierarchy names in your old control file represented as inst_signalname, change them
to \inst:signalname\ and recompile.
Problem A ComponentMoveData Error -623 error occurs during installation on the PC
and stops the installation.
Solution This error occurs because the setup program could not rename an intermediate file
created during the file transfer process. This error usually occurs because a virus-
checking program is being used on the system to prevent files from being renamed.
When this problem occurs, disable any virus-checking software running on the system
and run the setup process again. If you do not have a virus checking program running
and you still get this error, either install the software in a new directory or delete the
contents of the existing directory and run the setup program again.
Problem Project files not portable.
Solution When you copy a project to another machine which uses a different Warp directory,
the project will not compile because it cannot find the files in the path it has stored in
the .wde file. If you delete the *.wde files in the new project directory, then Galaxy
will know where the new library files are and recreate the *.wde files.
Problem When using the Search in Files function, with the default color selection (blue)
for keywords and with the string highlighted in reverse video, the found keyword
cant be read.
Solution The user needs to set their graphic card to more than 256 colors to be able to see
strings that have been found. Another solution is to set the colors in Edit -> Prefer-
ences to colors that wont cause problems.
Warp Release 6.3
Known Problems and Solutions:
WKPS.63 Page 9 of 16 July 8, 2002
Problem I cannot launch Active-HDL Sim or the FSM editor from Galaxy->Tools menu.
Solution This happens when you terminate Active-HDL Sim installation during installation or
the Active-HDL Sim installation was not successful. If you have terminated the
Active-HDL Sim installation because you already have the Active-VHDL product,
you can launch Active-VHDL from outside Galaxy. If you do not have Active-VHDL,
make sure that the Warp installation program successfully installs Active-HDL Sim
and/or Active-HDL FSM. Make sure to reboot after installation.
Problem Incorrect handling of nested procedures.
Solution Warp currently does not support procedures that are nested in other statements. You
will have to re-code your design to use either a function or invoke the procedure with-
out any nesting in the concurrent section of the architecture.
Problem When I try to compile hierarchical designs, I get the error: Abort: (E39) Need
to recompile '%s', even though the source files are compiled in the correct order.
Solution This happens when Warp thinks that the lower level .vif files are out of date. When this
happens, recompile the file listed in the error message and then compile the project. If
you get this message after recompiling the lower level files, delete the dependency file
<top_level_file>.wde in the current project directory and re-compile the project.
Problem The Verilog compiler gives the error: Cannot handle expr '%s' here. Expecting
one or both operands to be constants
Solution Warp does not support datapath inferencing inside Verilog functions/tasks when both
the operands are non-constants. When you encounter this error, modify your design
such that the datapath operators inside functions/tasks have at least one constant oper-
and or move the code that involves datapath operators to outside the functions/tasks.
Problem When the Verilog design contains too many parameters, the tovif module crashes.
Solution Currently Warp has a limitation on the number of parameters that it can handle and the
length of the parameter name(s). Even though it is legal in Verilog to use parameters to
define constants and parameterized modules, we recommend to use the parameters
only to write parameterized modules. If your design has too many constants, define the
constants using the `define compiler directive instead of a parameter statement. This
reduces the number of parameters in a design.We also recommend that the length of
your parameter names be shortened.
Warp Release 6.3
Known Problems and Solutions:
WKPS.63 Page 10 of 16 July 8, 2002
Problem A design that successfully fits with pins floated, fails to fit when the pin assign-
ment given by the fitter is back-annotated into the design.
Solution This rare situation can occur due to partitioning and routing constraints. In certain sit-
uations, back-annotating the internal nodes and recompiling the design will solve this
problem. (Ultra37000 only)
Problem Cannot use same name for a signal and component.
Solution Avoid using the same name for both a signal and a component within the same
architecture. This is legal in VHDL but Warp currently has some problems with it if
you use such a signal in the port map of a component.You will see the following error:
(E59) Expected ) or ,, but got COMPONENT NAME
Problem Certain designs which generate large equations (usually due to either XOR
expansion of more than 8 levels, or the implicit complementation of equations
involving more than 10 variables and 10 product terms) may cause Warp to hang.
Solution On a schematic design, place a buffer at the appropriate place. On a VHDL/Verilog
textual design, place a synthesis_off attribute on the appropriate signal. This will
factor the signal at that point by using a device resource like a macrocell. Lowering the
Node Cost value in the Compiler Options dialog box can help in some situations.
Problem Problem with overloading of enumeration literals.
Solution In VHDL, it is perfectly legal to use the same enumeration literal in multiple type def-
initions. Warp currently does not interpret this sort of overloading properly while pro-
ducing equations for variables/signals of such types. Please define all enumerated
types so that the enumeration literal types are unique within a given scope. In the fol-
lowing two declarations, the literal idle is used in two different type declarations. In
such a case, one of the idle instances must be changed to a different name.
type enum_type1 is (idle, busy, waiting);
type enum_type2 is (idle, sending, receiving);
Problem Warp hangs (or takes a long time to compile) when designs contain large behav-
ioral up/down counters.
Solution Use the counter defined in the LPM library. This component is optimized to prevent a
combinatorial blowup during synthesis and optimization. This problem does not
appear when you have an up-only or a down-only behavioral counter.
Warp Release 6.3
Known Problems and Solutions:
WKPS.63 Page 11 of 16 July 8, 2002
Problem Warp synthesizes the tri-buf with pad fb as mode buffer (mcell fb) instead of
inout.
Solution When this happens, apply the synthesis_off directive to the signals which have this
problem or reduce the optimization level to normal (-o1) and re-compile.
Problem When I specify a ROM data file in my design source files, I get an error message
from Warp: Could not open ROM data file <file name>.
Solution Make sure that you specify the absolute path of the ROM data file in your design
source file.
Problem On the Ultra37000 devices, if more than 4 double input registers are required in a
design, the additional registers may not fit.
Solution Use node_num attribute to lock the intermediate (first input register) flip-flop into a
buried macrocell.
WKPS.63 Page 12 of 16 July 8, 2002
Warp Release 6.3 : Active-HDL Sim
Known Problems and Solutions:
The following lists known problems and their work-around solutions at the time of the Active-
HDL Sim release. These problems will be addressed in upcoming updates.
Problem When I try to compile the post-synthesis netlist in Active-HDL Sim 3.3, I get
'Unknown identifier' errors.
Solution This happens when you are using a version of Active-HDL Sim 3.3 not shipped with
Warp Release 6.3. Some of the primitive models changed in Warp Release 6.3 and the
primitive libraries have been updated. Install the version of Active-HDL Sim 3.3 that
comes with Warp Release 6.3 and re-run the simulation.
Problem When I reload my VHDL file in Aldec, I lose my stimulator assignments.
Solution Before reloading the VHDL file, save and close the waveform.
Problem I am using a simulator not shipped with Warp and when I try to do post-synthesis
simulation, the simulator gives errors.
Solution If you are using a simulator other than the one that comes with Warp, make sure that
you recompile the primitive libraries in the target simulator before doing the post-syn-
thesis simulation. This is needed because the simulation models may change between
different versions of Warp.
Problem Where are the waveform files I saved in my previous sessions?
Solution In this release, the File->Open Waveform... menu item doesnt open in the current
working directory. If the waveform was saved in the default Aldec directory, these
waveforms are saved in the directory <proj_dir>\vhd\XXX\src. XXX is the directory
created in the vhd directory by the Aldec tool when you initiate a simulation session
by double-clicking on your XXX.vhd file. When the File->Open Waveform is used for
the first time, it does not go to the src directory. Browse to the directory src to
locate the waveform files.
Problem While compiling the post-synthesis VHDL file, the simulator complains that it
cannot find some libraries.
Solution This happens when the Active-HDL Sim is installed under Windows NT on an NTFS
volume and read-write privileges have not been granted to all the users. The solution is
make sure that the Active-HDL Sim directory structure has read-write privileges for
all the users.
WKPS.63 Page 13 of 16 July 8, 2002
Warp Release 6.3 : Active-HDL Sim
Known Problems and Solutions:
Problem I cannot print waveforms from Active-HDL Sim.
Solution This is not a bug. It is caused when the correct print driver is not installed. Please try to
print with non-postscript print driver(s) installed on your PC.
Problem When I install Active-HDL Sim alone from the Warp CD and run Active-HDL
Sim, I get framework errors.
Solution This is not a bug. After installing Active-HDL Sim, please make sure that you reboot
the PC before running Active-HDL Sim the first time.
Warp Release 6.3: Professional/Enterprise
Known Problems and Solutions:
WKPS.63 Page 14 of 16 July 8, 2002
The following are known problems and their work-around solutions at the time of Warp Release
6.3. These problems will be addressed in upcoming releases.
Problem When I try to load pre-6.2 release schematics with the cy_fifo symbol drawn in
the BDE, I get compilation warnings/errors.
Solution First, select Design -> Update Symbols. Second, select Design -> Update Diagrams.
Then save the updated schematic before compiling in the Active-HDL CY
environment.
Problem My VHDL project will not compile when attribute statements are used in the
source code.
Solution Include the following code in the library declaration section and recompile:
library cypress;
use cypress.cypress.all;
Problem When I try to simulate PSI designs, the simulator gives the error: Divide by zero.
Solution The PSI device simulation models need femto second (fs) resolution. Please change
your simulator resolution to 'fs' and re-run the simulation.
Problem If I try to use any of the Cypress specific packages, the Active-HDL Compiler
gives the error: Can not find <design unit> in the library 'work'.
Solution While using the Cypress specific packages, make sure that you specify the 'cypress'
library explicitly instead of work. For example, if you are using the statement like
"use work.std_arith.all;" change this to "library cypress; use cypress.std_arith.all;"
Problem When I try to do pre-synthesis simulation of a Verilog project, the simulator gives
the following error: Only l-value NET expression is allowed for OUTPUT/
INPUT port.
Solution This happens when a signal of type reg is connected to an output port of an instanti-
ated component. Change the signal type to wire instead of reg and recompile.
Problem Control file constraints do not appear to be applied.
Solution Ensure that the control file has the same prefix as the top level file and that it is located
either in the projects top level directory or in the Synthesis sub-directory.
Warp Release 6.3: Professional/Enterprise
Known Problems and Solutions:
WKPS.63 Page 15 of 16 July 8, 2002
Problem During pre-synthesis compilation, I get one of the following error messages:
Unknown indentifier zero or Unknown identifier one .
Solution In VHDL, change all signal value assignement references from zero and one to '0'
and '1'. In Verilog, change all signal value assignment references from zero and
one to 1'b0 and 1'b1.
Problem When I have test bench files created outside the testbench wizard, they do not
compile successfully in Warp.
Solution If you have testbench files created outside the testbench wizard, these files need to be
marked as TestBench files. Otherwise they will be treated as part of the design and
Warp will try to synthesize these files. To mark the file as a testbench file, choose the
file in the design browser, click the right mouse button and select Properties. Depend-
ing on the language, set the file type to 'VHDL Testbench' or 'Verilog Testbench' by
using the pull down menu.
Problem When my Verilog designs include 'lpm.v' file, I get an error message from Warp:
Could not open include file 'lpm.v'.
Solution Make sure that you specify the absolute path name (<your warp installation direc-
tory>/lib/common/lpm.v) in the include statement.
Problem When I specify a ROM data file in my design source files, I get an error message
from Warp: Could not open ROM data file <file name>.
Solution Make sure that you specify the absolute path of the ROM data file in your design
source file. When the absolute path name is specified, use '/' or '\\' as directory separa-
tors or include the ROM file in the project manager and mark the file type as internal.
Problem When I try to implement the Hex2Bin design in the sample designs; I get an error
message: error copying <filename.pfg> to <filename.pfg>: no such file or
directory.
Solution This is due to some extra entries (generated from previous runs of the tool) in the
project file. Open the project file <warp install/Active-HDL_40CY/projects/Hex2Bin/
hex2bin.adf> and delete the lines that contain: cy_proj_file, cy_proj_dir, cy_device.
Save the file and re-run the implementation.
Warp Release 6.3: Professional/Enterprise
Known Problems and Solutions:
WKPS.63 Page 16 of 16 July 8, 2002
Problem When I edit a file and attempt to Compile/Implement the design, Warp compiles
an old version of the file.
Solution The current version of the software doesnt support the AutoSave feature. Whenever
you make changes to a file, save the file before attempting to compile/implement the
design.
Problem During installation of Warp Professional/Enterprise, I was given an option to reg-
ister six file extensions with Warp Professional/Enterprise. Currently, even if I
deselect a file extension, it will still become registered.
Solution After completing installation, open up the Windows Explorer. Select View->Options.
Then select the file types tab. Look through the list of the currently registered file
extensions and deselect the extensions that you do not want to be registered.