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Opcode-Field Address-Field
where , , , and are five main memory locations representing five variables;
3-address format: Assume variables A, B, C, D, and X are stored in MM locations labeled by their names.
MUL X R1 R2 #
X [R1] [R2]
where src1 and src2 are the source operand, dst is the destination operand, and * represents the
operation specified in Op-code field OP.
• 2-address format:
MOV R1 A # R1 [A]
ADD R1 B # R1 [B] + [R1]
MOV R2 C # R2 [C]
ADD R2 D # R2 [D] + [R2]
MUL R2 R1 #
R2 [R1] [R2]
MOV X R2 # X [R2]
•
•
•
•
• where src is the source operand, dst is the destination operand, and * represents the operation specified
in Op-code field OP.
• 1-address format:
LOAD A # AC [A]
ADD B # AC [AC] + [B]
STORE R # R [AC]
LOAD C # AC [C]
ADD D # AC [AC] + [D]
MUL R #
AC [AC] [R]
STORE X # X [AC]
• 0-address format:
used in stack-organized computer. First, the given notation of the operation is converted into ``reversed
PUSH A
PUSH B
ADD
PUSH C
PUSH D
ADD
MUL
POP X
o Stack A last-in, first-out (LIFO) data structure.
o Queue A first-in, first-out (FIFO) data structure.
Instruction Format:
An instruction is one, two, or three halfwords in length and must be located in main storage on an integral
halfword boundary. Each instruction is in one of five basic formats: RR, RX, RS, SI, and S. Some instructions
contain fields that vary slightly from the basic format, and in some instructions the operation performed does
not follow the general rules stated in this section. All such exceptions are explicitly identified in the individual
instruction descriptions. The format names express, in general terms, the classes of operands which participate
in the operation: RR denotes a register-to-register operation; RX. a register-and-indexed-storage operation; RS,
a register-and-storage operation; SI, a storage-and- immediate operation. The S format denotes an operation
using all implied operand and storage. The first byte and, in the S format, the first two bytes of an instruction
contain the operation code (op code). For some instructions in the S format, all or a portion of the second byte is
ignored. The first two bits of the operation code specify the length and format of an instruction, as follows:
In the format illustration for each individual instruction description. the opcode field shows the opcode in
hexadecimal representation. The hexadecimal representation uses one graphic for a four-bit code, and therefore
two graphics for an eight-bit code. The graphics 0-9 are used for the codes 0000 - 1001 ; the graphics A-F are
used for codes 1010 - 1111. The remaining fields in the format illustration for each instruction are designated by
code names, consisting of a letter and possibly a subscript number. The subscript number denotes the operand to
which the field applies.
Instruction Format
The MIPS R2000/R3000 ISA has fixed-width 32 bit instructions. Fixed-width instructions are common for
RISC processors because they make it easy to fetch instructions without having to decode. These instructions
must be stored at word-aligned addresses (i.e., addresses divisible by 4). The MIPS ISA instructions fall into
three categories: R-type, I-type, and J-type. Not all ISAs divide their instructions this neatly. This is one reason
to study MIPS as a first assembly language. The format is simple.
R-type
R-type instructions refer to register type instructions. Of the three formats, the R-type is the most complex. This
is the format of the R-type instruction, when it is encoded in machine code.
B31-26 B25-21 B20-16 B15-11 B10-6 B5-0
opcode register s register t register d shift amount function
the order of the registers in the instruction is the destination register ($rd), followed by the two source registers
($rs and $rt). However, the actual binary format (shown in the table above) stores the two source registers first,
then the destination register. Thus, how the assembly language programmer uses the instruction, and how the
instruction is stored in binary, do not always have to match.
I-type instructions
I-type is short for "immediate type". The format of an I-type instuction looks like:
B31-26 B25-21 B20-16 B15-0
opcode register s register t immediate
J-type instructions
J-type is short for "jump type". The format of an J-type instuction looks like:
B31-26 B25-0
opcode target
j target
The semantics of the j instruction (j means jump) are:
PC <- PC31-28 IR25-0 00
where PC is the program counter, which stores the current address of the instruction being executed. You
update the PC by using the upper 4 bits of the program counter, followed by the 26 bits of the target (which is
the lower 26 bits of the instruction register), followed by two 0's, which creates a 32 bit address. The jump
instruction will be explained in more detail in a future set of notes.
One way to reduce the total number of operands is to make one operand both a source and a destination
register. Another approach is to use an implicit register.