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# 25

CHAPTER 3
2008 Pearson Education, Inc.
3-1.
3-2.*
3-3.
3-4. a) For the 3 x 3 pattern, there are exactly three row, three column and two diagonal combinations that
represent a win for the X player: W = X1 X2 X3 + X4 X5 X6 + X7 X8 X9 + X1 X4 X7 + X2 X5 X8 + X3 X6 X9
+ X1 X5 X9 + X3 X5 X7 Gate Input cost = 32
b) W = X5 (X1 X9 + X2 X8 + X3 X7 + X4 X6) + X1 X2 X3 + X1 X4 X7 + X7 X8 X9 + X3 X6 X9 Gate Input Cost = 30
3-5. a) For the 4 x 4 pattern, there are exactly four row, four column and two diagonal combinations that represent a
win for the X player: W = X1 X2 X3 X4 + X5 X6 X7 X8 + X9 X10 X11 X12 + X13 X14 X15 X16 + X1 X5 X9 X13
X2 X6 X10 X14 + X3 X7 X11 X15 + X4 X8 X12 X16 + X1 X6 X11 X16 + X4 X7 X10 X13 Gate Input cost = 50
b) W = X1(X2 X3 X4 + X5 X9 X13 + X6 X11 X15) + X7(X5 X6 X8 + X3 X11 X15 + X4 X10 X13) + X9 X10 X 11 X12
+ X13 X14 X15 X16 + X2 X6 X10 X14 + X4 X8 X12 X16 Gate Input Cost = 48
X
Y
Z
1 1
F = XZ + XY + YZ
1
This is the same function as the
1
Place a 1 in each K-map cell where 2 or more inputs are equal to 1.
A
B
C
D
1 1
1 1 1 1
F = AB + AC

W=A B C D + A B C D
1
1
00
01
11
10
00 01 11 10
AB
CD

1
1

1
X =A B C D + A B C + A B D
1
00
01
11
10
00 01 11 10
AB
CD

1

1
1
Y =A B (C D + C D) + A B(C D + C D)
1
00
01
11
10
00 01 11 10
AB
CD

1
1 1

Z =A B D + B C D + A B D
1
1
00
01
11
10
00 01 11 10
AB
CD

26
Problem Solutions Chapter 3
3-6.
3-7.
+
3-8.
X1 X2 X3 Z
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Z X1 X2 X3 =
a) Detecting a change in one-out-of-
Z X1 X2 X3 =
three inputs can be done using a
parity function as Z. The truth
table shown is for even parity.
For this case,

If odd parity is chosen, then an
alternative result for Z is:
ABCD GNS YNS RNS GEW YEWREW
0000 1 0 0 0 0 1
0001 1 0 0 0 0 1
0011 1 0 0 0 0 1
0010 1 0 0 0 0 1
0110 1 0 0 0 0 1
0111 1 0 0 0 0 1
0101 0 1 0 0 0 1
0100 0 0 1 0 0 1
1100 0 0 1 1 0 0
1101 0 0 1 1 0 0
1111 0 0 1 1 0 0
1110 0 0 1 1 0 0
1010 0 0 1 1 0 0
1011 0 0 1 1 0 0
1001 0 0 1 0 1 0
1000 0 0 1 0 0 1
GNS AC AB + =
YNS ABCD =
GEW AB AC + =
YEW ABCD =
REW A BCD + =
A
B
C
D
YNS
B
A
C
GNS
B
C
D
A
REW
B
A
C
GEW
A
B
C
D
YEW
RNS A BCD + =
B
C
D
A
RNS
A B C S5 S4 S3 S2 S1 S0
0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 1
0 1 0 0 0 0 1 0 0
0 1 1 0 0 1 0 0 1
1 0 0 0 1 0 0 0 0
1 0 1 0 1 1 0 0 1
1 1 0 1 0 0 1 0 0
1 1 1 1 1 0 0 0 1
S0 = C
S1 = 0
S2 = ABC + ABC
S3 = ABC + ABC
S5 = AB
S4 = AB + AC
27
Problem Solutions Chapter 3
3-9.
+
3-10.
3-11.
A B C D S2 S1 S0
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 1 0
0 1 0 0 0 1 0
0 1 0 1 0 1 0
0 1 1 0 0 1 0
0 1 1 1 0 1 1
1 0 0 0 0 1 1
1 0 0 1 0 1 1
1 0 1 0 0 1 1
1 0 1 1 0 1 1
1 1 0 0 0 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 1 0 0
S0 = B C D + B C D + AB + AC D + ABCD
S1 = AB + AB + ACD + BC D
S2 = ABC + ABD
A B C D W X Y Z
0 0 0 0 0 1 1 0
0 0 0 1 0 1 1 1
0 0 1 0 1 0 0 0
0 0 1 1 1 0 0 1
0 1 0 0 1 0 1 0
0 1 0 1 1 0 1 1
0 1 1 0 1 1 0 0
0 1 1 1 1 1 0 1
1 0 0 0 1 1 1 0
1 0 0 1 1 1 1 1
1010 to
XXXX
1111
W = A + B + C
X = B C + BC
Y = C
Z = D
PS LS RS RR PL LL RL
0 0 0 0 0 0 0
0 0 0 1 0 0 0
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 0 1 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 1 0
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 1 0 0
1 0 1 1 1 0 0
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 1 0 0
PL = PS
LL = PS LS RS + PS LS RR
RL = PS LS RS + PS RS RR

a)
b)
PS
LS
RS
RR
RL
PL
LL
28
Problem Solutions Chapter 3
3-12.
3-13.
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
1
1
1
1
1
1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 1
1 1
1
1
1 1
1
1
1
a = AC + A B D + ABD + AB C
b = A B + B C + A C D + ACD
c = AB + B C + AD
d = ABCD + AB C + A B D + A BC + ACD
e = B C D + ACD
f = AB C + ABD + ABC + A C D
g = AB C + ABC + A BC + ACD
Total gate inputs for this solutions = 74. Total gate inputs for book solution is 70. The book solution is better by 4 gate inputs.
a)
c) The following gate input counts include input inverters and share AND gates.
b)
a c d
a
b
e g f
X
Y
Z
W=XZ + YZ
Hierarchy
X
Y
Z
W
Hierarchy
X
Y
Z
W
Hierarchy
X
Y
Z
W
Hierarchy
X
Y
Z
W
A
B
C
D
E
G = B(CE + DE) + BC
F = A(CE + DE) + AD
29
Problem Solutions Chapter 3
3-14.
3-15.
+
3-16.
Hierarchy
X
Y
Z
H
A
B
C
D
Hierarchy
X
Y
Z
H
Hierarchy
X
Y
Z
H
BC+BD
BC+BD
G = A(BC + BD) + A(BC + BD)
= ABC + ABD + ABC + ABD
A
B
C
D
E
F
G
A
B
C
D
E
F
G
a) b)
c)
Part b requires 6 fewer gates.
H H
a) Original circuit
A
B
C
D
E
F
G
A
B
C
D
E
F
G
b) Replacement with equivalents
A
B
C
D
E
F
G
c) Cancel inverters
30
Problem Solutions Chapter 3
3-17.
3-18.
a) Original circuit
A
B
C
D
E
F
G
A
B
C
D
E
F
A
B
C
D
E
F
b) Replacement with equivalents
c) Manipulate inverters
A
B
C
D
E
F
d) Cancel inverters
G
G
G
a) Original circuit
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
b) Replacement with equivalents
A
B
C
D
E
F
G
H
c) Manipulate inverters
A
B
C
D
E
F
G
H
d) Cancel inverters
31
Problem Solutions Chapter 3
3-19.
3-20.
3-21.
G
H
a) Original circuit
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
A
B
C
D
E
F
c) Manipulate inverters
d) Cancel and minimize inverters
G
H
A
B
C
D
E
F
T1
T2
T3
F
X
Y
T1 = X Y
T2 = X Y
T3 = X Y
F = XY + X Y
G1
G2A
G2B
E
E G1 G2A G2B =
Y0 ABCE =
Y1 ABCE =
Y2 ABCE =
Y3 ABCE =
Y4 ABCE =
Y5 ABCE =
Y6 ABCE =
Y7 ABCE =
Except for G1 = 1 and G2A and G2B = 0,
the outputs Y0 through Y7 are all 1s. Oth-
erwise, one of Y0 through Y7 is equal to 0
with all others equal to 1. The output that is
equal to 0 has index i = decimal value of
the values of (A,B,C) in binary. E.g., if
(A,B,C) = (1,1,0), then Y6 = 0.
32
Problem Solutions Chapter 3
3-22.
3-23.
3-24.*
3-25.
11111111
01111111 10111111 11011111 11101111 11110111 11111011 11111101 11111110
11111111
0 100 200 300 400 500 600
A
B
C
G1
G2A_n
G2B_n
Y 11111111
01111111 10111111 11011111 11101111 11110111 11111011 11111101 11111110
11111111
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
0 20 40 60 80 100 120 140 160
A
B
C
D
W
X
Y
Z
10 11 12 13 14 15
F
7
F
6
F
5
F
4
F
3
F
2
F
1
F
0
VDD
a) b)
G
7
G
6
G
5
G
4
G
3
G
2
G
1
G
0
A
A
0
1
A
A
1
1
F
7
F
6
F
5
F
4
F
3
F
2
F
1
F
0
VDD
a) b)
G
7
G
6
G
5
G
4
G
3
G
2
G
1
G
0
F
A
VDD
8
3
0
2
1

33
Problem Solutions Chapter 3
3-26.
3-27.
3-28.
a) b)
F
12
11
9
G
6
5
3
G(3:0)
F(3:0)
4
4 H
8
7:4
3:0
4
1
2
0
7
5
3
1
A S
0
S
1
S
2
S
3
S
4
S
5
( ) M + =
L A =
V A S
0
S
1
S
2
S
3
S
4
S
5
( ) M + = =
C V =
M
S
5
A
S
3
S
2
S
1
S
0
S
4
L
V
C
A
0
A
1
A
2
A
3
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
DECODER
0
1
2
3
A
0
4
5
6
7
A
1
A
2
DECODER
0
1
2
3
A
0
4
5
6
7
A
1
A
2
34
Problem Solutions Chapter 3
3-29.
3-30.*
A
0
A
1
A
0
A
1
A
0
A
1
A
0
A
1
A
0
A
1
DECODER
0
1
2
3
EN
A
0
A
1
DECODER
0
1
2
3
En
A
0
A
1
DECODER
0
1
2
3
En
A
0
A
1
DECODER
0
1
2
3
En
A
0
A
1
DECODER
0
1
2
3
En
A
2
A
3
EN
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
A
0
A
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
DECODER
0
1
2
3
A
0
4
5
6
7
A
1
A
2
DECODER
0
1
2
3
A
0
A
1
A
3
D
16
A
4
A
2
D
17
D
19
D
20
D
18
D
21
D
23
D
25
D
22
D
24
D
26
D
27
D
28
D
29
D
30
D
31
35
Problem Solutions Chapter 3
3-31. (Errata: Replace 4 with 3 in 4-to-6-line decoder)
3-32.
3-33.
D
0
D
1
D
2
D
3
D
4
D
5
A
0
A
1
A
2
A
0
A
1
DECODER
0
1
2
3
A
0
DECODER
0
1
X
2
X
1
X
0
a) The Truth Table:
X
2
X
1
X
0
a b c d e f g
0 0 0 d d d d d d d
0 0 1 0 0 0 1 0 0 0
0 1 0 1 0 0 0 0 0 1
0 1 1 1 0 0 1 0 0 1
1 0 0 1 1 0 0 0 1 1
1 0 1 1 1 0 1 0 1 1
1 1 0 1 1 1 0 1 1 1
1 1 1 d d d d d d d
b) A = {d}
B = {a,g}
C = {c. e}
D = {b, f}
X
2
X
1
X
0
X
2
X
1
X
0
X
2
X
1
X
0 A
B C
D = X
2
1
1
1
d 1
1 1
1 1
d
d d
d
d
d
d
1
1
1
1
A = X
0
B = X
1
+ X
2
C = X
1
X
2
D
Gate input cost: b = 4 compared to a = 27 + 11 = 38
X
0
X
1
X
2
DECODER
0
1
2
3
A
0
4
5
6
7
A
1
A
2
a
g
b
f
c
e
d
Note: a = g, b = f, and c = e.
A
1
A
2
EN
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
A
0
36
Problem Solutions Chapter 3
3-34.
3-35.*
3-36.
C3
C2
C1
C0
B0
B1
DECODER
0
1
2
3
A
0
4
5
6
7
A
1
A
2
A
3
8
9
10
11
12
13
14
15
B2
B3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
K-Map for GE5: BCD = (C3,C2, C1, C0)
1 1 1
1 1
d d d d
d d
GE5 = C3 + C2 (C1 + C0)
GE5
C0
C1
C2
C3
P0
P1
P2
P3
P4
P5
P6
P0
P0
P0
Equations for output logic:
P0 = D0 + GE5D1
P1 = D2 + GE5D1
P2 = D3 + GE5D4
P3 = D5 + GE5D4
P4 = D6 + GE5D7
P5 = D8 + GE5D7
P6 = D9 + GE5D10
P7 = D11 + GE5D10
P8 = D12+ GE5D13
P9 = D14 + D15 + GE5D13
D
3
D
2
D
1
D
0
A
1
A
0
V
0 0 0 0 X X 0
X X X 1 0 0 1
X X 1 0 0 1 1
X 1 0 0 1 0 1
1 0 0 0 1 1 1
V D
0
D
1
D
2
D
3
+ + + =
A
0
D
0
D (
1
D
2
) + =
A
1
D
0
D
1
=
D
3
D
2
D
1
D
0
1
1
1
D
3
D
2
D
1
D
0
A
1
A
0
X
1
1
1 X
1
1
D
0
D
1
D
2
D
3
A
1
A
0
V
Decimal Inputs Binary Outputs
9 8 7 6 5 4 3 2 1 0 A
3
A
2
A
1
A
0
V
0 0 0 0 0 0 0 0 0 0 X X X X 0
0 0 0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 0 0 0 0 0 1 X 0 0 0 1 1
0 0 0 0 0 0 0 1 X X 0 0 1 0 1
0 0 0 0 0 0 1 X X X 0 0 1 1 1
0 0 0 0 0 1 X X X X 0 1 0 0 1
0 0 0 0 1 X X X X X 0 1 0 1 1
0 0 0 1 X X X X X X 0 1 1 0 1
0 0 1 X X X X X X X 0 1 1 1 1
0 1 X X X X X X X X 1 0 0 0 1
1 X X X X X X X X X 1 0 0 1 1
37
Problem Solutions Chapter 3
3-37.
3-38.
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
a) b)
S
2
S
0
S
1
S
2
DECODER
0
1
2
3
A
0
4
5
6
7
A
1
A
2
Y
4x1 MUX
0
1
2
3
S
0
Y
S
1
S
0
S
1
I
4
2x1 MUX
S
Y
I
5
I
6
I
7
4x1 MUX
0
1
2
3
S
0
Y
S
1
S
0
S
1
I
0
I
1
I
2
I
3
0
1
Y
A
0
A
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
DECODER
0
1
2
3
A
0
4
5
6
7
A
1
A
2
A
3
8
9
10
11
12
13
14
15
A
2
A
3
Y
38
Problem Solutions Chapter 3
3-39.
3-40.
I
A7
I
A6
I
A5
I
A4
I
A3
I
A2
I
A1
I
A0
S
0
S
1
S
2
DECODER
0
1
2
3
A
0
4
5
6
7
A
1
A
2
Y
A
I
B7
I
B6
I
B5
I
B4
I
B3
I
B2
I
B1
I
B0
Y
B
S
0
A
0
DECODER
0
1
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
S
1
S
2
S
3
DECODER
0
1
2
3
A
0
4
5
6
7
A
1
A
2
Y
I
8
I
9
I
10
I
11
39
Problem Solutions Chapter 3
3-41.
3-42.*
3-43.*
8x1 MUX
D
(7:0)
Y
0
S
(2:0)
8x1 MUX
D
(7:0)
Y
0
S
(2:0)
8x1 MUX
D
(7:0)
Y
0
S
(2:0)
8x1 MUX
D
(7:0)
Y
0
S
(2:0)
2x1x4 MUX
D
0,0
D
0,1

D
0,2
D
0,3
D
1,0
D
1,1

D
1,2

D
1,3

Y
0

Y
1

Y
2

Y
3

S
A
3
D
0(8)
D
1(8)
D
2(8)
D
3(8)
D
0(7:0)
D
1(7:0)
D
2(7:0)
D
3(7:0)
A
(2:0)
D
0(9)
D
1(9)
D
2(9)
D
3(9)
2x1x4 MUX
D
0,0
D
0,1

D
0,2
D
0,3
D
1,0
D
1,1

D
1,2

D
1,3

Y
0

Y
1

Y
2

Y
3

S
A
0
O
0
O
1
O
2
O
3
8x1 MUX
D
(7:0)
Y
0
S
(2:0)
8x1 MUX
D
(6:0)
Y
0
S
(2:0)
D(7:0)
D(14:8)
D
(7)
A(2:0)
A(3)
3 OR gates
A
1
A
0
E D
0
D
1
D
2
D
3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
Consider E as the data input and A0, A1 as the
select lines. For a given combination on (A1,
A0), the value of E is distributed to the corre-
sponding D output. For example for (A1, A0) =
(10), the value of E appears on D2, while all other
outputs have value 0.
40
Problem Solutions Chapter 3
3-44.
3-45.
3-46.
DECODER
0
1
2
3
A
0
4
5
6
7
A
1
A
2
Z
Y
X
F
1
F
3
F
2
BL
BR
DECODER
0
1
2
3
A
0
4
5
6
7
A
1
A
2
A
3
8
9
10
11
12
13
14
15
EM
LT

a) LR = LTBL + LTBR + EMBL = BL(LT + EM) + LTBR
RR = RTBL + RTBR + EMBL = BR(RT + EM) + RTBR
b) Maximum of four inputs on OR gates assumed.
LR
For RR, same circuit with LT replace by RT.
LT EM BR BL LR
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
A B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
F = 0
F = D
F = D
F = 0
8 x 1 MUX
D
0
D
1

D
2
D
3
D
4
D
5

D
6

D
7

Y
S
0
S
1
C
B
F
D
VDD
S
2
A
F = D
F = D
F = 1
F = D
41
Problem Solutions Chapter 3
3-47.*
3-48.
A B C D F
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
F=D
F=C D
F=C D
F=1
B
F
VDD
A
4 x 1 MUX
D
0
D
1

D
2
D
3
Y
S
0
S
1
C
D
DECODER
0
1
2
3
A
0
4
5
6
7
A
1
A
2 B
C
D
F
EN
DECODER
0
1
2
3
A
0
4
5
6
7
A
1
A
2
EN
B
C
D
A