BLUECHIP TECHNOLOGIES

VLSI 2014 IEEE TITLES

S.NO CODE PROJECT TITLE YEAR
1 VL01 Use of SSTA Tools for Evaluating BTI Impact on
Combinational Circuits
201
2 VL02 !n "ea#loc$ %roblem of !n&C'ip Buses Supporting !ut&of&
!r#er Transactions
201
( VL0( "ela) Test for "iagnosis of %o*er S*itc'es 201
VL0 "esign +lo* for +lip&+lop ,rouping in "ata&"riven Cloc$
,ating
201
- VL0- En'ance# .emor) /eliabilit) Against .ultiple Cell Upsets
Using "ecimal .atri0 Co#e
201
1 VL01 2ig'&/esolution All&"igital "ut)&C)cle Corrector in 1-&nm
C.!S Tec'nolog)
201
3 VL03 Incremental Trace&Buffer Insertion for +%,A "ebug 201
4 VL04 LASIC5 Loop&A*are Sleep) Instruction Cac'es Base# on
STT&/A. Tec'nolog)
201
6 VL06 Lo*&Comple0it) /econfigurable +ast +ilter Ban$ for .ulti&
Stan#ar# 7ireless /eceivers
201
10 VL10 Lo*&%o*er %ulse&Triggere# +lip&+lop "esign Base# on a
Signal +ee#&T'roug' Sc'eme
201
11 VL11 A 128-&,B9S !:&C2I% !SCILL!SC!%E T! .EASU/E
E;E "IA,/A.S A:" <ITTE/ 2IST!,/A.S !+ 2I,2&
S%EE" SI,:ALS
201
12 VL12 %ULSE"&LATC2 UTILI=ATI!: +!/ CL!C>&T/EE
%!7E/ !%TI.I=ATI!:
201
1( VL1( BUILT&I: BI:A/; C!"E I:VE/SI!: TEC2:I?UE +!/
!:&C2I% +LAS2 .E.!/; SE:SE A.%LI+IE/ 7IT2
/E"UCE" /EA" CU//E:T C!:SU.%TI!:
201
1 VL1 Soft*are92ar#*are %arallel Long&%erio# /an#om :umber
,eneration +rame*or$ Base# !n T'e 7ell .et'o#
201
#7, KRISHNA COMPLEX, OPP TO DAILY DHANTHI, ERODE. 9962064074/94977977
BLUECHIP TECHNOLOGIES
1- VL1-
Variation&A*are Variable Latenc) "esign
201
11 VL11 !n&C'ip .emor) 2ierarc') In !ne Coarse&,raine#
/econfigurable Arc'itecture To Compress .emor) Space An#
To /e#uce /econfiguration Time An# "ata&/eference Time
201
13 VL13 !n T'e Automatic ,eneration !f !ptimi@e# Soft*are&Base#
Self&Test %rograms +or Vli* %rocessors
201
14 VL14
Ultra&2ig' T'roug'put Lo*&%o*er %ac$et Classification
201
16 VL16 Lig't&7eig't !n&C'ip Structure +or .easuring Timing
Uncertaint) In#uce# B) :oise In Integrate# Circuits
201
20 VL20 A S)nergetic Use !f Bloom +ilters +or Error "etection An#
Correction
201
21 VL21 An Accurac)&A#Austment +i0e# 7i#t' Boot' .ultiplier Base#
!n .ultilevel Con#itional %robabilit)
201
22 VL22 +%,A Base# Bit Error /ate %erformance .easurement !f
7ireless S)stems
201
2( VL2(
2ar#*are Efficient .i0e# /a#i0&2-91196 +ft +or Lte S)stems
201
2 VL2
2ig'&T'roug'put An# Lo*&Comple0it) Bc' "eco#ing
201
2- VL2-
A /eal&Time .otion&+eature&E0traction Vlsi Emplo)ing
201
21 VL21
Lo*&Comple0it) 2ar#*are "esign for +ast Solving LS%s
7it' Coor#inate# %ol)nomial Solution
201
23 VL23 Lo*&Energ) T*o Stage Algorit'm +or 2ig' Efficac) Epileptic
Sei@ure "etection
201
24 VL24
"esign an# Implementation of .o#ifie# Signe#&"igit A##er
201
26 VL26
Area&"ela) Efficient Binar) A##ers in ?CA
201
WE SOLVE YOUR NEW IDEAS/CONCEPTS ALSO
#7, KRISHNA COMPLEX, OPP TO DAILY DHANTHI, ERODE. 9962064074/94977977