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2.1 HS-PDSCH: High speed physical downlink shared channel
This channel transports the physical downlink traffic to the UEs and
uses a shared concept, i. e. there can be several UEs receiving data on
the common used channel. Fig. 2-3 below outlines the structure of the
HS-PDSCH.
J Spreading factor 16
J Assignment of multiple channelization codes to one UE possible
Slot 0
Slot 1
Slot 2
T
slot
= 2560 chips
HS-DSCH:
transport channel
with user data
1 subframe of 3 slots: 2 ms
HS-PDSCH:
physical channel
320 bits for QPSK, 640 bits for 16QAM
Fig. 2-3 HS-PDSCH structure.
Source: [TS 25.211, Ref. 20], reproduced by permission of 3GPP.
The HS-PDSCH always uses a spreading factor of 16. Due to its shared
channel structure, the WCDMA Rel-99 concept of a variable spreading
factor must be discontinued. Multiple channelization code allocation is
possible to increase the throughput. Using a spreading factor of 16 rep-
resents an optimization of the efficiency. Recalling the effect of code
blocking in WCDMA with the CPICH and P-CCPCH always blocking
the codes C
ch, SF, 0,
it is clear that the definition of a constant spreading
factor of 16 represents a good compromise between reduced signaling
effort (i. e. if a spreading factor >16 were used, the higher layer proto-
cols would require more signaling overhead to indicate the amount of
multiple codes) and the total available physical resources (i. e. if a
spreading factor <16 were used, the code blocking effect would reduce
the remaining capacity within a cell). A side effect is that the spreading
factor itself is not signaled to the UE, and only the number of codes is
contained in the control information. The physical channel HS-PDSCH
carries a transport block that is delivered by the transport channel
HS-DSCH within a TTI of 2 ms. This time is also constant and no flex-
ibility is allowed. The flexible values on the HS-PDSCH are the modu-
lation scheme (QPSK or 16QAM) and the transport block size, i. e. the
amount of data bits contained in one HS-DSCH transport block. This
is set by the puncturing scheme and indicated as the redundancy ver-
30
HSDPA operation overview and physical channels
sion. Additionally, the redundancy version can be changed, meaning
the puncturing procedure can be executed in different ways. If the UE
category allows, HS-DSCH transport blocks can be scheduled to the
UE continuously, i. e. in every TTI. Less complex UEs corresponding to
a lower UE category can only process data received in every second or
even every third TTI. This is described by the so-called inter-TTI dis-
tance parameter; see section 2.8, page 79 for further details. An
inter-TTI distance of 1 corresponds to continuous HS-PDSCH trans-
mission (assuming data is available for transmission). An example of
the maximum amount of multiple channelization codes used for
HS-PDSCH is shown in Fig. 2-4. Here, all of the 15 possible channeliza-
tion codes for spreading factor 16 are assigned, but as can be seen, this
already occupies most of the available resources provided by the NodeB.
SF = 1 SF = 2 SF = 4 SF = 8 SF = 16 SF = 32 SF = 64 SF = 128 SF = 256
2,0
2,1
4,0
8,0
16,0
32,0
64,0
128,0
256,1
16,1
8,1
4,1
4,2
4,3
1,0
64,1
128,1
8,2
8,3
256,0 All possible HS-PDSCH codes
Possible HS-SCCH codes (example)
CPICH
P-CCPCH
Blocked
256,3
256,2
128,2
128,3
256,7
256,6
256,5
256,4
32,1
64,2
128,4
256,9
64,3
128,5
256,11
256,10
128,6
128,7
256,15
256,14
256,13
256,12
256,8
64,62
128,124
256,249
64,63
128,125
256,251
256,250
128,126
128,127
256,255
256,254
256,253
256,252
256,248
32,30
32,31
16,2
16,3
16,4
16,5
16,6
16,7
16,8
16,9
8,4
8,5
16,10
16,11
16,12
16,13
8,6
8,7
16,14
16,15
The code word C(x) is now obtained by appending the check word to
the data word.
C(x) = x
nk
D(x) + R(x)
The receiver knows the generating polynomial G(x) and performs the
division C(x)/G(x). If there are no transmission errors, the code word
C(x) is divisible by G(x). The probability is therefore high that any
errors will be detected. The maximum number of errors per code word
that can be detected is determined by the length of the check word,
which in our case is the length of the CRC. But what is not known is the
position of those errors and thus there is no way to correct them. This
is the responsibility of the inner error correction such as the attach-
ment of redundancy bits which enable the receiver to correct some bit
errors. Note that block codes can also be used in general to correct
errors, but this is not performed in HSPA because this would increase
the overall latency time.
Error correction performed with forward error correction (FEC),
principle of convolutional coding
With forward error correction (FEC), redundant bits are inserted into
data packets (bursts) at the transmitting end to enable the receiving
end to implement a correction mechanism. The assumption is that the
errors do not occur in a burst. Here, the principle of a convolutional
coder is used. This type of coder remembers the last n bits sent and
adds each input bit to the stored n bits. The words obtained at the out-
put are usually longer than one bit. The code rate defines the ratio of
the input bits to the output bits, for example a coder using a code rate
of generates for each input bit a code word of two output bits. Error
correction is based on the fact that a previous state, i. e. a word or a bit
36
HSDPA operation overview and physical channels
sequence can only assume one of two succeeding states depending on
whether 0 or 1 was entered into the coder, i. e. the decoder decides for
the metric providing the minimum error estimation. If a word arrives
at the receiver in a state that cannot be reached from a state obtain-
able from one of the two input combinations, a transmission error has
occurred and needs to be corrected. This procedure is equivalent to
tracing a path through a trellis diagram which is familiar from cod-
ing theory.
We would now like to discuss a brief example to demonstrate the func-
tionality of channel coding and the subsequent steps of puncturing.
Please note that this example does not represent the real coders used
in HSDPA. Consult the relevant literature for further details of cod-
ing theory, [Ref. 10], [Ref. 11] and [Ref. 14] as well as the specification
[TS 25.212, Ref. 21] which describes the coding applied in HSPA.
The convolutional coder shown in Fig. 2-8 consists of one input fol-
lowed by three registers in a shift configuration and finally two out-
puts. With each clock generation, the content of each register is shifted
one register to the right as the last registers content is discarded and
a new input bit is inserted into the first register. The outputs 1 and 2
are generated by an XOR operation between the linked register con-
tents. In this manner, we create a finite response filter and a certain
memory effect. Lets assume we want to transmit the following input bit
sequence: 110110 0/1. Here, the nomenclature 0/1 means that the last
bit of our contemplated sequence can be either 0 or 1 and we wish to
consider both alternatives. The registers are initialized with all 0s, and
typically some tail bits are attached to the code word which will ensure
this for the succeeding code word. The table in Fig. 2-8 shows the input
bit on the left side, the register sequence content after each step and
outputs 1 and 2 on the right side. The output sequence for the given
input will be 11 01 01 00 01 01 11/00. Note the last two lines in the table.
We do assume an either / or, i. e. there are two alternatives such that
alternative A means that after the sequence 110110 has been sent to the
coder, the following bit will be logical 0. Alternative B means that after
the sequence 110110, the following bit will be a logical 1. So we present
an either / or situation. This will be used to explain the coding principle.
HS-DSCH: High speed downlink shared channel, transport channel
37
Example of convolutional coding
Input Regis-
ter 1
Regis-
ter 2
Regis-
ter 3
Out-
put 1
Out-
put 2
XOR operation
Register 3 Register 2 Register 1
+
Input
Output 1
Output 2
+ +
1 1 0 0 1 1
1 1 1 0 0 1
0 0 1 1 0 1
1 1 0 1 0 0
1 1 1 0 0 1
0 0 1 1 0 1
Alt. A 0 0 0 1 1 1
Alt. B 1 1 0 1 0 0
Fig. 2-8 Simple example for convolutional coding.
In Fig. 2-9 that follows, there is a trellis diagram representing in each
column the four possible output values of our channel coder 00, 01, 10
or 11 and in bold color there is the trellis path through this diagram
resulting from the input sequence. Recalling our definition of the two
alternatives for the last bit of our example code word, we can see that
the rightmost part of this trellis diagram shows the two possible steps.
From state 01, we can only reach either state 00 or state 11. The two
other states 01 or 10 are not possible, and with no input to the coder
shown in Fig. 2-8 the output can reach these two states in this step. For
example, if the receiver detects a sequence such as 11 01 01 00 01 01 01,
it knows there is an error at the last position 01 which had to be cor-
rected as either 00 or 11 because only these two alternatives are pos-
sible. The error correction is performed by looking at the total trellis
path and selecting the maximum likelihood sequence estimation based
on the received data pattern. In our short example, we admit that we
stopped at this point, of course. Imagine that the input sequence of bits
continues: The decoder would not know if it should proceed with the
pattern 00 or 11 so the decision will be to continue both ways. The fol-
lowing step is then checked again and one of the assumed ways will dif-
fer more from the demodulated pattern than the other one. This prin-
ciple is described in the Viterbi algorithm [Ref. 15]. Based on this algo-
rithm, the stronger path will survive, i. e. the decoder checks at each
step which path of the examined ones in the trellis path exhibits the
smallest deviation from the demodulation sequence and thus this path
will be continued. The paths exhibiting a higher deviation are discarded
to reduce the calculation expense. The path through the trellis diagram
is called a metric and the term maximum likelihood sequence esti-
mation (MLSE) represents the selection by the channel decoder of the
real possible metric which is the closest to the received data pattern. As
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HSDPA operation overview and physical channels
an analogy: If we do a crossword puzzle and find some characters in a
word, the channel decoder would check in a primer or dictionary of the
language containing all possible character combinations that we call
words and select the existing word that has the maximum likelihood
for the prevailing sequence of characters.
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Alternative B
Alternative A
Register 2
+ +
+
Output 1
Output 2
XOR operation
Trellis diagram above shows
metric for input sequence:
110110 0 or 1
into a coder such as:
1
1
0
1 1
0
0
1
Register 3 Register 1
Fig. 2-9 Metric in trellis diagram.
Interleaving
Forward error correction based on convolutional coders has one disad-
vantage related to the impact of block errors. If the transmission errors
are distributed, they can be corrected as demonstrated in the trellis dia-
gram example using the Viterbi algorithm, but if many adjacent bits
are lost, the decoder will have problems retrieving the right bit pattern.
Interleaving means that the information to be transmitted is spread or
distributed over several bursts in such a way that contiguous informa-
tion is split up and transmitted in a time or block distributed mode.
To avoid error bursts, an attempt is made to spread the bit errors over
several code words. This is achieved by interleaving several code words.
This method is also called diagonal interleaving; see Fig. 2-10. Another
kind of interleaving is block interleaving as shown in Fig. 2-11. Blocks
of code words are written row-by-row into a matrix and then read col-
umn-by-column. With both methods, consecutive bits of a code word
are never transmitted consecutively, and conversely, when the bits are
deinterleaved at the receive end, error bursts are spread over several
code words.
HS-DSCH: High speed downlink shared channel, transport channel
39
As several code words are interleaved, the decoder has to wait a cer-
tain time until all bits of a particular code word arrive. This delay, i. e.
the measure for spreading over time is referred to as the interleav-
ing depth. The greater the interleaving depth, the more code words are
available for spreading the error bursts and the greater the probability
that errored bits can be corrected, but on the other hand this increases
the overall latency time.
HSDPA uses the block diagonal interleaving principle for the HS-DSCH
only since, as we should recall, one goal is to have a short round-trip
time.
Spreading
Interleaving
HS-PDSCH
(2 T
slot
= 5120 chips)
HS-SCCH
HS-PDSCH
Fig. 2-18 Timing relation between HS-SCCH and HS-PDSCH.
Source: [TS 25.211, Ref. 20], reproduced by permission of 3GPP.
Content of the HS-SCCH control channel
The control information contained in the HS-SCCH control chan-
nel has already been mentioned, so we will now consider the values
in more detail. We will begin with an overview of what kind of control
information is contained in the HS-SCCH channel before proceeding
with further details about the single control elements. The following
control information is present in the HS-SCCH [TS 25.212, Ref. 21]:
Channelization code set information (7 bits)
Modulation scheme information (1 bit)
Transport block size information (6 bits)
Hybrid ARQ process information (3 bits)
Redundancy and constellation version (3 bits)
New data indicator (1 bit)
UE identity (16 bits) = H-RNTI
High speed shared control channel (HS-SCCH)
49
Some of these parameters are more or less self-explanatory, while oth-
ers require additional background information and closer examination.
Modulation scheme information, 1 bit
This single bit is used to inform the receiver whether the modulation
scheme QPSK or 16QAM is applied on the data channel HS-PDSCH.
The interpretation of the bit x
ms,1
is as follows:
ms,1
x
if QPSK
otherwise
0
1
=