Memristor based Programmable Threshold Logic

Array
Jeyavijayan Rajendran, Harika Manem, Ramesh Karri and Garrett S. Rose
Department of Electrical and Computer Engineering
Polytechnic Institute of New York University, Brooklyn, NY - 11201
{jrajen01,hmanem01}@students.poly.edu,{rkarri,grose}@duke.poly.edu
AbstractIn this work, we utilized memristors in the realiza-
tion of power and area efcient programmable threshold gates.
Memristors are used as weights at the inputs of the threshold
gates. The threshold gates are programmed by changing the
memristance to enable implementation of different Boolean
functions. A new threshold gate-array architecture is proposed
and evaluated for power, area and delay metrics. The CAD set-
up that was utilized in the evaluation of the aforementioned
architecture, can also be used to analyse the performance of
emerging computing technologies. The proposed architecture
achieves an average power reduction of 75% and area (transistor
count) reduction of 75% when compared to look-up-table (LUT)
based logic with some delay penalty.
I. INTRODUCTION
Although the memristor, or memory resistor, was rst
theorized by Leon Chua in 1971 [1], it was fabricated by
HP Labs memristors [2], [3] only recently. A memristor is
a device whose resistance changes based on the history of the
voltage applied across its terminals and hence can be thought
of as a recongurable resistor. Memristance is an electronic
device property that could lead to new ways of thinking about
electronic devices, circuits, logic and system architectures.
Memristors can have potential applications as memory, as
digital logic building blocks, as analog circuit building blocks
and as neuromorphic building blocks.
Memristors can be used to build threshold circuits, logics
and systems which are the basis for neural computing. In the
past, threshold gates have been implemented using CMOS
devices [4][6], negative resonant devices and, single electron
devices [7][9] and monostable-bistable logic elements [10],
[11]. A survey of these threshold logic implementations can be
found in [12]. A threshold logic synthesis tool was developed
[13] and a neuro-morphic architecture based on threshold logic
was proposed [14]. While threshold logic provides powerful
computational properties beyond Boolean logic its implemen-
tation in CMOS and other logics is expensive.
In this paper, we leverage the memristance property to
implement low-power and area, programmable threshold gates.
We implemented Boolean logic using these programmable
threshold gates and showed that these implementations con-
sume less power and area when compared to their imple-
mentation using CMOS look-up-tables (LUTs). To evaluate
the power, performance and area overhead of threshold logic
implementation, we used a CAD framework that includes:
CAD tools from Cadence to model memristors and mem-
ristor based threshold gates,
a simple algorithm to determine the memristance values
required to implement a Boolean function, and
Berkeley SIS logic synthesis tool to map Boolean func-
tions onto threshold logic gates.
II. MEMRISTORS
A. Theory
Leon Chua proposed a fourth fundamental device, the
memristor, which relates charge q and ux in the following
way [1]:
M(q) =
d((q))
dq
The parameter M(q) denotes the memristance of a charge
controlled memristor, measured in ohms. It has been observed
that the memristance at any particular instance depends on
the integrals of the current and the voltage through the device
from to that instance. Thus, the memristor behaves like
an ordinary resistor at any given instance, where its resistance
depends on the complete history of the device [1], [3].
B. Experimental Devices
Strukov et al. [2], [3], describe the fabrication of nanoscale
memristor devices. The memristance behaviour was observed
for TiO
2
metal-oxides based devices [3]. A TiO
2X
layer
with oxygen vacancies is placed on a perfect TiO
2
layer,
which are sandwiched between platinum wires. The experi-
mental memristor fabricated by HP has memristances in the
range 121 K-121 M. In all of these materials, the switching
from R
off
to R
on
and vice-versa, occurred as a result of ion
migration due to the enormous electric elds applied across
the nanoscale structures.
C. Modeling
The charge transport in metal-oxide memristors is based
on a form of atomic rearrangement, which adjusts the overall
resistance of the device as a function of electric current. In
this work we are considering devices that have symmetric
behaviour for positive and negative voltages applied across it.
For modeling purposes, a thin lm metal-oxide of thickness
D sandwiched between two conductors is modeled as two
variable resistors connected in series. Each resistor in the
model represents two distinct regions of the metal-oxide, one
5 978-1-4244-8018-0/10/$26.00 c 2010 IEEE
with a high ionic dopant concentration, R
on
, and the other
with a low concentration, R
off
. Assuming x is the length of
the high concentration region and that x is allowed to vary
from 0 to D, the memristance can be modeled as [2], [3],
[15]:
M(x) = R
on
x +R
off
(D x)
There can be different values for the memristance M as x
varies from 0 and D.
Some of the properties of the memristors, based on this
linear drift velocity model are:
1) When a positive (negative) voltage difference is applied
across the memristor over a period of time, its memris-
tance will change to R
on
(R
off
).
2) A memristor can be controlled to exhibit any value of
resistance between R
on
and R
off
by controlling the
amplitude and the duration of the voltage.
3) At low frequencies, the memristor exhibits the hysteresis
property and at high frequencies it behaves like a linear
resistor.
The rst property can be exploited for digital applications
like threshold logic while, the third property can be leveraged
for analog applications like frequency ltering. In this work,
we leverage the second property, to set the weights for the
programmable threshold gates. The second property can be
viewed as programming the memristor to a particular memris-
tance value using voltage and time as the programming agents.
III. THRESHOLD GATES USING MEMRISTORS
The output of a threshold gate depends on the weighted sum
of its inputs. The output is high, only when this weighted sum
is greater than a specied threshold. For a generic threshold
logic gate if w
i
is the weight for input x
i
, T is the threshold,
then the output Y is:
Y =

0 if w
i
x
i
< T
1 if w
i
x
i
T
The key idea: We use memristors as weights of the inputs
to a threshold gate. For a threshold gate using memristors as
weights, if V
i
and Mem
i
are the the voltage and memristance
at the input i, then the output Y is,
Y =

0 if
Vi
Memi
< I
ref
1 if
Vi
Memi
I
ref
The voltages applied at the inputs to a threshold gate are
converted into current values which are then summed up by
connecting all the wires together. This sum of all weighted
currents is then compared with a threshold or reference current
I
ref
. The memristance value can be selected by applying an
appropriate voltage over a period of time.
A three input threshold gate using memristors as weights
is shown in Fig. 1. A simple threshold circuit which can be
designed using a PMOS current mirror, can sum up the current
owing through the memristor and compare it with I
ref
. There
Isolator
Period
extender
Pulse shaper
Iref
A
B
C
MA
MB
MC
Current
mirror
Vout
Current
mirror
Vinv
N
Current
mirror
Current
comparator
Pulse shaper
1
2 3 4
CLK
Fig. 1: Circuit diagram of a 3-input threshold gate. The memristors
act as weights. is a current mirror to prevent reverse ow of current,
is an isolator to prevent loading, is a period extender to retain
input pulse period, and is a pulse shaper to retain memristance.
are four problems of such a straightforward memristor based
threshold gate. Hence additional circuits as shown in Fig. 1
are necessary.
1) Current can ow from the output to the input of the
circuit. To prevent this current ow in the reverse
direction, we add a 2 transistor current mirror on each
input line.
2) The current comparator can be loaded by the next stage.
To prevent this we add a 2-transistor isolation circuit.
3) In the proposed threshold gate, we represent a logic 1 as
a positive pulse followed by a negative pulse (the reason
will be explained in the pulse shaper sub-section). The
current mirror and the isolation circuitry function only
during the positive pulse and clip-off the negative pulse.
Even though the isolator gives the functional output of
the threshold gate, the pulse period of the input is not
fully restored. We use a period extender circuit to restore
the negative pulse immediately following the positive
pulse to represent the logic 1. The period extender
consists of a latch that uses 4 CMOS transistors and
a CLK signal.
4) When a threshold gate operates one has to make sure
that its weights do not change, because a change in
the weights can alter its functionality. However, a con-
stant voltage applied across the memristor will alter
the memristance with a function of time. To overcome
this problem, we use 0V to represent a logic 0 and a
positive pulse followed by a negative pulse to represent a
logic 1. The negative pulse will reverse any changes to
the memristance during the positive pulse. We use a six
transistor pulse shaper circuit to generate this pattern.
The pulse shaper consists of a pass transistor and a level
shifter. The pass transistor transmits a 0V to represent
a logic 0. The level shifter generates a positive pulse,
when the output of the period extender is HIGH and the
CLK signal is HIGH. It generates a negative pulse, when
the output of the period extender is HIGH and the CLK
signal is LOW. The output of the pulse shaper feeds the
input of the next threshold gate. There is a similar pulse
shaper for the inverted output V
inv
.
In general an N-input threshold gate needs (2 n) + 18
transistors. For example, a 3 -input threshold gate requires
6 2010 IEEE/ACM International Symposium on Nanoscale Architectures
24 transistors.
IV. THRESHOLD GATE ARRAY ARCHITECTURE
Metal 1
Metal 2
Contacts/Vias
Memristor
Fig. 2: One possible layout of the proposed architecture. Memristors
are at the junction of the metal 1 and metal 2 wires shown black
boxes. The output of one gate (CMOS layer) drives inputs of multiple
memristors, which are at the input of different gates. The metal 1 to
metal 2 via is shown in white boxes.
A physical layout of a single threshold gate is shown in
the Fig. 2. The gure shows an inverter feeding three current
mirror circuits of the next stage. The metal-oxide memristors
at the junction of the metal 1 and metal 2 layers, can be created
in the place of vias from metal 1 to metal 2, at required places.
The metal 1 and metal 2 layers can be used to form orthogonal
wires that comprise a crossbar island.
CM
CM
CM
CM
CM
CM
CM CM CM
IL
PE
PS
Interconnection network
I
n
t
e
r
c
o
n
n
e
c
t
i
o
n
n
e
t
w
o
r
k
A 3-input threshold gate
IL
PE
PS
IL
PE
PS
Fig. 3: An island of threshold gates. Each column corresponds to a
single threshold gate and the number of rows determine the fan-in of
the threshold gate. A single threshold gate is shown within a dotted
box. IL refers to isolator, CM refers to current mirror, PE refers to
period extender and PS refers to pulse shaper.
The Fig. 3 shows a 33 crossbar based island architecture.
It consists of three 3-input threshold gates. Each threshold gate
has 2 outputs one complemented and the other uncomple-
mented. The crossbar is constructed by running two adjacent
metal wires perpendicular to each other. The memristors at
the junction of the metal wires are associated with current
mirror circuits which prevents the sneak-paths. Each column
corresponds to a threshold gate and the number of rows
determine the number of inputs to a threshold gate. In the
above island, a threshold gate can have upto three inputs.
Each column sums up the current from the current mirrors
and feeds to the comparator. The inputs to an island come
from the interconnection network on the left and the outputs
of this island appear at the bottom interconnection network.
Similarly, islands of 4- and 5- input threshold gates can be
constructed. The limitation to this island architecture is the
maximum number of threshold gates (fan-out) that the pulse
shaper can drive. The fan-out of the threshold gate of the
previous stage determines the number of columns permissible
in an island.
ISLAND 1
Output
I
n
p
u
t
ISLAND 2 ISLAND 3
ISLAND 4 ISLAND 5
ISLAND 6
Fig. 4: A cascaded architecture using two rows of islands. The
unshaded box corresponds to an island of threshold gates. The lightly
shaded box corresponds to an interconnection network.
Fig. 4 shows a cascaded architecture formed using the
threshold gate islands. Each island is connected to the next
island through an interconnection network. The interconnec-
tion network selects certain outputs from the previous stage
as inputs to the next stage. The primary inputs are applied to
the left-most island and the outputs are obtained at the right-
most island. The cascaded architecture can be extended to any
number of islands without any signal degradation; the period
extender and pulse shaper provides signal and memristance
restoration. The programming circuitry consists of a pulse
generator to program the memristor. The discussion of the
programming circuitry is beyond the scope of this paper.
V. EXPERIMENTAL VALIDATION
Modeling of
memristor
(Matlab,VerilogA)
Circuit level design of a
threshold gate
(Cadence Spectre)
Mapping on to a threshold gate,
and characterization
(SKILL, Cadence Spectre)
Boolean logic synthesis using
threshold gates
(SIS)
List of 2-, 3-, 4-, and 5 -
input Boolean functions
Boolean logic
benchmarks
(.blif)
Library of mapped gates
(.genlib)
System level
performance
Fig. 5: Design ow
2010 IEEE/ACM International Symposium on Nanoscale Architectures 7
Threshold 3 1 2 3 2 Common threshold = 6 Reference current I
ref
= (0.8A)
Weights Adjusted weights for the common threshold Memristance (K)
Functions ABC A+B+C AB+BC+CA AB+AC A+BC ABC A+B+C AB+BC+CA AB+AC A+BC ABC A+B+C AB+BC+CA AB+AC A+BC
Input A 1 1 1 2 2 2 6 3 4 6 1200 400 800 600 400
Input B 1 1 1 1 1 2 6 3 2 3 1200 400 800 600 400
Input C 1 1 1 1 1 2 6 3 2 3 1200 400 800 600 400
TABLE I: The rst row shows the threshold for all ve 3-input different functions, the common threshold calculated with their LCM using
steps 9 11 in algorithm 1 and the threshold current I
ref
. The third row shows the list of 3-input Boolean functions. The weights column
show the raw weights and the adjusted weights column shows the weights adjusted to the common threshold calculated using steps 13 16
in algorithm 1. In the memristance column, the three rows show the memristances calculated using steps 17 22 in algorithm 1.
We used a bottom-up CAD ow from the device level to
the system level to evaluate the performance of this architec-
ture. We used tools that are available for different hardware
abstraction levels ranging from Cadence Spectre to Berkeley
SIS.
Characterizing a memristor: We modeled individual mem-
ristors using the linear drift velocity model proposed in [2], [3],
[15]. This model holds good, when the applied electric eld
is within the range of 10
6
. Since we are using memristors for
low voltage applications, this model holds good in our case.
The device model of the memristor is written in VerilogA
hardware description language. The physical parameters for
the memristors such as its thickness, the R
on
and R
off
resistance values are obtained from the device fabricated by
HP [3]. A memristor test circuit was designed and analysed
for various inputs ranging from AC voltages of different
amplitudes and frequencies to DC and other voltage signals.
Output current waveforms are measured and compared with
theoretical and experimental data.
Circuit level design of a threshold gate: We developed a
circuit-level model for the threshold gate as shown in Fig.
1 using Cadence Spectre. Berkeley Predictive Technology
Models (PTM) were used for 45nm node CMOS transistors
[16].
Mapping Boolean functions onto threshold gates and
characterization: All Boolean logic functions that can be im-
plemented using a 3-input, 4-input and 5-input threshold gates,
are listed in [17]. The proposed memristor-based threshold
logic gate can implement all realizable Boolean functions and
their complements. A threshold gate can be programmed to
implement a Boolean function either by changing the weights
at its inputs or by changing its threshold or both. For example
a 2-input threshold gate with threshold 2, implements an
AND gate if the weights at its inputs are 1 and implements
an OR gate if the weights are changed to 2. In the proposed
threshold gate, we x the threshold and use an algorithm to
tune the weights of different functions on a common threshold
scale and to map the weights to the acceptable memristance
values. Table I shows the values of all 3-input Boolean
functions, that are calculated using the above algorithm. For
each of these Boolean functions, the memristors are congured
with the corresponding memristance values and circuit level
simulations are run.
The memristors are set to a memristance value by adjusting
Algorithm 1 Adjusting weights and calculating the memristances
for a xed threshold
1: B number of Boolean functions that can be implemented by
an N input threshold gate
2: Ti threshold of the i
th
Boolean function
3: Wi,j weight at the j
th
input of the i
th
Boolean function
4: Tc common threshold
5: W
r
i,j
adjusted weight at the j
th
input of the i
th
Boolean
function
6: W
r
min,N
minimum of the adjusted weights of for all the N-
input Boolean functions
7: Memi,j memristance at the i
th
input for the j
th
Boolean
function
8: Memmax The maximum value of memristance that can be
used as a weight
{Calculate common threshold}
9: for i = 1 to B do
10: Tc = LCM of {Ti,Tc}
11: end for
{Adjusted weights}
12: for i = 1 to B do
13: for j = 1 to N do
14: W
r
i,j
= Wi,j
Tc
T
i
15: end for
16: end for
17: W
r
min,N
= Minimum(W
r
i,j
) i : 1 to B, j : 1 to N.
18: W
r
min,N
= Memmax
{Calculate memristance}
19: for i = 1 to B do
20: for j = 1 to N do
21: Memi,j = Memmax
W
r
min,N
W
r
i,j
22: end for
23: end for
its parameter which corresponds to the history of voltage
applied across the memristor. We used the Cadence scripting
language SKILL to congure the memristors, run the simu-
lations and obtain the respective power and delay values for
each function. Since the proposed threshold gate implements
a function and its complement, the total power consumption
includes the power consumed to implement the function and
its complement.
The power consumption, transistor count and delay for some
of the Boolean functions are listed in table II. For a given
number of inputs, the power consumption differs only slightly
from one function to another. The power consumption varies
with the number of inputs due to change in the reference
8 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Function Power Transistor Delay
(W) count (ns)
AB 27.9 22 6.1
A+B 26.5 22 6.1
ABC 38.2 24 6.1
A+B+C 35.4 24 6.1
AB+BC+CA 36.8 24 6.1
AB+AC 36 24 6.1
ABCD 43.1 26 6.1
A+B+C+D 42 26 6.1
A+BC+BD+CD 42.1 26 6.1
AB+AC+BC+AD+CD+BD 42.2 26 6.1
ABCDE 45.9 28 6.1
A+B+C+D+E 45.5 28 6.1
ABC+ABDE 45.7 28 6.1
ABC+ABD+ABE+ACDE+BCDE 45.5 28 6.1
TABLE II: Power, transistor count, and delay for some 2-, 3-, 4-,
and 5-input Boolean functions. The power consumption is the power
consumed by a function and its complement. The transistor count
includes the number of transistors required to implement a function
and its complement.
current (threshold). The transistor count includes the number
of transistors required to implement a function and its com-
plement.
The delay through the threshold gate is independent of the
number of inputs because the effect of input loading is masked
by the current mirror circuits. The delay is dominated by the
RC delay caused by the memristance and the input capacitance
of the CMOS current mirror. To have an upper bound on delay,
the maximum permissible memristance value that can be used
as weight in threshold gate is xed at 1.2 M (i.e. Mem
max
= 1.2 M in algorithm 1). A lower value for the memristance
upper bound was not chosen as it would highly constrain the
range of weights for the threshold gate. Memristance value
greater than 1.2 M will increase the delay. Furthermore,
this circuit delay give the minimum duration of the positive
pulse generated by the pulse shaper. Since the amplitudes of
positive pulse and the negative pulse are 1.1V and 0.55V
respectively, the duration of the negative pulse is twice the
duration of the positive pulse. This is because, due to circuit
level limitations of CMOS gates, a maximum negative voltage
that can be achieved was 0.55V . The clock period is the sum
of the duration of the positive and negative pulses. Since the
maximum memristance that we used for the 2-, 3-, 4- and 5-
input Boolean functions is 1.21 M, .This memristance causes
a RC delay of 2.03ns and so the duration of positive pulse is
2.03ns. The duration of negative pulse is 2 2.03 = 4.06ns.
The clock period is 2.03 + 4.06 = 6.1ns and its constant for
all the threshold gates for the given circuit parasitics.
The power and delay information for all 2-, 3-, 4- and 5-
input Boolean functions that can be implemented using thresh-
old gates are obtained from Cadence Spectre simulations. A
SKILL script is written to create a library of mapped gates
which contains the power and delay information of different
Boolean functions implemented using threshold gates. This
library is similar to .genlib format [18] with the only difference
being that the area eld is replaced with the power data.
Logic synthesis: Netlist of the ISCAS-85 combinational
benchmarks in .blif format are synthesized for the developed
library of mapped gates using the Berkeley SIS 2.0 [18] logic
synthesis tool. They are then mapped to the designed threshold
gates and the power, gate count and delay are calculated.
VI. COMPARISON WITH SRAM-BASED 4-INPUT LUT
We compared the threshold gate using memritors with a 4-t
LUT. We considered a SRAM-based 4-input LUT and eval-
uated its performance using the same design ow described
above. The design of a 4-input LUT, generation of library of
mapped gates and logic synthesis using them follow the same
design ow as shown in Fig. 5 except for the memristor model.
The 4-input LUT consists of sixteen SRAM cells and
three 2-input multiplexers. The power consumption of a 4-
input LUT cell is computed as: (1 access power of SRAM
+15 static power of SRAM cell +3 power of 2-inpuit
multiplexer). Access power of a single 45nm-SRAM cell is
30W [19] and static power of a 45nm-SRAM cell is 50nW
[20]. From Spectre simulations, a 2-input multiplexer from
the 45nm OSU-standard cell library, consumes 45.17W. The
power of a single 4-input LUT is calculated as 168W. The
delay of the 4-input LUT is the sum of the access time of
SRAM cell and the multiplexer delay. The access time of a
SRAM cell is 450ps. The delay of a 2-input multiplexer from
Spectre simulations, is found to be 50ps. Hence, the total delay
of 4-input LUT is 500ps.
ISCAS-85 combinational benchmarks are mapped on to the
4-input LUT. Logic synthesis using SIS was done to get the
power, delay and transistor count data for the implementation
using 4-input LUT. We are neglecting the interconnection
network for this analysis.
A. Power
0
50
100
150
200
250
300
350
C17 C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552
P
o
w
e
r

(

W
)
Benchmarks
4-input LUT 5- input TL gate
4 -input TL gate 3-input TL gate
Fig. 6: Power consumption for different benchmarks. TL gate refers
to threshold logic gate using memristors. There is an average power
reduction of 75% when compared with 4-input LUTs.
Fig. 6 shows the power consumed by the benchmarks
implemented using the 3-,4- and, 5-input threshold gates and
4-input LUTs. A 3-input threshold gate can implement both
2- and 3-input Boolean functions. A 4-input threshold gate
can implement 2-, 3- and 4-input Boolean functions. A 5-
input threshold gate can implement 2-, 3-, 4- and 5-input
Boolean functions. It can be seen the power reduces by nearly
2010 IEEE/ACM International Symposium on Nanoscale Architectures 9
75% for almost all the circuits considered. Since the power
consumption of a single threshold gate is less when compared
to a single 4-input LUT the proposed architecture achieves
low power consumption.
B. Area (Transistor count)
0
50
100
150
200
250
300
C17 C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552
T
r
a
n
s
i
s
t
o
r

c
o
u
n
t

Benchmarks
4-input LUT 5- input TL gate
4 -input TL gate 3-input TL gate
10
3
Fig. 7: Transistor count for different benchmarks. TL gate refers to
threshold logic gate using memristors. There is an average transistor
reduction of 75% when compared with 4-input LUTs.
Figure 7 shows the transistor count of the proposed archi-
tecture and SRAM based 4-input LUT architecture. It can be
seen that the area is reduced by 75% on average. A single
threshold gate gives both complemented and uncomplemeted
outputs which reduces the overall gate count in the threshold
gate based architecture. A 5-input threshold gate requires
28 transistors but a SRAM based 4-input LUT requires 126
transistors. The logic density provided by the threshold gate
for the same number of transistors is high when compared to
4-input LUT . This vast difference in the number of transistors
required gives the proposed architecture an added advantage.
C. Delay
The delay of the proposed architecture depends on clock
frequency for the threshold gate. Thus, the delay of the
threshold gate is almost 12 times the delay of the 4-input LUT.
This is main cause for such high delay is that the memristance
and the CMOS are interfaced directly. This causes a RC delay
at the input of the current mirror as explained previously.
Furthermore, the level shifter provides only a negative voltage
of 0.55V across a memristor, compared to the positive
voltage of 1.1V . Hence, to maintain the memristance state, the
duration of the negative voltage should be twice the duration of
the positive voltage. By making the amplitude of the negative
voltage equal to the to the amplitude of the positive voltage
the duration of both pulses would be the same, which further
reduce the delay of the threshold gate.
VII. CONCLUSION
An area and power efcient threshold architecture using
memristors is realized. The power consumption and effective
area footprint are reduced by approximately 75% in compari-
son to CMOS based LUTs. However, there is a delay penalty.
The increase in delay can be attributed to the integration of
nano-scale devices exhibiting memristance with bulk silicon.
Use of alternate technologies such as nanowire FETs will be
considered in the future to reduce the effective delay. Future
work will also involve study of different methodologies to
program the weights of the threshold gates with minimal
power and delay overhead.
VIII. ACKNOWLEDGEMENTS
This work was supported by the National Science Founda-
tion (EMT/NANO 0829824).
REFERENCES
[1] L. Chua, Memristor-the missing circuit element, IEEE Transactions
on Circuit Theory, vol. 18, no. 5, pp. 507 519, Sep. 1971.
[2] R. Williams, How we found the missing Memristor, IEEE Spectrum,
vol. 45, no. 12, pp. 28 35, dec. 2008.
[3] D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, Nature,
vol. 453, pp. 8083, 2008.
[4] J. M. Quintana, M. J. Avedillo, R. Jim enez, and E. Rodrguez-Villegas,
Practical low-cost CPL implementations threshold logic functions,
Proceedings of the Great Lakes symposium on VLSI, pp. 139144, 2001.
[5] Y. Leblebici, F. Gurkaynak, and D. Mlynek, A compact 31-input
programmable majority gate based on capacitive threshold logic, IEEE
International Symposium on Circuits and Systems, vol. 2, pp. 105 108,
1998.
[6] Y. Leblebici, A. Kepkep, F. Gurkaynak, H. Ozdemir, and U. Cilingiroglu,
A fully pipelined programmable real-time (3 times;3) image lter based
on capacitive threshold-logic gates, Proceedings of IEEE International
Symposium on Circuits and Systems, vol. 3, pp. 2072 2075, jun 1997.
[7] K. Goser, C. Pacha, A. Kanstein, and M. Rossmann, Aspects of systems
and circuits for nanoelectronics, Proceedings of the IEEE, vol. 85, no. 4,
pp. 558 573, apr 1997.
[8] C. Moffat, A Survey of Nanoelectronics, Univ. College, London, U.K.,
1994. [Online]. Available: http://ipga.phys.ucl.ac.uk/papers/rep94-2.pdf.
[9] M. Padure, C. Dan, S. Cotofana, M. Bodea, and S. Vassiliadis, Capaci-
tive threshold logic: a designer perspective, International Semiconduc-
tor Conference, vol. 1, pp. 81 84, 1999.
[10] K. Maezawa, T. Akeyoshi, and T. Mizutani, Functions and applica-
tions of monostable-bistable transition logic elements (mobiles) hav-
ing multiple-input terminals, IEEE Transactions on Electron Devices,
vol. 41, no. 2, pp. 148 154, feb 1994.
[11] K. Chen, T. Akeyoshi, and K. Maezawa, Monolithic integration of
resonant tunneling diodes and fets for monostable-bistable transition
logic elements (mobiles), IEEE Electron Device Letters, vol. 16, no. 2,
pp. 70 73, feb 1995.
[12] V. Beiu, J. Quintana, and M. Avedillo, VLSI implementations of
threshold logic-a comprehensive survey, IEEE Transactions on Neural
Networks, vol. 14, no. 5, pp. 1217 1243, sept. 2003.
[13] R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, Synthesis and Optimiza-
tion of Threshold Logic Networks with Application to Nanotechnolo-
gies, Proceedings of the conference on Design, automation and test in
Europe, p. 20904, 2004.
[14] J. Rajendran, H. Manem, and G. Rose, NDR based threshold logic
fabric with memristive synapses, IEEE Conference on Nanotechnology,
pp. 725 728, July 2009.
[15] Y. N. Joglekar and S. J. Wolf, The elusive memristor: properties of
basic electrical circuits, European Journal of Physics, vol. 30, no. 4, p.
661, 2009.
[16] Berkeley Predictive Technology Model (PTM). [Online]. Available:
http://www.eas.asu.edu/

PTM/
[17] S. Muroga, Threshold logic and its applications, 1971.
[18] Berkeley sis. [Online]. Available: http://www-cad.eecs.berkeley.edu/

pchong/sis.html
[19] S. Paul, S. Chatterjee, S. Mukhopadhyay, and S. Bhunia, A circuit-
software co-design approach for improving edp in recongurable frame-
works, IEEE/ACM International Conference on Computer-Aided De-
sign, pp. 109 112, nov. 2009.
[20] G. Razavipour, A. Afzali-Kusha, and M. Pedram, Design and analysis
of two low-power sram cell structures, IEEE Transactions on Very
Large Scale Integration (VLSI) Systems, vol. 17, no. 10, pp. 1551
1555, oct. 2009.
10 2010 IEEE/ACM International Symposium on Nanoscale Architectures