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ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
40C to 85C TSSOP PW Tape and reel SN74HC163IPWRQ1 HC163I
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.
For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
M1
G2
G4
3D
4R
1, 2T/1C3
4
13
B
Q
B
M1
G2
G4
3D
4R
1, 2T/1C3
5
12
C
Q
C
M1
G2
G4
3D
4R
1, 2T/1C3
6
11
D
Q
D
M1
G2
G4
3D
4R
1, 2T/1C3
2
LD
CK
CK
R
LD
SN74HC163Q1
4BIT SYNCHRONOUS BINARY COUNTER
SCLS584A MAY 2004 REVISED APRIL 2008
3 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic symbol, each D/T flip-flop
M1 LD (Load)
Q (Output)
G2 TE (Toggle Enable)
CK (Clock)
G4
3D
4R
1, 2T/1C3
D (Inverted Data)
R (Inverted Reset)
logic diagram, each D/T flip-flop (positive logic)
TG
TG
TG
TG
TG
TG
CK
LD
TE
LD
LD
D
R
CK
CK
CK
CK
The origins of LD and CK are shown in the logic diagram of the overall device.
SN74HC163Q1
4BIT SYNCHRONOUS BINARY COUNTER
SCLS584A MAY 2004 REVISED APRIL 2008
4 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1. Clear outputs to zero (synchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
Data
Inputs
Data
Outputs
CLR
LOAD
A
B
C
D
CLK
ENP
ENT
RCO
Q
A
Q
B
Q
C
Q
D
Async
Clear
Sync
Clear
Preset
Count Inhibit
12 13 14 15 0 1 2
SN74HC163Q1
4BIT SYNCHRONOUS BINARY COUNTER
SCLS584A MAY 2004 REVISED APRIL 2008
5 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
V
CC
Supply voltage 2 5 6 V
V
CC
= 2 V 1.5
V
IH
High-level input voltage V
CC
= 4.5 V 3.15 V V
IH
High-level input voltage
V
CC
= 6 V 4.2
V
V
CC
= 2 V 0.5
V
IL
Low-level input voltage V
CC
= 4.5 V 1.35 V V
IL
Low-level input voltage
V
CC
= 6 V 1.8
V
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
V
CC
= 2 V 1000
t/v
Catalog: SN74HC163
PACKAGE OPTION ADDENDUM
www.ti.com 24-Jan-2013
Addendum-Page 2
Military: SN54HC163
NOTE: Qualified Version Definitions: