1

Rashtreeya Sikshana Samithi Trust

R.V.COLLEGE OF ENGINEERING
(Autonomous Institution Affiliated to VTU, Belgaum)
R.V. Vidyaniketan Post, Mysore Road
Bangalore 560 059
















Scheme & Syllabus

VII & VIII Semester B.E.
ELECTRONICS & COMMUNICATION
ENGINEERING

w.e.f. 2013
2


Vision
Imparting quality technical education through research, innovation and teamwork for a lasting
technology development in the area of Electronics and Communication Engineering.
Mission
To train the Electronics & Communication Engineering graduates to meet future global
challenges.
To inculcate the quest for modern technologies in the emerging areas.
To motivate the students towards research leading to multidisciplinary innovative projects.
To impart quality technical education to produce industry-ready engineers.
To produce future leaders with cohesive teamwork.
To kindle the entrepreneurial skill amongst students for overall societal upliftment.
To create centers of excellence in the field of electronics and communication engineering
with industrial and university collaborations.




















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Program Educational Objectives (PEOs):
I. To strengthen concepts and fundamentals in mathematics, science and engineering to develop
analytical skills.
II. To prepare students for the design and development of innovative electronic systems.
III. To provide an opportunity for students to work on multidisciplinary projects there by
producing graduates who will exhibit teamwork.
IV. To provide students with an academic environment which helps in building leadership
qualities, effective communication skills and ethics needed for a successful professional
career.
V. To prepare graduates for successful career in electronics industries and R&D organizations to
solve real world problems.

Program Outcomes:
a. Ability to apply knowledge of mathematics, science and engineering to electronics and
communication engineering problems.
b. Ability to design and conduct innovative experiments.
c. Ability to analyze and work on multidisciplinary tasks.
d. Ability to use modern engineering tools, software and equipment to solve problems.
e. Ability to design and develop complete electronics system.
f. Ability to transform students into solution architects.
g. Ability to understand professional and ethical responsibility.
h. Ability to transform innovative project outcomes into patents.
i. Ability for effective communication.
j. Ability to engage in life-long learning to follow developments in electronics and
communication engineering.
k. Ability to participate and succeed in competitive examinations.






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R.V. College of Engineering, Bangalore 560059.
(Autonomous Institution, Affiliated to VTU, Belgaum)
Department of Electronics & Communication

Semester: VII SCHEME OF TEACHING & EXAMINATION
Sl.
No.
Course-
Code
Title BoS
Teaching Scheme
Hours/Week
Credits
Theory Tutorial Practical
1. 10HSS71
Intellectual Property Rights and
Entrepreneurship
HSS 3 - - 3
2. 10EC72
Analog and Mixed Mode VLSI
Design
EC 4 - - 4
3. 10EC73
Wireless Cellular Communication
(Theory & Practice)
EC 3 1 3 5
4. 10EC74 Microwave Systems EC 3 - - 3
5. 10ECF75X Elective-F EC 4 - - 4
6. 10HG7XX Elective-H* ALL 4 - - 4
7. 10ECG77X Elective-G EC 3 - - 3
8. 10ECP78 Mini Project EC - - 6 3
TOTAL 24 1 9 29

Elective-F Elective-G
10ECF751 Satellite Communication & GPS 10ECG771 Artificial Neural Network
10ECF752 Wavelets &Multirate Filter Banks 10ECG772 Testing & Testability for Digital ICs
10ECF753 ATM Networks 10ECG773 Broad Band Communication
10ECF754 Low Power VLSI Design 10ECG774 MIMO in Communication Systems

Elective-H
Sl.No. Name of the Elective BoS Code
1. Bioinformatics BT 10HG701
2. Industrial Safety & Risk management CH 10 HG703
3. Information Security CSE 10HG704
4. Disaster Management CV 10HG705
5. Automotive Electronics ECE 10HG706
6. Electro Magnetic Interference & Compatibility EEE 10HG707
7. Foundations of System Engineering IEM 10HG708
8. Cloud computing ISE 10HG709
9. Micro Electro Mechanical Systems IT 10HG710
10. Graph Theory & Applications MATHS 10HG711
11. Introduction to Aircraft Systems ME 10HG712
12. Space Technology and Applications TC 10HG714
13. Chemistry of Materials CHEMISTRY 10HG715

Semester: VIII SCHEME OF TEACHING & EXAMINATION
HSS: Humanities and Social Science * Offered by respective boards
Sl.
No.
Course-
Code
Title Bos
Teaching Scheme
Hours/Week Credits
Theory Tutorial Practical
1 10HSS81 Innovations and Social Skills HSS - - 2 1
2 10ECS82 Seminar EC - - 4 2
3 10ECP83 Project Work EC - - 40 20
TOTAL - - 43 23
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Intellectual Property Rights and Entrepreneurship

Sub. Code: 10HSS71 CIE Marks: 100
Hrs/Week: L:T:P 3:0:0 SEE Marks: 100
Credits: 03 SEE Hrs: 03

Course Learning Objectives:
At the end of the course student will be able to
Build awareness on the various forms of IPR and to educate on the link between technology
innovation and IPR.
Encourage invention, investment and innovation and disclosure of new Technology and to
recognize and reward innovativeness.
Promote linkages with industries and stimulate research through developing and utilizing
novel technologies.
Trigger the entrepreneurial thinking amongst the student community and to provide necessary
inputs and motivation for promoting entrepreneurial careers.

Unit I 08 Hrs
Introduction: Types of Intellectual Property, International Scenario in IPR: WIPO, WTO, TRIPS.
Patents: Introduction, Basic concepts, Object and value of patent law, Advantages of patent to
inventor, patentable inventions, inventions are not patentable, Over view of Patent Procedure,
Biotechnology patents and patents on computer program, Patent rights on micro-organism, plant
breeding and breeders right, protection of biodiversity, protection of traditional knowledge,
Infringement of patents and remedy for infringement, Case study for patent engineering.
Trade Secrets: Definition, Significance, Tools to protect Trade secrets in India.

Unit II 07Hrs
Trade Marks: Basic concepts, Definition, Functions, different kinds of trademarks like service
marks, collective trademarks, certification trademarks and textile trade marks, registrable and non
registrable marks, Establishing trade mark right, Good will, infringement and action for trademarks,
Passing off, Trade mark and Eco Label, Comparison with patents, industrial design and copy right,
Case Studies.

Unit III 08 Hrs
Industrial Design: basic concepts and scope and nature of rights process of registration rights,
available after registration, transfer of interest or rights. Reliefs and Remedies and Action for
infringement of the rights; Appeals, Case studies.
Copy Right: Introduction, Nature and scope, Subject matter, Related or allied rights, the works in
which copy right subsists, Rights conferred by copy right, Copy right protection in India, transfer of
copy rights, right of broad casting organizations and of performer, computer software and IPR and
Case Studies.
Cyber Laws: Co-relation to Intellectual Property.

Unit IV 07 Hrs
Entrepreneur and Entrepreneurship: Evolution of the concept of Entrepreneur, Characteristics of
an Entrepreneur, Distinction between an entrepreneur and a manager, Functions of an entrepreneur,
types of entrepreneur, Intrapreneur, Concept of Entrepreneurship ,Growth of entrepreneurship in
India, Role of Entrepreneurship in economic development, overview on entrepreneurial development
models, Case discussions on a couple of successful entrepreneurs.

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Unit V 07 Hrs
Micro Small & Medium Enterprises (MSME): Definition, Characteristics, Need and rationale,
Objectives, Scope, role of MSME in Economic Development, Advantages of MSME, Steps to start
an MSME Government policy towards MSME, Impact of Liberalization, Privatization &
Globalization on MSME, Effect of WTO / GATT. Sustainability and MSME.
Institutional Support to Entrepreneurs: Over view on National and State Agencies. Identification
of Business Opportunities: Market Feasibility studies; Technical Feasibility Studies; Financial
Feasibility Studies and Social Feasibility studies.

Reference Books:
1. P Narayan, Intellectual Property Law, Eastern Law House, New Delhi and Kolkata, 2005,
EAN: 9788171771813.
2. Prabuddha Ganguly, Intellectual Property Rights: Unleashing Knowledge Economy, Tata
McGraw Hill Publishing Company Ltd., New Delhi, 1st Edition, 2001. ISBN: 0074638602.
3. Cornesh W. R., Intellectual Property Rights Patents, Copy Right, Trade Mark, Allied Rights,
Universal Law Publishing Company Pvt. Ltd, Delhi, 2001, ISBN 0199263078.
4. S. R. Myneni, Law of Intellectual Property, Asia Law House, Hyderabad, 2001, SKU
664773841.
5. S.S. Khanka, Entrepreneurial Development, S. Chand & Co., 2008,ISBN:81-219-1801-4.
6. Poornima M Charantimath, Entrepreneurship Development & Small Business Enterprises,
Pearson Education, 2007, ISBN: 81-7758-260-7.

Recommended approach to teaching the course
The course is meant to build the awareness about the issues pertaining to IPR and their utility to
scientists and engineers. Case studies pertaining to the branch of study can be taken up for discussion
by the concerned teachers, to create the interests among the Students.

Scheme of Continuous Internal Evaluation:
CIE consists of Three Tests each for 45 marks (15 marks for Quiz + 30 marks for descriptive) out of
which best of two will be considered. In addition there will be one seminar on new topics / model
presentation etc. for 10 marks.

Scheme of Semester End Examination:
The question paper consists of Part A and Part B. Part A will be for 20 marks covering the complete
syllabus and is compulsory. Part B will be for 80 marks and shall consist of five questions
(descriptive, analytical, problems or/and design) carrying 16 marks each. All five from Part B will
have internal choice and one of the two have to be answered compulsorily.
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Analog and Mixed Mode VLSI Design

Course Code: 10EC72 CIE Marks: 100
Hrs/Week: L:T:P : 4:0:0 SEE Marks: 100
Credits: 04 SEE Hrs: 03

Course Learning Objectives:
At the end of the course student will be able to
Explain the operation of differential amplifiers and be able to analyze differential amplifier
circuits using MOSFETs.
Design and analyze single stage & multi stage OPAMP.
Analyze the stability of given system and apply the appropriate compensation technique.
Analyze the effect of sampling on continuous-time signal and system.
Develop and interpret the frequency representation of discrete-time signal and system.
Design various types of analog/digital filters.
Define the specifications for Digital to Analog converters and Mixed signal layout issues.
Evaluate the Accuracy error issues in both ADC & DAC
Apply z-transform for analysis and design of discrete-time systems.
Demonstrate the Frequency transformation in the Analog Domain and Frequency transformation
in the Digital Domain.

Unit I 10 Hrs
Review of MOS Single-stage Amplifiers, Differential Amplifiers and their Frequency
Response:
Operational Amplifiers: General considerations, One-Stage Op amps, Two-Stage Op amps, Gain
Boosting, Comparison, Input Range Limitations, Slew Rate, Power Supply Rejection.

Unit II 09 Hrs
Stability and Frequency Compensation: General considerations, Multipole Systems, Phase
Margin, Frequency Compensation, Compensation of Two-Stage Op amps, Other compensation
Techniques
Introduction to Switched-capacitor Circuits: General considerations, Sampling Switches,
Switched-Capacitor Amplifiers, Switched-Capacitor Integrator, Switched-Capacitor Common-Mode
Feedback.

Unit III 09 Hrs
Filters: Introduction to Filters, Filter Transmission, Types & Specifications, Filter Transfer
Functions, Butterworth &Chebyshev Filters, First-order & Second Order Filter Functions, The
second Order LCR Resonator, Second Order Active Filters based on Inductor Replacement.

Unit IV 10 Hrs
Data Converter Fundamentals: Analog Versus Discrete Time Signals, Converting Analog Signals
to Digital Signals, Sample-and-Hold Characteristics, Digital-to-Analog Converter Specifications,
Analog-to-Digital Converter Specifications, Mixed-Signal Layout Issues.
DAC Architectures: Digital Input Code, Resistor String, R-2R Ladder Networks, Current Steering,
Charge Scaling DACs, Cyclic DAC, Pipeline DAC.




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Unit V 09 Hrs
ADC Architectures: Flash ADC, Two-Step Flash ADC, Pipeline ADC, Integrating ADCs,
Successive Approximation ADC, Oversampling ADC.
Data Converter Modeling: Sampling and Aliasing, Quantization Noise.

Course outcomes:
Ability to apply the knowledge of MOSFETs to design practical electronic circuits.
Ability to design circuits using MOSFETs/Op Amps and to analyze and interpret the results.
Ability to apply the knowledge of compensation techniques to acquire the desired frequency
response in multi stage amplifier circuits
Ability to design filters of desired spectrum.
Ability to understand the different architectures for data conversion process and characterize
the behavior under practical considerations.

Reference Books
1. BehzadRazavi; Design of Analog CMOS Integrated Circuits; McGraw-Hill Edition;
2002;ISBN: 0-07-238032-2
2. A. Williams and F. Taylor: Electronic Filter Design Handbook; 4th edition; McGraw-Hill;
2006; ISBN: 0-07-147171-5
3. Adel S Sedra& Kenneth C Smithi, Microelectronic Circuits: Theory & Applications 5
th

Edition, Oxford University Press, 2009, ISBN:0-19-806225-7;
4. R. Jacob Baker, Harry W. Li and David E. Boyce; CMOS Circuit Design, Layout and
Simulation; IEEE Press; 2002; ISBN: 81-203-1682-7
5. R. Jacob Baker; CMOS Mixed-signal Circuit Design; IEEE Press; 2009; ISBN: 978-81-265-
1657-5

Scheme of Continuous Internal Evaluation:
CIE consists of Three Tests each for 45 marks (15 marks for Quiz + 30 marks for descriptive) out of
which best of two will be considered. In addition there will be one seminar on new topics / model
presentation etc. for 10 marks.

Scheme of Semester End Examination:
The question paper consists of Part A and Part B. Part A will be for 20 marks covering the complete
syllabus and is compulsory. Part B will be for 80 marks and shall consist of five questions
(descriptive, analytical, problems or/and design) carrying 16 marks each. All five from Part B will
have internal choice and one of the two have to be answered compulsorily.















9

Wireless Cellular Communication
(Theory & Practice)

Course Code: 10 EC73 CIE Marks: 100+50
Hrs/Week: L:T:P : 3:1:2 SEE Marks: 100+50
Credits: 05 SEE Hrs : 03 + 03

Course Learning Objectives:
At the end of the course the student should be able to
Explain the Classification of mobile communication systems.
Analyze the radio channel characteristics and the cellular principle.
Analyze the measures to increase the capacity in GSM systems- sectorization and
Spatial Filtering for Interference Reduction
Explain the basic structure and elements of a GSM system and their interfaces as well as the
identifiers of users, equipment and system areas.
Explain the GSM modulation, multiple access, duplexing, frequency hopping, the logical
channels and synchronization, GSM coding.
Analyze the entire protocol architecture of GSM - communication protocols for radio
resource management, mobility management, connection management at the air interface the
mechanisms for authentication and encryption.

Unit I 08 Hrs
The Mobile Radio Channel and the Cellular Principle: Characteristics of the mobile radio
channel, Separation of directions and duplex transmission, Multiple access FDMA, TDMA, CDMA,
Cellular principle, Frequency reuse, Traffic capacity, Near Far effect, Interference.
System Architecture and Addressing: System architecture, The SIM concept, Addressing,
Registers and subscriber data, Location registers (HLR and VLR) Security-related registers (AUC
and EIR), subscriber data, Network interfaces and configurations.
Air interface GSM Physical Layer: Logical channels , Physical channels , Synchronization-
Frequency and clock synchronization, Adaptive frame synchronization, Mapping of logical onto
physical channels , Radio subsystem link control, Channel coding, source coding and speech
processing , Source coding and speech processing, Channel coding , Power-up scenario.

Unit II 07 Hrs
GSM Protocols: Protocol architecture planes, Protocol architecture of the user plane, Protocol
architecture of the signaling plane, Signaling at the air interface (Um), Signaling at the A and Abis
interfaces, Security-related network functions, Signaling at the user interface.
GSM Roaming Scenarios and Handover: Mobile application part interfaces, Location registration
and location update, Connection establishment and termination, Handover.

Unit III 07Hrs
Services: Classical GSM services, Popular GSM services: SMS and MMS.
Improved data services in GSM: GPRS, HSCSD and EDGE: GPRS System architecture of
GPRS, Services, Session management, mobility management and routing, Protocol architecture,
Signaling plane, Interworking with IP networks, Air interface, Authentication and ciphering,
Summary of GPRS.


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Unit IV 07 Hrs
Principles of Spread Spectrum, DS/SS, DS/FH, Processing Gain, Correlation.
Pseudo Random Noise sequences for Spread Spectrum M- sequences, Gold, Kasami and Walsh
sequences, Properties.
Time Synchronization of spread spectrum sequences Code acquisition, analysis of serial
acquisition, sequential acquisition, matched filter acquisition, Code tracking schemes in AWGN
channels, Code acquisition and tracking in fading channels.
Cellular CDMA principles Interference considerations, Single user receiver in a multiuser channel,
Improved single user receivers, adaptive single user receivers, CDMA system capacity, effects of
power control on link capacity.

Unit V 07Hrs
CDMA Standard IS95A - Forward link channels, Reverse Link channels, Mobility issues
CDMA Standard IS95B
CDMA Standard CDMA 2000 Physical channels, Forward and Reverse link channels,
supplemental channels, Transmit diversity. CDMA 2000 Revisions
UMTS WCDMA

Practicals: Communication Lab
1. Determination of Gain and beam width of a Pyramidal Horn antenna from its Radiation pattern.
2. Determination of Gain and beam width of the following antennae from their Radiation pattern: a)
Microstrip patch antenna b) Printed dipole antenna.
3. Determination of Modes, Transit time, Electronic timing range and sensitivity of Klystron
source.
4. Determination of s-matrix for the following devices:
a) Magic Tee b) H-plane Tee c) E-plane Tee d) Isolator e) Circulator f) Directional
coupler.
5. Design and simulation of Microstrip patch and 4- element array antenna at L-band and S-band
and plot the radiation pattern using Matlab.
6. Measurement of S-parameters of a power divider, printed directional coupler and resonant
antennas (Patch and Dipole antennas) using network analyzer.
7. To study Gaussian minimum shift keying modulation technique for GSM.
8. To design a receiver using Viterbi Hard decision algorithm.
9. To design a receiver using Viterbi soft decision algorithm.
10. Generation of PN sequence (a) Maximal length (b) Gold-Kasami sequence.
11. Study- Experiment: Design and simulation of Microstrip patch antenna at L-band and S-band
and plot the radiation pattern in the principal planes and also plot the S-parameters verses
frequency (Using IE3D software).

Course outcomes:
Ability to analyze the radio channel characteristics and the cellular principle.
Ability to explain the basic structure and elements of a GSM system and their interfaces as well
as the identifiers of users, equipment and system areas.
Ability to analyze the entire protocol architecture of GSM - communication protocols for radio
resource management, mobility management, connection management at the air interface the
mechanisms for authentication and encryption.
Ability to analyze improved data services in cellular communication.



11



Reference Books
1. Jorg Eberspacher, Hans-JorgVogel, Christian Bettstetter, Christian Hartmann, "GSM
Architecture, Protocols and Services, Willey, 3
rd
Edition, 2009.
2. Gunnar Heine, "GSM Networks: Protocols, Terminology and Implementation, 2
nd
Edition,
2009.
3. Timo Halonen, Javier Romero, Juan Melero, "GSM, GPRS, EDGE Performance: Evolution
towards 3G/UMTS, 3
rd
Edition, 2008.
4. Geoff Sanders, Lionel Thorens, Manfred Reisky, Oliver Rulik, Stefan Deylitz, GPRS
Networks, Willey, 2
nd
Edition, 2003.
5. Mosa Ali Abu-Rgheff, Introduction to CDMA Wireless Communications, Academic Press,
First Edition 2007.

Scheme of Continuous Internal Evaluation:
CIE consists of Three Tests each for 45 marks (15 marks for Quiz + 30marks for descriptive) out of
which best of two will be considered. In addition there will be one seminar on new topics / model
presentation etc. for 10 marks.

Scheme of Continuous Internal Evaluation: Practicals
A student is expected to conduct one experiment in the lab test.

Scheme of Semester End Examination:
The question paper consists of Part A and Part B. Part A will be for 20 marks covering the complete
syllabus and is compulsory. Part B will be for 80 marks and shall consist of five questions carrying
16 marks each. All five questions from Part B will have internal choice and one of the two have to be
answered compulsorily.

Scheme of Semester End Examination: Practicals
A student is expected to conduct one experiment in the practical exam






















12

Microwave Systems

Course Code: 10EC74 CIE Marks: 100
Hrs/Week: L:T:P : 3:0:0 SEE Marks: 100
Credits: 03 SEE Hrs : 03

Course Learning Objectives:
At the end of the course the students should be able to:
Apply the knowledge of fields and waves to develop transmission line theory.
Apply the knowledge of electromagnetic theory to analyze the fields in a waveguide.
Develop basic microwave circuit theory and include detailed discussions of impedance,
admittance and scattering matrix descriptions of microwave junctions.
Describe the variety of passive components.
Recognize the basic operation of microwave solid state devices, transfer electron devices,
avalanche transit time devices.
Describe the basic operation of multi-cavity klystron tubes.
Calculate the fundamental parameters for antennas and the radiation field from an antenna using
potential functions
Describe the radiation from isolated, linear wire antennas and from linear elements near or on a
conducting surface
Account for circular loop antennas and apply the field equivalence principle to aperture antennas
Account for the most important properties of travelling wave antennas, broadband antennas and
Microstrip antennas and how to match an antenna to a transmission line

Unit I 08 Hrs
Transmission Lines: Introduction, transmission lines equations and solutions, termination of line by
infinite line, by its characteristic impedance, short circuit line, open circuit line and any load resistive
impedance reflection, standing waves and SWR, problems.
Impedance Transforms and Matching: Smith chart construction and properties, single stub
matching, quarter wave transforms.

Unit II 08 Hrs
Microwave Waveguides: Introduction, TE, TM waves Rectangular waveguides (qualitative analysis
TE, TM modes), circular waveguides (quantitative analysis), dominant modes, group velocity phase
velocity, and wave impedance, microwave cavities resonant frequency q-factor.
S-parameters: Introduction properties, Representation of ABCD parameters in terms of S-matrix
(quantitative analysis).

Unit III 08 Hrs
Microwave Passive Devices: Waveguide Tees, Directional couplers, circulators, power diver (s-
parameters of all devices). Isolators, phase shifters, Attenuators, (s-parameters of all devices).
Microwave Sources: Multicavity Klystron amplifier, Reflex klystron oscillator, travelling wave
tube.

Unit IV 08 Hrs
Antenna Basics: Introduction, antenna radiation mechanism, basic Antenna parameters, patterns,
beam area, radiation intensity, beam efficiency, diversity and gain, antenna apertures, effective
height, bandwidth, radiation, efficiency, antenna temperature and antenna filed zones.
Dipole Antenna: Electric dipoles: Introduction, short electric dipole, fields of a short dipole,
radiation resistance of short dipole, radiation resistances of lambda/2 Antenna.

13

Unit V 08 Hrs
Antenna Arrays: Array of two isotropic point sources, non-isotropic but similar point sources, array
factor, principles of pattern multiplication, and examples of pattern synthesis by pattern
multiplication.
Antenna Types: Loop antennas, Helical Antenna, Yagi-Uda array, parabolic reflectors, log periodic
antenna, lens antenna, Smart Antennas.

Course outcomes:
Ability to describe the basic concept of microwaves.
Ability to compare waveguides with other methods of energy transfer.
Ability to describe the theory and operation of horn antennas, microwave reflectors and lenses.
Ability to describe the theory of semiconductor microwave devices.
Ability to analyze basic methods for antenna measurements

Reference Books
1. R E Collin, Foundations of Microwave Engineering, 2
nd
Edition,IEEE Press on Electromagnetic
and Wave Theory.
2. Goldberg, Bar-Giora, Digital Frequency Synthesis Demystified, LLH Technology Publishing,
1999.
3. John D.Krauss, Antennas, 3
rd
Edition, McGraw-Hill International Edition, 2006.
4. C.A Balanis, Antenna Theory & Design, 3
rd
Edition, John Wiley, 2010.
Scheme of Continuous Internal Evaluation:
CIE consists of Three Tests each for 45 marks (15 marks for Quiz + 30marks for descriptive) out of
which best of two will be considered. In addition there will be one seminar on new topics / model
presentation etc. for 10 marks.

Scheme of Semester End Examination:
The question paper consists of Part A and Part B. Part A will be for 20 marks covering the complete
syllabus and is compulsory. Part B will be for 80 marks and shall consist of five questions carrying
16 marks each. All five questions from Part B will have internal choice and one of the two have to be
answered compulsorily.









.





14

Satellite Communication & GPS

Course Code: 10ECF751 CIE Marks: 100
Hrs/Week:L:T:P:4:0:0 SEE Marks: 100
Credits: 04 SEE Hrs : 03

Course Learning Objectives:
At the end of the course the students should be able to:
Understand the Satellite orbits and orbital perturbations.
Analyze link power budget calculations and losses in the atmosphere.
Understand the components of the satellite in space and Earth stations.
Understand the Basic GPS Concept and Satellite Constellation
Analyze Earth-Fixed Coordinate System and GPS C/A Code Signal Structure

Unit I 09 Hrs
Overview Of Satellite Systems: Introduction, frequency allocation, Kepler laws, definitions, orbital
element, apogee and perigee heights, orbit perturbations, inclined orbits, calendars, universal time,
sidereal time, orbital plane, local mean time and sun synchronous orbits, Geostationary orbit:
Introduction, antenna, look angles, polar mix antenna, limits of visibility, earth eclipse of satellite,
sun transit outage.

Unit II 09Hrs
Propagation Impairments and Space Link: Introduction, atmospheric loss, ionospheric effects,
rain attenuation, other impairments.
Space Link: Introduction, EIRP, transmission losses, link power budget, system noise, CNR, uplink,
down link, effects of rain, combined CNR.

Unit III 09 Hrs
Space Segment: Introduction, power supply units, altitude control, station keeping, thermal control,
TT&C, transponders, antenna subsystem.
Earth Segment: Introduction, receive only home TV system, outdoor unit, indoor unit, MATV,
CATV, Tx Rx earth station.

Unit IV 09 Hrs
Basic GPS Concept: Introduction, History of GPS Development, Basic GPS Receiver, Approaches
of Presentation, Software Approach, Potential Advantages of the Software Approach.
GPS Performance Requirements, Basic GPS Concept, Basic Equations for Finding User Position,
Measurement of Pseudo-range, Solution of User Position from Pseudo-ranges, Position Solution with
more than Four Satellites, User Position in Spherical Coordinate System, Earth Geometry, Basic
Relationships in an Ellipse, Calculation of Altitude, Calculation of Geodetic Latitude, Calculation of
a Point on the Surface of the Earth, Satellite Selection, Dilution of Precision.
Satellite Constellation: Introduction, Control Segment of the GPS System, Satellite Constellation,
Maximum Differential Power Level from Different Satellites, Sidereal Day, Doppler Frequency
Shift, Average Rate of Change of the Doppler Frequency, Maximum Rate of Change of the Doppler
Frequency, Rate of Change of the Doppler Frequency Due to User Acceleration, Keplers Equation,
True and Mean Anomaly, Signal Strength at User Location.
15


Unit V 09 Hrs
Earth-Centered, Earth-Fixed Coordinate System:
Introduction, Direction Cosine Matrix, Satellite Orbit Frame to Equator Frame Transform, Vernal
Equinox, Earth Rotation, Overall Transform from Orbit Frame to Earth-Centered, Earth-Fixed
Frame, Perturbations, Correction of GPS System Time at Time of Transmission, Calculation of
Satellite Position, Coordinate Adjustment for Satellites, Ephemeris Data.
GPS C/A Code Signal Structure: Introduction, Transmitting Frequency, Code Division-Multiple
Access (CDMA) Signals, P Code, C/A Code and Data Format, Generation of C/A Code, Correlation
Properties of C/A Code, Navigation Data Bits, Telemetry (TLM) and Hand Over Word (HOW), GPS
Time and the Satellite Z Count, Parity Check Algorithm, Navigation Data from sub frame 1,
Navigation Data from subframes 2 and 3, Navigation Data from subframes 4 and 5Support Data,
Ionospheric Model, Tropospheric Model, Selectivity Availability (SA) and Typical Position Errors.

Course outcomes:
Ability to estimate apogee, perigee heights and eclipse angle
Ability to demonstrate atmospheric loss, ionospheric effects
Ability to estimate transmission losses and perform link power budget calculations
Ability to demonstrate Space Segment and Earth Segment components
Ability to estimate Satellite Position and perform Coordinate Adjustment for Satellites
Ability to generate C/A Code and demonstrate different sub frames of Navigation Data.

Reference Books:
1. Dennis Roddy; Satellite Communications; McGraw-Hill; 4
th
Edition, 2006 ISBN: 13:978-
0-07-007785-0.
2. Timothy Pratt, Charles Bostian and Jeremy Allnutt; Satellite Communications; John Wiley
& Sons; 2
nd
Edition; 2003; ISBN 13: 9780471370079.
3. James Bao-Yen, Tsui; Fundamentals of Global Positioning System Receivers A Software
Approach; John Wiley; 2
nd
Edition; 2005, ISBN 0-471-70647-7.
Scheme of Continuous Internal Evaluation:
CIE consists of Three Tests each for 45 marks (15 marks for Quiz + 30 marks for descriptive) out of
which best of two will be considered. In addition there will be one seminar on new topics / model
presentation etc. for 10 marks.

Scheme of Semester End Examination:
The question paper consists of Part A and Part B. Part A will be for 20 marks covering the complete
syllabus and is compulsory. Part B will be for 80 marks and shall consist of five questions
(descriptive, analytical, problems or/and design) carrying 16 marks each. All five from Part B will
have internal choice and one of the two have to be answered compulsorily.







16

Wavelets & Multirate Filter Banks

Course Code: 10ECF752 CIE Marks: 100
Hrs/Week:L:T:P: 4:0:0 SEE Marks: 100
Credits: 04 SEE Hrs : 03

Course Learning Objectives:
At the end of the course the students should be able to
Analyze & apply sampling-rate conversion
Apply sampling-rate conversion to multirate digital signal processing, including the
implementation of digital filters.
Analyze multirate filter banks, 1D and 2D wavelet transforms, wavelet-based filtering
Design and implement wavelet transforms (WT), applications of WT for filtering, compression
and analysis of signals and images

Unit I 09 Hrs
Review of Digital Filters: Introduction, Filter Design specifications, FIR Filter Design, IIR Filter
Design, All pass Filters, Special types of Filters, IIR Filters Based on two All pass Filters,
Concluding remarks, Problems.

Unit II 09 Hrs
Fundamentals of Multirate Systems: Introduction, Basic Multirate Operations, Interconnection of
building blocks, The Polyphase representation, Multistage implementations, Some applications of
Multirate Systems, Special filters & filter banks, Multigrid methods, Problems.

Unit III 10 Hrs
Maximally Decimated Filter Banks: Introduction, Errors created in the QMF bank, A simple alias-
free QMF systems, Power symmetric QMF banks, M-channel filter banks, Polyphase representation,
Perfect reconstruction (PR) systems, Alias-free filter banks, Tree structured filter banks,
Transmultiplexers, Summary and tables, Problems.

Unit IV 09 Hrs
Paraunitary Perfect Reconstruction (PR) Filter Banks: Introduction, Lossless transfer matrices,
Filter bank properties induced by paraunitariness, Two channel FIR Paraunitary QMF banks, The
two channel Paraunitary QMF lattice, M-channel FIR Paraunitaryfilter banks, Transform coding and
the LOT Summary, Comparisons, and Tables, Problems.

Unit V 10 Hrs
The Wavelet Transform and its relation to Multirate Filter Banks: Introduction, Background
and outline, The short-Time Fourier transform, The wavelet transform, Discrete-Time orthonormal
wavelets, Continuous- Time orthonormal wavelet basis, Concluding remarks, Problems.

Course outcomes:
Ability to understand the practical aspects of sampling and reconstruction and be able to
select a suitable sampling rate for a given signal processing problem.
Ability to design and analyze multi-rate filters for a given specification
Ability to implement of multirate QMF, PR orthogonal filter banks
Ability to understand the aspects of discrete-time wavelet transform and establish the
connection to tree-structured maximally decimated filter banks


Reference Books:
17

1. Vaidyanathan, P.P.: Multirate Systems and Filter Banks., Pearson Publication 2006, ISBN:
81-7758-942-3.
2. Proakis,J.G., Manolakis,D.G.: Digital Signal Processing. Principles, Algorithms and
Applications, 4
th
Edition, Pearson Publication, 2007, ISBN:9780131873742.

Scheme of Continuous Internal Evaluation:
CIE consists of Three Tests each for 45 marks (15 marks for Quiz + 30 marks for descriptive) out of
which best of two will be considered. In addition there will be one seminar on new topics / model
presentation etc. for 10 marks.

Scheme of Semester End Examination:
The question paper consists of Part A and Part B. Part A will be for 20 marks covering the complete
syllabus and is compulsory. Part B will be for 80 marks and shall consist of five questions
(descriptive, analytical, problems or/and design) carrying 16 marks each. All five from Part B will
have internal choice and one of the two have to be answered compulsorily.



































18

ATM Networks

Course Code: 10ECF753 CIE Marks: 100
Hrs/Week: L:T:P : 4:0:0 SEE Marks: 100
Credits: 04 SEE Hrs : 03

Course Learning Objectives:
At the end of the course the students should be able to
Describe ATM architecture, adaptation layer and switching architecture.
Analyze technologies involved in ATM Networking and their performance is highlighted.
Compare techniques involved in supporting real-time traffic and congestion control.

Unit I 09 Hrs
Overview of ATM: Introduction, Motivation for ATM, Definition of ATM, Genesis of ATM, Basic
Principles of ATM, ATM Protocol Reference Model.
ATM Physical Layer: Transmission Convergence Sub layer, Physical Medium Dependent Sub
Layer, Physical Layer Standards for ATM, DS1 ATM Physical Layer Interface, DS3 ATM Physical
Layer Interface, E1 ATM Physical Layer Interface, E3 ATM Physical Interface, Fractional T1/E1
ATM Physical Interface, SONNET/SDH based ATM Physical Layer Interface, Universal Test and
Operations PHY Interface for ATM(UTOPIA.

Unit II 10 Hrs
ATM Layer and ATM Adaptation Layer: ATM Cell Header Structure at UNI, ATM Cell Header
Structure at NNI, ATM Layer Functions Service Classes and ATM Adaptation Layer, AAL1, AAL2,
AAL3/4, AAL5.
ATM Traffic and Service Parameterization: ATM Traffic Parameters, ATM Service Parameters,
Factors affecting QOS Parameters, ATM Service Categories, QOS and QOS Classes.

Unit III 09 Hrs
ATM Traffic Control Management: ATM Traffic Shaping, ATM Traffic Policing, ATM Priority
Control, ATM Flow Control, ATM Congestion Control.
ATM Switching: Components of a Typical Switch, Performance Measures in Switch Design,
Switching Architectures, Shared Memory Architecture, Shared Medium Architecture, Space Davison
Architecture, Switching in ATM.
ATM Traffic Shaping, ATM Traffic Policing, ATM Priority Control, ATM Flow Control, ATM
Congestion Control.

Unit IV 10 Hrs
ATM Addressing: ATM End System Address (AESA) Format, ATM Group Address, Acquiring
ATM Address, ATM Name System (ANS)
ATM Signalling& Routing: ATM Signaling Protocol Stack, Signalling ATM Adaptation Layer
(SAAL), UNI Signaling, ATM Point-Point Signalling, ATM Point to Point Signalling, ATM Point to
Multipoint Signalling, PNNI Protocol, PNNI Routing Hierarchy, PNNI Topology Information,
Summarization and Aggregation.

Unit V 10 Hrs
Interworking with ATM: T Traditional LAN Technologies, ATM in LAN, LANE, Issues and
Requirements for LAN Emulation, Classical IP Over ATM, Logical IP Sub network(LIS), Address
Resolution in Classical IP Environment , Multi Protocol Encapsulation over AAL5, Maximum
Transmission Unit (MTU) Size, Multi Protocol Over ATM(MPOA).
19

Application of ATM Networks: Overview of MPLS, ATM and MPLS, MPLS for IP over ATM,
ATM-MPLS Networking, Carrying Voice over ATM, Overview of DSL, ATM and DSL, Overview
of UMTS, UTRAN and ATM.

Course outcomes:
Ability to describe ATM architecture, adaptation layer and switching architecture.
Ability to analyze the real time traffic and congestion control etc.
Ability to analyze technologies involved in ATM Networking and their performance.

Reference Books:
1. Sumit Kasera, ATM NETWORKS: Concepts and Protocols Tata McGraw-Hill, 2
nd
Edition,
2006.
2. Harry G Perros, An Introduction to ATM Networks, John Wiley & Sons Limited.
3. Rainer Handel, Manfred N.Huberetc, ATM Networks: Concepts, Protocols and Applications,
Addision-Wesley, 2
nd
Edition, 1994.
4. Internetworking over ATM An Introduction, International Business Machines ((IBM)
Corporation, 1996.

Scheme of Continuous Internal Evaluation:
CIE consists of Three Tests each for 45 marks (15 marks for Quiz + 30 marks for descriptive) out of
which best of two will be considered. In addition there will be one seminar on new topics / model
presentation etc. for 10 marks..

Scheme of Semester End Examination:
The question paper consists of Part A and Part B. Part A will be for 20 marks covering the complete
syllabus and is compulsory. Part B will be for 80 marks and shall consist of five questions
(descriptive, analytical, problems or/and design) carrying 16 marks each. All five from Part B will
have internal choice and one of the two have to be answered compulsorily.

















20


Low Power VLSI Design

Course Code: 10ECF754 CIE Marks: 100
Hrs/Week: L:T:P : 4:0:0 SEE Marks: 100
Credits: 04 SEE Hrs: 03

Course Learning Objectives:
At the end of the course the students should be able to
Explain the need for low power VLSI chips, Sources of power dissipation on Digital Integrated
circuits.
Emerging Low power approaches, Physics of power dissipation in CMOS devices.
Analyze the impact of Device Technology such as Transistor sizing & gate oxide thickness and
Device innovation on Low Power.
Evaluate various simulation based power analysis techniques at various levels of abstraction.
Evaluate various probabilistic based power analysis techniques at various levels of abstraction.
Compare the trade-off between accuracy and resources for both simulation based and probability
based power analysis.
Apply various circuit level techniques to optimize the power dissipation of the standard cells.
Apply various logic level techniques to optimize the power dissipation of the design reducing the
switching activities in the design
Design and analyze various low power circuits like low power SRAM, low power DRAM, etc..
Apply low power techniques to analog and mixed mode circuits.
Design and analyze simple digital circuits like combinational, sequential circuits using low
power concepts.

Unit I 09 Hrs
Introduction: Need for Low Power VLSI Design, Sources of power dissipation, Basic Principles of
Low Power Design, Degrees of freedom, Dynamic Power: Charging and Discharging of Capacitor,
Short Circuit Current and Short Circuit power in CMOS Circuits, Static Power: Leakage Currents,
Static Currents, Emerging low power approaches, Low power figure of merits.

Unit II 09 Hrs
Simulation Power Analysis: Spice Circuit Simulation, Discrete Transistor Modeling and Analysis,
Gate Level Logic Simulation, Architecture Level Analysis, Data Correlation Analysis in DSP
Systems, Monte Carlo Simulation.
Probabilistic Power Analysis: Random Logic Signals, Probability and Frequency, Probabilistic
Power Analysis Techniques, Signal Entropy.

Unit III 09 Hrs
Device and Technology Impact on Low Power Electronics: Introduction, Dynamic Dissipation in
CMOS, Effects of V
DD
and V
t
on speed, Constraints on V
t
Reduction, Transistor and Gate Sizing,
Transistor Sizing and Optimal Gate Oxide Thickness, Impact of Technology Scaling, Equivalent Pin
Ordering, Network Restructuring and Reorganization, Technology and Device Innovations, Gate
Reorganization, Signal Gating, Logic Encoding, State Machine Encoding, Pre-computational Logic.

Unit IV 10 Hrs
Low Power Circuit Techniques: Introduction, Power consumption in circuits, Circuit design styles,
Adders, multipliers, division, Flip-Flops and Latches, Logic, Special Latches and Flip Flops, Low
Power Cell Library.
21

Algorithm, Architecture and System: Introduction, design flow, Analysis and optimization, Power
and Performance Management, Switching activity reduction, Parallel Architecture with voltage
reduction.

Unit V 10 Hrs
Special Techniques for Power Optimization: Energy recovery CMOS: Retractile logic, Reversible
pipelines, High performance approaches, Adiabatic computation, Power Dissipation in clock
Distribution, Single Driver vs. Distributed Buffers, Buffer and Device Sizing under Process
Variations, Zero Skew vs. Tolerable Skew, Chip and Package Co Design of clock Network, Power
Reduction in Clock Networks, CMOS Floating Nodes, Low Power Bus, Delay Balancing, Low
Power Techniques for SRAM and DRAM.

Course outcomes:
Ability to acquire the knowledge with regard to the physical principles, analysis and the
characteristics of the low power designs.
Ability to apply knowledge of low power designs at different abstraction levels.
Ability to Identify, formulate, and solve engineering problems in the area of low power VLSI
designs.
Ability to use the techniques and skills in system designing through modern engineering tools
such as logic works SPICE and description languages such as VHDL and Verilog.
Ability to design a digital system, components or process to meet desired needs of low power
within realistic constraints.

Reference Books
1. Gary K. Yeap, Practical Low Power Digital VLSI Design, Kluwer Academic Publishers,
2002.
2. Jan M. Rabaey, MassoudPedram, Low Power Design Methodologies Kluwer Academic
Publishers, 5
th
reprint, 2002.
3. Kaushik Roy, Sharat Prasad, Low-Power CMOS VLSI Circuit Design, John Wiley, 2000.
4. K. S. Yeo, S. S. Rofail& W. L. Goh, CMOS/BICMOS VLSI Low Voltage, Low Power,
PHI, 2002.
5. P. Chandraksan, R. W. Broderson, Low power digital CMOS Design, Kluwer Academics,
1996.

Scheme of Continuous Internal Evaluation:
CIE consists of Three Tests each for 45 marks (15 marks for Quiz + 30 marks for descriptive) out of
which best of two will be considered. In addition there will be one seminar on new topics/ model
presentation etc. for 10 marks.

Scheme of Semester End Examination:
The question paper consists of Part A and Part B. Part A will be for 20 marks covering the complete
syllabus and is compulsory. Part B will be for 80 marks and shall consist of five questions
(descriptive, analytical, problems or/and design) carrying 16 marks each. All five from Part B will
have internal choice and one of the two have to be answered compulsorily.





22

Artificial Neural Networks

Course Code: 10ECG771 CIE Marks: 100
Hrs/Week: L:T:P : 3:0:0 SEE Marks: 100
Credits: 03 SEE Hrs: 03

Course Learning Objectives:
At the end of the course the student should be able to:
Define what is Neural Network and model a Neuron and Express both Artificial
Intelligence and Neural Network
Analyze ANN learning, Error correction learning, Memory-based learning, Hebbian
learning, Competitive learning and Boltzmann learning
Demonstrate Learning with and without teacher, learning tasks, Memory and Adaptation.
Implement Simple perception, Perception learning algorithm, Modified Perception
learning algorithm, and Adaptive linear combiner, Continuous perception, learning in
continuous perception.
Analyze the limitation of Single layer Perceptron and Develop MLP with 2 hidden layers,
Develop Delta learning rule of the output layer and Multilayer feed forward neural
network with continuous perceptions,
Develop least square estimator, Linear neuron, Recursive least square algorithm.
Develop basis function network, RBF techniques, Gaussian radial basis function, RBF as
interpolation networks, RBF as approximation networks, GRBF network training.

Unit I 07 Hrs
Introduction to Neural Networks: Neural Network, Human Brain, Models of Neuron, Neural
networks viewed as directed graphs, Biological Neural Network, Artificial neuron, Artificial Neural
Network architecture, ANN learning, analysis and applications , Historical notes.

Unit II 07 Hrs
Learning Processes: Introduction, Error correction learning, Memory-based learning, Hebbian
learning, Competitive learning, Boltzmann learning, credit assignment problem, Learning with and
without teacher, learning tasks, Memory and Adaptation.

Unit III 07 Hrs
Single layer Perception: Introduction, Pattern Recognition, Linear classifier, Simple perception,
Perception learning algorithm, Modified Perception learning algorithm, Adaptive linear combiner,
Continuous perception, Learning in continuous perception. Limitation of Perception.

Unit IV 08 Hrs
Multi-Layer Perceptron Networks: Introduction, MLP with 2 hidden layers, Simple layer of a
MLP, Delta learning rule of the output layer, Multilayer feed forward neural network with
continuous perceptions, Generalized delta learning rule, Back propagation algorithm.

Unit V 07 Hrs
Radial Basis Function Networks: Introduction, Least square estimator, Linear neuron, Recursive
least square algorithm, Basis function network, RBF techniques, Gaussian radial basis function, RBF
as interpolation networks, RBF as approximation networks, GRBF network training. Application to
approximation, MLP Vs RBF.



Course outcomes:
23

Ability to express what is Neural Network and model a Neuron and to analyze ANN
learning, and its applications
Ability to perform Error correction learning, Memory-based learning, Hebbian learning,
Competitive learning, Boltzmann learning,
Ability to do credit assignment problem, Learning with and without teacher,
Ability to perform Pattern Recognition, Linear classifier
Ability to develop Perception learning algorithm, Modified Perception learning algorithm,
Adaptive linear combiner, Continuous perception, apply Learning in continuous perception.
Ability to analyze the Limitation of Single layer Perceptron, and to analyze MLP and develop
Delta learning rule of the output layer.
Ability to develop Multilayer feed forward neural network with continuous perceptions ,
Generalized delta learning rule and Back propagation algorithm
Ability to develop detailed mathematical treatment of another class of layered networks: radial
basis function networks.

Reference Books:
1. Simon Haykins, Neural Network- A Comprehensive Foundation, Pearson Prentice Hall, 2
nd

Edition, 1999.
2. Zurada, Jacek M, Introduction to Artificial Neural Systems, West Publishing Company,
1992.
Scheme of Continuous Internal Evaluation:
The CIE consists of Three Tests each for 45 Marks (15 Marks for Quiz + 30 Marks for descriptive)
out of which best of two will be considered. In addition, there will be seminar on recent trends/
model presentation/ Assignment etc. for 10 marks.

Scheme of Semester End Examination:
The question paper consists of Parts A and B. Part A will be for 20 Marks covering complete
syllabus and is compulsory. Part B will be for 80 Marks and shall consists of 5 questions carrying 16
Marks each. All five questions from part B will have internal choice and one of the two have to be
answered compulsorily.



















Testing & Testability for Digital ICs
24


Course Code: 10ECG772 CIE Marks: 100
Hrs/Week :L:T:P: 3:0:0 SEE Marks: 100
Credits: 03 SEE Hrs : 03

Course Learning Objectives:
At the end of the course the student should be able to:
Analyze the need for testing
Difficulties and challenges in testing
Concepts of Design for Testability
Comprehend the different testing techniques

Unit I 07 Hrs
Introduction to VLSI Testing: Testing philosophy, role of testing, digital and analog testing, VLSI
technology, trends affecting testing, VLSI testing process and test equipment, Types of testing,
Automatic test equipment, electrical parameter testing, Test economics and product quality: Test
economics, yield, defect level as a quality measure.

Unit II 07 Hrs
Fault Modeling: Defects, Faults, Errors and Failure, Functional versus Structural testing, Levels of
fault model, Single stuck-at fault.

Unit III 08 Hrs
Test Pattern Generation: Combinational circuit test generation: Algorithms and representation,
redundancy identification, significant combinational ATPG algorithms-D Calculus and D algorithm,
PODEM.

Unit IV 07 Hrs
Fault simulation: Fault Simulation Techniques, Fault Simulation for combinational circuits, Fault
Sampling.

Unit V 07 Hrs
Digital Design for Testability: Controllability and Observability, Ad-Hoc DFT, Structured DFT:
Scan based DFT, BIST.

Course outcomes:
Ability to Grasp the ideas behind fault modeling
Ability to Recognize the various test techniques
Ability to Evaluate the significance of each test techniques
Ability to Develop algorithms

Reference Books:
1. M.L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing for Digital, Memory and
Mixed-Signal VLSI Circuits, Kluwer Academic Publishers, 2000.
2. M.Abramovici, M.Breuer and A Friedman, Digital Systems Testing and Testable Design,
JAICO Publishing house, ISBN 81-7724-891-1.
25


Scheme of Continuous Internal Evaluation:
CIE consists of Three Tests each for 45 marks (15 marks for Quiz + 30 marks for descriptive) out of
which best of two will be considered. In addition there will be one seminar on new topics / model
presentation etc. for 10 marks.

Scheme of Semester End Examination:
The question paper consists of Part A and Part B. Part A will be for 20 marks covering the complete
syllabus and is compulsory. Part B will be for 80 marks and shall consist of five questions
(descriptive, analytical, problems or/and design) carrying 16 marks each. All five from Part B will
have internal choice and one of the two have to be answered compulsorily.








































26



Broad Band Communication

Course Code: 10ECG773 CIE Marks: 100
Hrs/Week: L:T:P: 3:0:0 SEE Marks: 100
Credits: 03 SEE Hrs: 03

Course Learning Objectives:
At the end of the course the student should be able to:
Learn the current state of art technology in Broadband over wire line and wireless media.
Understand communication over DSL and different flavors of DSL.
Learn the various standards in wireless broadband communication.

Unit I 08 Hrs
Twisted Pair Environment: Full duplex systems, hybrids, cable bundles, Gauge & line
characteristics, RLCG Models And Propagation Constant, Characteristic Impedance.
Loop Impairments and Analysis: Unbalance models, Cross talk types NEXT - FEXT, PSD of
Disturbers (T1, ADSL, HDSL, ISDN) and their interference models, RFI, Impulse noise, Bridge
taps, loading coils. Input impedance, transfer functions and insertion loss. ADSL and VDSL loop
configurations.
DSL Physical Layer Processing: 2B1Q, 4B3T, QAM, DMT, ADSL capacity, VDSL capacity.
Capacity in the presence of crosstalk. Tone loading Algos, rate adaptation RS codes. Equalization -
Time domain eqlr, frequency domain eqlr in ADSL and VDSL context. Analog Front end, PAR.
Echo path and echo cancellation.

Unit II 07Hrs
ADSL and VDSL2:
ADSL / ADSL2 / ADSL2+ System: ADSL Reference model, Framing, Superframe, single latency
and dual latency paths, bitswap, SRA and DRR. Initialization, Activation, gain estimation,
synchronization. Channel discovery, Training, Channel analysis, exchange. Showtime processes and
monitoring for bitswap and SRA.
VDSL2 System: VDSL Reference model, Framing, super frame, single latency and dual latency
paths, Bitswap, SRA, DRR, and SOS. Initialization, Activation, gain estimation, synchronization.
Channel discovery, Training, Channel analysis, exchange. Showtime processes and monitoring for
Bitswap and SRA, Standards G993.2.

Unit III 07Hrs
WiMax: Overview of 802.16 WiMax and Architecture: Salient features, Overview of Phy and
Mac layers, Reference architecture model, Protocol layering, Network discovery, IP address
assignment, Authentication.
IEEE 802.16 Physical Layer: Channel coding, hybrid ARQ, Interleaving, symbol mapping, OFDM
symbol, sub channels, slot and frame structure, ranging, power control, channel quality
measurements, MIMO deployment.

Unit IV 07Hrs
WiMax:
IEEE 802.16 MAC Layer: Convergence, MacPDU, Bandwidth request and allocation, entry and
initialization power saving operations, mobility management.
IEEE 802.16 Security Issues AND QOS: Mechanisms multimedia session management, encryption
and AES, mobility management, IP for wireless solutions.
27


Unit V 08 Hrs
WLANIEEE 802.11 Architecture: Basic service set, extended service set, Distribution service set.
Interaction between services.
IEEE 802.11 MAC Layer: Functionality, frame exchange protocol, access mechanism, frame
formats, frame subtypes data, control, and management.
IEEE 802.11 Physical Layer: Functionality, DSSS, FHSS, 802.11a OFDM, 802.11b, 802.11g,
802.11n.
IEEE 802.11 SECURITY MANAGEMENT AND QOS: 802.11X Authentication and Key
management protocol AKMP, Temporary key Integrity protocol. 802.11e QOS specification.
Operation, frame formats and options.

Course outcomes:
Ability to learn the current state of art technology in Broadband over wire line and wireless
media.
Ability to understand communication over DSL and different flavors of DSL.
Ability to learn the various standards in wireless broadband communication.

Reference Books:
1. Thomas Starr, John Cioffi, and Peter Silverman, Understanding Digital subscriber Line
Technology, Prentice Hall, 1999.
2. Philip Golden, Herve Dedieu and Krista Jacobsen, Fundamentals of DSL Technology,
Auerbach Publications, 2004.
3. Jeffrey Andrews, Arunabha Ghosh, and Rias Muhamed, Fundamentals of WiMax, Prentice
Hall, 2007.
4. Bob O, Hara and Al Petrick, IEEE 802.11 Handbook , IEEE Press,1999.
Scheme of Continuous Internal Evaluation:
CIE consists of Three Tests each for 45 marks (15 marks for Quiz + 30 marks for descriptive) out of
which best of two will be considered. In addition there will be one seminar on new topics / model
presentation etc. for 10 marks.

Scheme of Semester End Examination:
The question paper consists of Part A and Part B. Part A will be for 20 marks covering the complete
syllabus and is compulsory. Part B will be for 80 marks and shall consist of five questions
(descriptive, analytical, problems or/and design) carrying 16 marks each. All five from Part B will
have internal choice and one of the two have to be answered compulsorily.








28


MIMO in Communication Systems

Course Code: 10ECG774 CIE Marks: 100
Hrs/Week: L:T:P : 3:0:0 SEE Marks: 100
Credits: 03 SEE Hrs : 03

Course Learning Objectives:
At the end of the course the student should be able to:
Understand multiple-antenna systems such as multiple-input multiple-output (MIMO) and
space-time codes.
Learn how the benefits from MIMO are realized.
Learn the basics of Antenna Diversity, Beam forming.
Understand MIMO techniques with diversity, beamforming and Space Division
Multiplexing.
Recognize the applications of MIMO in WiFi, WiMax and LTE.

Unit I 07 Hrs
Overview: Need of MIMO systems, MIMO communication in wireless standards.
Fading Channel: Wireless channels, path loss, shadowing and small scale fading, fading channel
models, error/outage probabilities over fading channels. Outage probability for Rayleigh fading
channels, average error probabilities over Rayleigh fading channels, extension to other fading
channels, performance over frequency selective fading channels.

Unit II 07 Hrs
Diversity Techniques: Diversity techniques types of diversity, system model for L
th
order
diversity, maximal ratio combining, Suboptimal combining algorithm, selection combining. Channel
coding as a means of time diversity, block coding over a fully interleaved channel. Convolution
Coding. Multiple antennas in wireless communications receive diversity, smart antennas and beam
forming, space time coding basic ideas.

Unit III 08 Hrs
Capacity and Information Rates of MIMO: Capacity and information rates of noisy channels,
Capacity and information rates of AWGN and fading channels, AWGN channels, fading channels,
Capacity of MIMO channels, deterministic MIMO channels, Ergodic MIMO channels, Non-Ergodic
MIMO channels and outage capacity, transmit CSI for MIMO fading channels. Constrained
signaling for MIMO communications.

Unit IV 07 Hrs
Space Time Block Codes: Transmit diversity with two antennas: the Almouti Scheme,
Transmission scheme, optimal receiver for the Almouti Scheme. Performance analysis of the
Almouti Scheme. Orthogonal space time block codes, Linear orthogonal design, decoding of linear
orthogonal design, performance analysis of space time block codes, quasi orthogonal space time
block codes, linear dispersion codes.
Space Time Trellis Codes-I: A simple space time trellis code, general space time trellis code, basic
space time code design principles.

29


Unit V 08 Hrs
Space Time Trellis Codes-II: Representation of space time trellis code for PSK constellations,
Performance analysis for space time trellis code, comparison of space time block and trellis codes
Layered Space Time Codes: Basic Bell laboratories layered Space time (BLAST) architecture.
DBLAST, multilayered space time codes, Thread space time codes, other detection algorithms for
spatial multiplexing systems. Diversity multiplexing, gain trade off.

Course outcomes:
Ability to understand multiple-antenna systems such as multiple-input multiple-output
(MIMO) and space-time codes.
Ability to understand MIMO techniques with diversity, beam forming and Space Division
Multiplexing.
Ability to recognize the applications of MIMO in WiFi, WiMax and LTE.

Reference Books:
1. Tolga. M. Duman and Ali Ghrayeb, Coding for MIMO Communication Systems, 1
st

Edition, 2007.
2. Tsoulos, George MIMO System Technology for Wireless Communication, CRC Press,
2006.
Scheme of Continuous Internal Evaluation:
CIE consists of Three Tests each for 45 marks (15 marks for Quiz + 30 marks for descriptive) out of
which best of two will be considered. In addition there will be one seminar on new topics / model
presentation etc. for 10 marks.

Scheme of Semester End Examination:
The question paper consists of Part A and Part B. Part A will be for 20 marks covering the complete
syllabus and is compulsory. Part B will be for 80 marks and shall consist of five questions
(descriptive, analytical, problems or/and design) carrying 16 marks each. All five from Part B will
have internal choice and one of the two have to be answered compulsorily.




















30

Automotive Electronics

Course Code: 10HG706 CIE Marks: 100
Hrs/Week: L:T:P : 4:0:0 SEE Marks: 100
Credits: 04 SEE Hrs: 03

Course Learning Objectives:
At the end of the course the student should be able to:
Know the automotive domain fundamentals and prepare for the application of electronics on
the same.
Understand the application of principles of sensing technology in automotive field, smart
sensors, and the type of sensor better suited for a particular application
Apply control systems in the automotive space, an application oriented learning with
examples, criticality / specific to real time embedded system like anti wind up function,
actuator dithering, etc
Understand automotive specific communication protocols / techniques , their significance &
benefits.
Analyze fault tolerant real time embedded systems, the basics of diagnostics, its method,
reporting mechanism and error handling / fault reactions.

Unit I 09 Hrs
Power Train Engineering and Fundamentals of Automotive: Fundamentals of Petrol, diesel and
gas engines, electric motors and control systems. Basic Automotive System, System Components,
Evolution of Electronics in Automotive. Alternators and charging, battery technology, Ignition
systems. Working principles of various electronic components and accessories used in Automotive.
Developments in existing engine forms and alternatives. Hybrid designs (solar power,
electric/gasoline, LPG, fuel cells). Basic Transmission systems, Different forms and development.

Unit II 09 Hrs
Sensor Technologies in Automotive: In-vehicle sensors: Working principles, Characteristics,
limitations and use within the automotive context of the following: Temperature sensing e g. coolant,
air intake. Position sensing e.g. crankshaft, throttle plate. Pressure sensing e.g. manifold, exhaust
differential, tyre. Distance sensing e.g. anti-Collision, Velocity sensing e.g. speedometer, anti-skid.
Torque sensing e.g. automatic transmission. Vibration sensing e.g. Airbags. flow sensing and
measurement e.g. fuel injection. Interfacing principles: Operation, topologies and limitations of all
sensors covered in the above to in-vehicle processing or communications nodes. Use of Actuators:
Types, Working principle, Characteristics, limitations and use within the automotive context of each
type.
Unit III 09 Hrs
Automotive Control Systems: Control system approach in Automotive: Analog and Digital control
methods, stability augmentation, control augmentation. Transmission control, System components
and functions. Cruise control, traction control, actuator limiting, wind-up, gain scheduling, adaptive
control. Special Control Schemes: Vehicle braking fundamentals, Antilock systems. Variable assist
steering and steering control. Controls for Lighting. Wipers, Air conditioning /heating. Remote
keyless Entry and Anti-theft System, Emission Course-system control. Control techniques used in
hybrid system. Electronic Engine control: Motion equations, modeling of linear and non-linear
systems, numerical methods, system responses Objective of Electronic Engine control. Spark
Ignition and Compression Ignition Engines and their electronic controls. Engine management testing:
Engine management system strategies and implementation. Simulation and implementation methods.
Methods of improving engine performance and efficiency.
31


Unit IV 10 Hrs
Automotive Communication Systems: Communication interface with ECUs: Interfacing
techniques and interfacing with infotainment gadgets. Relevance of internet protocols, such as
TCP/IP for automotive applications. Wireless LANs standards, such as Bluetooth, IEEE802.11x.
Communication protocols for automotive applications. Automotive Buses: Use of various buses such
as CAN, LIN, Flex Ray. Recent trends in automotive buses (Such as OBDI1. MOST, IE, IELI.I,
D2B and DSI). Application of Telematics in Automotive: Global Positioning Systems (GPS) and
General Packet Radio Service (GPRS), for use in an automotive environment. Higher End
Technology: Comparative Study and applications of ARM Cortex.-Ascries/M-scries. ARM 9 and
ARM11, Current developments and issues.

Unit V 10 Hrs
Diagnostics and Safety in Automotive: Fundamentals of Diagnostics: Basic wiring system and
Multiplex wiring system. Preliminary checks and adjustments, Self Diagnostic system. Fault finding
and corrective measures. Electronic transmission checks and Diagnosis, Diagnostic procedures and
sequence. On board and off board diagnostics in Automotive. Safely in Automotive: Safety norms
and standards. Passenger comfort and security systems. Electromagnetic environment and
Automotive EMC Standards.SAE and IEEE Standards. Future trends in Automotive Electronics.

Course outcomes:
Ability to understand the automotive domain fundamentals and prepare for the application of
electronics on the same.
Ability to understand the application of principles of sensing technology in automotive field,
smart sensors, which type of sensing principle is better suited for a particular application
Ability to apply control systems in the automotive space, an application oriented learning with
examples, criticality/specific to real time embedded system like anti wind up function,
actuator dithering, etc.
Ability to understand automotive specific communication protocols/techniqueswhy & how.
Its significance & benefits
Ability to analyze fault tolerant real time embedded systems, the basics of diagnostics, its
method, reporting mechanism and error handling/fault reactions.

Reference Books:
1. Williams. B. Ribbens, Understanding Automotive Electronics, 6
th
Edition, Elsevier science,
Newness Publication, 2003.
2. Robert Bosch, Automotive Electronics Handbook, John Wiley and Sons, 2004.
3. Nitaigour Mahalik, Mechatronics: Principles, Concepts and Applications, TMH, 2003.
4. Uwekiencke & lars Nielsen, Automotive Control Systems Engine, Driveline and Vehicle,
2
nd
Edition, Springer, 2005.

Scheme of Continuous Internal Evaluation:
CIE consists of Three Tests each for 45 marks (15 marks for Quiz + 30 marks for descriptive) out of
which best of two will be considered. In addition there will be one seminar on new topics / model
presentation etc. for 10 marks

Scheme of Semester End Examination:
The question paper consists of Part A and Part B. Part A will be for 20 marks covering the complete
syllabus and is compulsory. Part B will be for 80 marks and shall consist of five questions
(descriptive, analytical, problems or/and design) carrying 16 marks each. All five from Part B will
have internal choice and one of the two have to be answered compulsorily.