AN

INDIVIDUAL ASSIGNMENT REPORT

ON



A REVIEW ON FOUR DIFFERENT METHODS OF
FLOORPLANNING






2012
(Autumn Semester)





Submitted to: Submitted By:
Mr. Mriganka Gogoi Sivaranjan Goswami (DC2009BTE4066)
Asst. prof. 7
th
Semester (B)
ECE Department Branch: ECE






DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
DON BOSCO COLLEGE OF ENGINEERING AND TECHNOLOGY
AIRPORT ROAD , AZARA, GUWAHATI-781017, ASSAM
CONTENTS
1. Introduction 1
2. GRCA: A Global Approach for Floorplanning Synthesis in
VLSI Macrocell Design 2
3. Yield and Routing Objectives in Floorplanning 5
4. Object Oriented Lisp Implementation of the CHEOPS VLSI
Floor Planning and Routing System 7
5. Simultaneous Floor Planning and Global Routing for
Hierarchical Building-Block Layout 9
6. Overall Review of the Papers 11
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Chapter 1: Introduction


1.1 What is Floorplanning?
Floorplanning is the placement of flexible blocks, that is, blocks with fixed area but
unknown dimensions. In floorplanning, several layout alternatives for each block are
considered. Usually, the blocks are assumed to be rectangular and the lengths and widths of
these blocks are determined in addition to their locations. The blocks are assigned
dimensions by making use of the aspect ratios. The aspect ratio of a block is the ratio of the
width of the block to its height. Usually, there is an upper and a lower bound on the aspect
ratio a block can have as the blocks cannot take shapes which are too long and very thin.
Initial estimate on the set of feasible alternatives for a block can be made by statistical
means, i.e., by estimating the expected area requirement of the block. Many techniques of
general block placement have been adapted to floorplanning. The only difference between
floorplanning and general block placement is the freedom of interface characteristic of cells.
Inaccurate data partly affects floorplanning. In addition to the inaccuracy of the cost
function that we optimize, the area requirements for the blocks may be inaccurate.
Floorplanning algorithms are typically used in hierarchical design. This is due to the fact
that, although the dimensions of each leaf of the hierarchical tree may be known, the blocks
at the node level in the tree are flexible, i.e., they can take any dimension. Hence, the
floorplanning algorithms are used at each of the nodes in the tree so that the area of the
layout is the minimum and the positions of all the blocks are identified.

1.2 Objective of this Report

Researchers at various universities and companies are trying to formulate various new
methods of floorplanning in order to increase optimization. A number of papers have been
published. Some of the methods are practically used by VLSI designers at various
organizations. In this report a comparative study of four different proposed methods of
floorplanning will be discussed. All these methods are taken from four IEEE papers. These
four papers are summarized in the following four chapters. The fifth chapter will contain an
overall review of the papers.








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CHAPTER 2: GRCA: A Global Approach for
Floorplanning Synthesis in VLSI Macrocell Design


The author of this paper is Alexander Herrigel, Hagelin-Cryptos Crypto AG, Staff Scientist,
Research & Development, P.O. Box 474, CH-6301 Zug, Switzerland.

In this paper anew pseudo-polynomial area optimization algorithm is proposed that derives
from a given hierarchical floorplan tree the optimal slicing tree. The method has been
successfully applied to an industrial design with about 260000 transistors. In this technique
the entire floorplanning process is divided into four phases as follows:

Phase 1: 2D Partitioning

A two-dimensional partitioning procedure is applied as a fast means to generate a
hierarchical floorplan tree.

The partitioning is based on a symmetric reference matrix R. An entry of the R-matrix
represents a set of properties between two macrocells. These properties are connectivity and
shape match. This measure will force two macrocells to be placed close to each other, if
they are strongly connected and if they have a similar shape.


Phase 2: Estimation of the Template Class with minimal Total
Chip Area

A new bottom-up tree traversal procedure is executed to get a set of appropriate template
classes (a template class is a rectangular dissection D of given macrocells in a plane). In
this phase the interconnect around each macrocell is dynamically allotted. Then the best
template class with the minimal total chip area is selected. In this process first slicing
structures are considered and a new area optimization algorithm proposed.

As mentioned in the earlier chapter, the proposed technique is for optimizing a hierarchical
floorplan tree. Thus the first phase, i.e., partitioning merely provides the hierarchical
floorplan tree of order at least two. In this phase the main objective is to find the optimal
template class with respect to chip aspect ratio and area.

The concept of shape functions is applied to determine the appropriate template class. The
vertical and horizontal sum of the associated shape functions are determined to compose
two macrocells. The lower bound of these two shape functions is computed to collect the
different representations. Suppose the floorplan tree is of order 3. For three different
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macrocells A, B and C we compute the lower bound of the vertical and horizontal sum of
the associated shape functions from A and B and then from [A,B] and C. Since the resulting
shape function from [[A,B],C] describes a different template class as the shape function of
[[A,C],B], we consider all different permutations and compute the associated shape
functions. The lower bound of all these shape functions represents the resulting shape
function for the complete hierarchy. Since the addition of two shape function does not
depend on the order of the considered macrocells (the shape functions from [A,B] and [B,A]
are identical) we only consider a subset of the possible permutations. An element of this
subset is called a binary permutation, since a binary sequence is a good representation for
checking which shape function has to be considered.

It is observed from experiment that 80% of the tuples have low area utilization. Therefore,
the described method does not need much memory space. The same procedure is applied if
some cells have multishape representation.

The above method is for slicing structure. A non-slicing structure may be generated by
placing a fifth cell in the interior empty space of the bounding box. To get all possible non-
slicing representations of five cells, all tuples are enumerated, and two of them composed if
they are disjoint. If the shape of the fifth cell fits in the interior empty space of the bounding
box, a non-slicing representation has been found. Otherwise the cells are positioned such
that no overlapping occurs and the adjacency relations are maintained.

A statistical analysis is applied to maintain enough routing area between the cells by
expanding the shape of cells in the leaf nodes of the floorplan tree as a function of
the relative port density. During the floorplan assembly, the connectivity
information of the circuit is considered by modifying the shape functions at each
node. Depending on the track demand the shape function is shifted right. Unlike
other approaches, the connection count between different clusters is computed to
determine the track demand more precisely.

Phase 3: Generation of Final Floorplan

After minimizing the weighted maximum cut line and selecting an optimal template class
for chip aspect ratio and area, the design is optimized with respect to global routing area and
total wire length. An algorithm is proposed in this paper which evaluates all variants of the
hierarchy. Hence the proposed procedure is independent of the successor node ordering for
the considered hierarchical level. The cut densities for all channels are computed to estimate
the final chip area, i.e. cell and global routing area, of a variant.




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Phase 4: Optimization of Port Positions

In this phase, an analytical optimization technique is used to minimize the routing
complexity. Unlike other techniques, all cells are simultaneously considered in this
technique.

Implementation and Outcomes

The proposed GRCA based global floorplanning technique that considers multiple goals
simultaneously has been implemented in C++on a Sun 3/60. It has been found to give
satisfactory result to various testing processes. A number of floorplans have been designed.
It is found to save area by about 20% compared to a commercial design. However, it has not
yet been implemented for fabrication of IC.


Conclusion

It is efficient, since it first determines the best template class and then the best variant of the
state space. The approach is based on a two-dimensional partitioning that generates a
hierarchical floorplan tree. Unlike traditional slicing approaches, the technique covers a
larger space of different template classes. It maintains the global perspective of these
approaches. This additional degree of freedom generates denser floorplans. In addition,
interconnect space around each cell is dynamically allocated during the floorplan assembly
to avoid an increase in chip area after global routing. The port positions of the cells are
optimized by an analytic algorithm simultaneously considering all cells.













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CHAPTER 3: Yield and Routing Objectives in
Floorplanning


The authors of this paper are Israel Koren and Zahava Koren, Department of Electrical and
Computer Engineering, University of Massachusetts, Amherst, MA 01003.

This paper emphasizes on the fact that floorplan also affects the yield of the chip in addition
to total chip area and routing cost. The goal of this paper is to study the two seemingly
disjoint objectives of yield enhancement and routing complexity minimization, and find out
whether they lead to different optimal floorplans, resulting in a need for a tradeoff analysis.

There is no clear cut solution to a multi-objective problem, since improving one objective
will usually have a negative impact on the others. The two most frequently used approaches
to attacking such a problem are weighting and Pareto optimization. In the first approach, a
weight is attached to each objective according to its importance, and the weighted sum of
the objectives is calculated for each solution point. The solution with the highest weighted
sum is then selected. This approach changes the decision problem from multi-dimensional
to one-dimensional. The second approach keeps the multi-dimensionality of the problem.
Rather than selecting one solution, a set of "Pareto-optimal" solutions is found, so that none
of the solutions in the set "dominates" any of the others, and all are considered equally good
and equally \optimal". We will demonstrate these two approaches while solving the problem
discussed in this paper.

Denoting the wiring cost by W and the yield by Y, the multi-objective is minimizing W and
maximizing Y. These are usually conflicting objectives and cannot be accomplished
simultaneously (except for some very special cases). In the weighting method, weights c
w

and c
y
are selected, and the optimal solution s* =(w*,y*) is the one which minimizes the
function Z =c
w
W c
y
Y.

Definition

Given two solutions, s
1
=(w
1
, y
1
) and s
2
=(w
2
, y
2
), we say that s
1
dominates s
2
, denoted by
s
1
>s
2
, if w
1
w
2
and y
1
y
2
.

A set of solutions {s
1
.s
n
} is called Pareto-optimal if no solution in the set dominates any
other solution, i.e., for any s
i,
s
j
in the set, s
i
is not greater than sj and s
j
is not greater than s
i
.
Specifically for our problem, a set of solutions is Pareto-optimal if for every s
i
and s
j
in the
set (where s
i
=(w
i
; y
i
) and s
j
=(w
j
; y
j
)), either w
i
<w
j
and y
i
<y
j
, or w
i
>w
j
and y
i
>y
j
, i.e.,
each solution is better in one aspect but worse in the other.


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Discussion

In this paper two examples are considered and it is shown that although both minimization
of wiring cost and maximization of yield is not possible, however, it is possible to obtain an
optimal yield within a set of floorplans with minimum wiring cost or very close to it.





































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CHAPTER 4: Object Oriented Lisp Implementation of the
CHEOPS VLSI Floor Planning and Routing System

The authors of this paper are Christian Masson, Remy Escassut Denis Barbier, Daniel
Winer and Gregory Chevallier of BULL S.A, 78340 Les Clayes-sous-Bois, France.

This paper presents the architecture and capabilities of a highly interactive system known as
CHOEP System that provides an integrated set of facilities allowing VLSI designers to
cover all steps from initial floorplan evaluation down to final chip composition and detailed
routing.

In the following sections of this chapter the various features of this system will be
discussed.

CHEOPS SOFTWARE ENVIRONMENT

The CHEOPS basic architecture and software methodology was initially developed as part
of the French CAD Research Project SYCOMORE, joining INRIA, Thomson, INPG and
BULL and where Le-Lisp was used as primary CAD development language.

It is basically an Object Oriented LISP based environment. Thus it inherits advantages of
LISP such as dynamic memory management, dynamic linkage of procedures, powerful
exception handling and error recovery mechanisms, flexible interactive debugging facilities
and freedom to choose best programming style and paradigms. It also inherits features of
Object Oriented Programming like easy modeling of complex interacting objects by
behavior encapsulation, incremental software development, code robustness and software
maintainability.

CHEOPS GRAPHICS INTERFACE

Considering the complexity and amount of graphical data involved in VLSI Floorplanning
and Layout, it was mandatory to supply VLSI designers with well synthesized information
through a very fast and high quality graphic interface.
The CHEOPS object display manager maintains incremental consistency between the
CHEOPS data structures and the terminal display file, in order to minimize line throughput.
It also provides the identification mechanism when a user picks a layout object.





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CHEOPS DATA STRUCTURES

A major feature of the CHEOPS architecture is a novel memory data structure that
consistently and uniformly models topological relationships and connectivity through the
whole design flow.

The three main steps of VLSI design can be modeled in CHEOPS:

(i) Modeling Floorplans
(ii) Modeling Geometrical Constraints
(iii) Modeling Interconnections and Routing.


DISCUSSION

CHEOPS have various abilities and features like File Transfer, Block placement and
channel definition, Power and clock bussing definition, Global routing of logic nets,
Pseudo-pin cross assignment, Wiring and congestion analysis, Channel routing and
compaction, The GEODE channel router (high quality and general purpose 2 layer channel
router which accepts rugged borders, gridless pin locations and routes simultaneously nets
and power/clock busses), etc.

In this paper it is demonstrated that CHEOPS is a very efficient framework for quick
development of advanced and flexible VLSI synthesis and layout tools, without incurring
significant speed or memory penalty. This software package is now worldwide used within
Groupe BULL to design 22 full custom high performance VLSI chips (from 80K to
5OOKtrans. in 1.1 and 0.8 micron CMOS technologies).















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CHAPTER 5: Simultaneous Floor Planning and Global
Routing for Hierarchical Building-Block Layout


The authors of this paper are Wei-Ming Dai, Student Member, IEEE, and Ernest S. Kuh,
Fellow, IEEE.

In this paper a new methodology for hierarchical floor planning and global routing for
building block layout is presented. Unlike the traditional approach, which separates
placement and global routing into two consecutive stages, our approach accomplishes both
jobs simultaneously in a hierarchical fashion.

This paper focuses on the fact the quality of floorplanning is hard to evaluate without
considering global routing. Even the most sophisticated placement and routing schemes do
not guarantee an appropriate layout if placement and global routing solution mismatch.
Therefore a new floorplanning problem has been formulated in this paper to incorporate
global routing.

Description of the Proposed Method

In this paper, initially the concepts of floorplan graph and global routing graph are defined.
Then floorplan enumeration method is discussed. The next section focuses on the scheme of
combining floorplanning and global routing in a hierarchical fashion. It is followed by a top
level algorithm which is based on the underlying concepts of the earlier concepts. Then the
experimental results are presented. A discussion of partial 3-trees and the underlying idea of
a linear time minimumSteiner tree algorithm for a special class of partial 3- trees are also
presented towards the end of the paper followed by the conclusion section.

A hierarchy may be formed in either top-down or bottom-up fashion. Both has its pros and
cons. After forming the physical hierarchy in the form of tree by the hierarchical clustering
of the building blocks the floorplanner performs a top-down traversal of the hierarchy for
evaluation. Bothe chip area and net path length are considered when evaluating a given
floorplan template and room assignment. To estimate the net path length, all the edge
widths between each pair of cluster in adjacent rooms are summed up. It is called adjacency
gain, which gives a reasonable estimate of the path length if the number of rooms is small.
In addition, we need to estimate the shape of the blocks by introducing a shape penalty
function. At the bottom level, the shape penalty is computed based on matching between
fixed block shapes and the corresponding rooms. At higher level the dimensions of the
rooms corresponding to the blocks are compared which are levels of the sub-tree rooted at
the vertex.

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When undesirable block shapes and pin positions are detected, alternate floorplan templates
and room assignments may be tried.

Even though the proposed floorplanning and global routing are not solved in one set of
equations, they influence each other in a hierarchical fashion. At each level, the global
routing graphs are sub-graphs of the floorplan's inner dual graph. On the other hand the
global routing solution at current level will be used to construct the I/O pad goal for the
floorplan evaluation at next level. Thus floorplanning and global routing together restrict
the aspect ratio of the walls of the rooms, and produce assignments for I/O pads on the walls
of the rooms. This information is then recursively transmitted downwards as sub-goals as
we traverse down the cluster tree.

Based on these concepts an Overall Floorplanning Algorithmhas been designed.

Conclusion

Currently, the cluster size of a given level of hierarchy is set to five because at least five
rooms are required to from a non-slicing floor plan topology of all possible floor plans or
placements to slicing structures. This restriction not only limits the choices of floor plans
and placements but also wastes area when the slicing structure is imposed during the routing
stage. The proposed system can generate non-slicing floorplan if desired.

The number of floorplan templates can grow exponentially with the number of rooms,
which is determined by the cluster size limit.

Currently, only the floorplan templates including all possible topologies of two, three and
four room floorplans and a subset of all possible topologies of five room floorplans are
used. However, in future, it is intended to increase this number up to seven.

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CHAPTER 6: Overall Review of the Papers


In Chapters 2, 3, 4 and 5 we have summarized four different IEEE papers on Floorplanning.
In this paper a summarized review of all these four papers will be presented.

The paper in chapter 2 presents a hierarchical area optimization algorithm. It is claimed to
reduce the area requirement by about 20% compared to commercial design. This paper is
fully based on area optimization and optimization of Global Constraints. It is not concerned
about any other perspective of the yield.

The paper in chapter 4 describes the various features of CHEOPS, a LISP and CAD based
software package for floorplan design and routing. It summarizes the various abilities of the
framework. It is explained that it is a highly efficient framework for quick development of
advanced and flexible VLSI synthesis and layout tools, without incurring significant speed
or memory penalty.

The paper summarized in chapter 3 is of high significance because these two papers
focuses on more than one goals. This paper focuses on dealing with both yield and routing
objective. For a VLSI design yield is always expected to be high whereas the routing cost
minimized. It is usually believed that the routing cost always increases as the yield
increases. Thus these two objectives are contradictory to each other. However, in this paper
it is shown that it is possible to obtain an optimal yield within a set of floorplans with
minimum routing cost or very close to it.

The paper in chapter 5 is also of significance. It proposes an algorithm for simultaneous
floorplanning and global routing. Traditionally, floorplanning and global routing are not
performed simultaneously. The quality of the floorplanning is difficult to judge without
taking global routing into account. The layout may suffer because of a mismatch in
floorplanning and global routing solutions. This paper provides an algorithm for
simultaneous floorplanning and routing so as to minimize this risk. It has some limitations
in terms of cluster size since the number of floorplan templates increases exponentially with
the cluster size. Since this system represents floorplanning as a sub-block of global routing,
the complexity of the global routing solution also depends upon the floorplan template used.

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