Electrical Engineering Department University of Texas at Arlington

EE 3444
Electronics II

Lab Manual

Howard T. Russell, Jr., PhD
V 1.1 January 1, 2011
2010 OPAL
tx



- 1 -

EE 3444
Electronics II

Lab Manual
V 1.1 January 1, 2011
2010 OPAL
tx


Table of Contents

Lab Meeting No. 1 Introduction to EE Labs ..2

Lab Experiment No. 1 Bipolar Device Characterization ..30

Lab Experiment No. 2 MOSFET Characterization ..41

Lab Experiment No. 3 Biased Current Sinks and Sources ....48

Lab Experiment No. 4 Self-Biased Current Sinks and Sources .57

Lab Experiment No. 5 Current Mirrors .....64

Lab Experiment No. 6 Single-Stage Amplifiers ....71

Lab Experiment No. 7 Operational Amplifier Design ...77

Lab Experiment No. 8 Amplifier Networks ..84

Lab Experiment No. 9 Op-Amp Testing ..86

Appendix 1 Breadboard Layout Examples ...92

Appendix 2 Lab Measurement Example ...96

Appendix 3 Bills of Material ....102


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Lab Meeting No. 1 Introduction to EE Labs

I. Introduction
The objective of this first lab meeting is to reintroduce EE students to a professional laboratory environment where
electronic circuits are built and electrical engineering experiments performed. The following topics will be addressed in
this introductory meeting
an orientation regarding proper behavior and safety while in the lab,
tools and tool box requirements,
lab instruments,
cables, connectors, probes, and wires,
electronic components, parts, and the parts request form,
lab report format, and
useful web sites.

II. Lab Orientation
All EE 3444 students are required to attend an orientation regarding proper behavior and safety while in the lab. This
orientation is presented by the resident lab technicians who are responsible for the maintenance and up-keep of the EE
labs in Nedderman Hall.

III. Tools and Tool Box (Attachment A)
Basic items such as pliers, cutters, and wire strippers are integral components in any electrical engineers tool box.
These tools are necessary to build circuits and perform experiments in the EE lab. Therefore, it is a mandatory
requirement that all EE 3444 students obtain and maintain a tool box containing a set of electrical engineering
specific tools. The tool box requirement is not an option and all students must bring their tool box fully loaded to
every lab meeting beginning with the second meeting. Students without a tool box on the second and subsequent lab
meetings will not be allowed in the lab and will receive a zero for the lab. A list of these tools along with their
photographs is included in Attachment A at the end of this document.

IV. Lab Instruments (Attachment B)
The electrical engineering labs located in rooms NH129, NH129A, NH148, and NH148A are equipped with the
most current industry standard test and measurement equipment found in professional electrical engineering
companies. Each lab is divided into a series of lab benches with each bench containing the following instruments
Agilent 34401A 6 digit multimeter (DMM),
Agilent E3620A dual dc power supply (25V, 1A),
Agilent 54621A 60MHz dual channel oscilloscope, and
Agilent 33120A 15MHz function generator.
Most of the experiments performed in EE 3444 will involve the above mentioned instruments to some degree. Data
sheets for these instruments are included in Attachment B.

V. Cables, Connectors, Probes, and Wires
Each lab is equipped with one or more wall-mounted racks containing a variety of cables, connectors, oscilloscope
probes, and wires. These connectors provide the necessary electrical connections among the bench instruments and
your circuits.

VI. Electronic Components, Parts, and the Parts Request Form (Attachment C)
A wide assortment of electronic components and parts are available in the EE lab. An extensive list of components
and parts can be found on the lab web site www-ee.uta.edu/eelabs2/. Click on parts available for a view of the list.
The experiments performed in EE 3444 labs involve the use of parts supplied by the lab GTA. In more advanced
courses, students will have to order their own parts through the lab by submitting an online parts request form. A
copy of this form is shown in Attachment C. Most of the parts listed on the lab web site are considered disposable.
This means that once parts are given to the student, the student is allowed to keep and accumulate them. For parts
not on the list, a formal written request for these parts may be submitted along with instructor approval to lab
personnel.

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VII. Lab Report Format (Attachment D)
Formal lab reports are due typically within one week after each lab experiment. Exceptions are made for more
complex and/or extensive lab experiments. The format for lab reports is outlined below.
Title Page. Every lab report begins with a title page. This page includes the course and section number,
experiment number, experiment title, date the experiment was performed, date the report submitted, and student
name and ID number. A sample of the EE 3444 lab report cover page is included in Attachment D.
Introduction. A brief description of the purpose of the lab and a discussion of key information the reader will
need to understand the experiment. Give a brief description of the theory the experiment is based upon.
Procedure. Describe how the experiment was performed. List equipment, instruments, and components used
in the experiment. Include the theory, equations, and detailed schematics of circuits involved.
Results. Present the results of the experiment with data collected from measurements performed. Data should
be professionally and neatly presented in the form of tables, graphs, and plots.
Discussions. Discuss any new ideas and/or questions produced in the experimental process. Comment on the
validity, accuracy, and usefulness of the procedure.
Conclusion. A description of what the experiment revealed. Generate a comparison between the expected
results based on theory and the actual results. An attempt should be made here to explain any discrepancies between
these results.
Appendix. The appendix should contain actual compiled data, notes and comments, equations, sketches, and
schematics made during the experiment.
References. List any material contributed from other sources.

VIII. Useful Web Sites
Mouser Electronics www.mouser.com
Jameco Electronics www.jameco.com
Marlin P. Jones & Associates, Inc. www.mpja.com
Electronics Express/RSR www.elexp.com
Nuts and Volts (magazine) www.nutsvolts.com


- 4 -

Attachment A

Tools and the Tool Box
August 2, 2009
Component Example Brand Example Source Price ($)
Suitable container (all-purpose plastic
tool box; fishing tackle box)
Keter (13 all-purpose
box)
Wal-Mart 3.64
Needle nose pliers (4 to 5) (Figure 1) Stanley (mini plier set) Wal-Mart
12.88
(set of 6)
Diagonal cutters (4 to 5) (Figure 2) Stanley (mini plier set) Wal-Mart
Wire strippers (5) (Figure 3)
H-Tools (cutter and
stripper, 34-899C)
Frys 3.49
Prototype breadboard (6.5 x 2 to 6.5 x
4 with 3 to 5 binding posts) (Figures 4
and 5)
Elenco (Model 9425,
6.5 x 2, 830 test
points)
Frys 9.99
Precision screwdriver set (6 to 11 piece
set with slotted and Phillips screwdrivers)
(Figure 6)
Stanley (6 piece; 4
slotted, 2 Phillips)
Wal-Mart 4.88
22 gauge solid hook-up wire (Figure 7)
Frys product number:
PLU#1615281
Frys 2.99

Tax: 3.09
Total: 40.96

Photos


Figure 1
5 needle-nose pliers
- 5 -


Figure 2
5 diagonal cutters


Figure 3
Wire strippers


- 6 -


Figure 4
Three binding post breadboard


Figure 5
Three binding post breadboard

- 7 -


Figure 6
Screwdriver set


Figure 7
22 gauge wire



- 8 -

Attachment B


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Attachment C



- 29 -

Attachment D

EE 3444.002
Lab Experiment 2
Resistors and Resistor Color Bands




























Date experiment performed: June 7, 2010

Date Lab Report submitted: June 14, 2010

Student name: Howard T. Russell, Jr.

Student ID: 10

- 30 -

Lab Experiment No. 1 Bipolar Device Characterization

I. Introduction
The purpose of this lab is to gain familiarity with several well-known semiconductor devices. In particular, these devices
are the small-signal pn-junction diode, the NPN bipolar junction transistor (BJT), and the PNP BJT. The experiments
involved in this lab address the dc characteristics of the devices and how these characteristics are used in modeling the
devices. The theory and equations associated with these devices are covered in Chapter 1 of your class notes. Your job
in this session is to build, test, and evaluate each of the given test circuits in order to expand your hands-on experience in
working with semiconductor devices. For each test circuit, make use of the parts supplied by the GTA, and the DMM
and dc power supply located on the lab bench.

II. Components and Instruments
The components and instruments required for this lab are listed below.
Components:
Diode measurement circuit
Diode: 1N4148 (DUT)
Resistors:
200 (1/2 watt) 2K 20K 200K 2M
330 (1/2 watt) 3.3K 33K 330K
820 (1/2 watt) 8.2K 82K 820K

NPN and PNP measurement circuits
Op-amp: OP-07
NPN: MPS8098 (DUT)
PNP: MPS8598 (DUT)
Capacitors: 220pF (2)
Resistors:
51 (1/2 watt) 82 (1/2 watt) 200 510 820
2K (2) 3K 5.1K 8.2K (2) 20K (2)
30K 51K 82K 200K (3) 300K
820K 2M

Instruments:
Power supply Multimeter
Agilent E3620A Agilent 34401A

Additional:
Breadboard
Tool box
Hook-up wire

III. Diode DC Measurements and Modeling
The schematic for the diode dc test circuit is shown in Figure 1. This simple circuit is used to obtain the forward biased
IV characteristics of the device under test (DUT) by sweeping the current I
D
and measuring the corresponding forward
voltage V
D
. The DUT in this experiment is the 1N4148 small-signal pn-junction diode which is a standard device in
many circuit designs. The diode current is swept by setting the power supply voltage V
ps
at a constant value (20V) and
changing the resistor R
m
with values spanning 200 to 2M to obtain a wide dynamic current range. By measuring the
voltage across this resistor (V
R
), I
D
is determined from the VCR equation


R
D
m
V
I
R
= (1)

With V
R
and R
m
accurately measured, I
D
is an accurate calculation of the diode current. This calculation allows an
indirect yet accurate means to determining the diode current.

- 31 -

1. Measurements:
(a) At the beginning of the experiment, the GTA will provide a 1N4148 diode and an assortment of resistors.
(b) Build the test circuit shown in Figure 1 to measure the forward IV characteristics of the 1N4148 diode. A photo of
the correct way to build this circuit on a breadboard is shown in Figure 2. Request the GTA to verify your circuit
prior to making measurements.
(c) With the resistors provided by the GTA, measure the variables listed in Table 1 for each value of R
m
. Record these
values in the first six columns of the table in order to obtain the voltage V
D
versus current I
D
data.
(Hint: for neatness, you must record these values in your lab notebook before you transfer them to the printed
table. You may redraw the table in Word if you wish.)
2. Data processing:
(a) Use the Windows Excel program to plot your measured data in the form of I
D
versus V
D
. An example of this plot
is shown in the IV graph in Figure 3. This is the format typical to display a device IV curve; therefore, copy the
style of this graph exactly as shown.
3. Parameter extraction:
(a) On the EE 3444 course website is an application note entitled The SPICE Diode Model. On pages 62 to 64 of
this note, a parameter extraction method labeled Three-point I-V method for the calculation of the SPICE diode
model parameters RS, N, and IS is explained. These parameter correspond to the theory model parameters rS, ,
and IS, respectively. Equations for these parameters are given in (3.36) for RS, (3.37) for N, and (3.38) for IS.
Apply this method to your measured IV data to extract r
S
, , and I
S
for your diode. Show all for your calculations.
4. Playback and comparison:
(a) For the I
D
values in calculated in Table 1, calculate the diode voltage V
DC
using the extracted parameters r
S
, , and
I
S
in the diode model equation given as

ln 1
D
DC t S D
S
I
V V r I
I

= + +


(2)

where V
t
is the thermal voltage of 26mV. Record these calculated voltage values in the seventh column of the
table.
(b) Use Excel to generate a graph with plots of V
D
and V
DC
versus I
D
for a visual comparison of the measured and
calculated voltages. Use the graph style and format shown in the example graph in Figure 4.
(c) Evaluate the results of your parameter extraction by generating the error in percent between the measured diode
voltage and the calculated voltage with the measured values as the basis. That is, calculate the percent error from

( ) % 100%
DC D
D
V V
V

= (3)

Record the errors in the last column where indicated. Finally, generate the error function E
2
given in equation
(3.35) on page 62 in the above mentioned application note where


( ) ( ) ( ) ( )
2 2 2 2
13
1 2 13
2
1
% % % %
100 100 100 100
i
i
E

=
= + + + =

L (4)

Record E
2
at the bottom of the table where indicated.
(d) As stated in the application note, the method that yields the lowest value for E
2
produces the most accurate values
for the extracted parameter values. Therefore, comment on the accuracy of your extracted parameters from the
measured and calculated IV plots and E
2
value.

- 32 -

5. Lab report: Your lab report on this section of the lab should consist of the following:
(a) Table 1 completely filled out.
(b) Values for the model parameters; show all calculation steps.
(c) Measured IV plot.
(d) Measured and calculated IV plots on the same graph.
(e) A plot of in % versus I
D
.
(f) A conclusion and comments on the accuracy of your model.
(g) An appendix containing copies of pages from your lab notebook containing all data and calculations made during
the experiment.

V
ps
20V
Agilent power supply
R
m
V
R
I
D
V
D
DUT
200 <R
m
<2M

Figure 1
Diode dc test circuit


Figure 2
Correct breadboard layout

- 33 -


Figure 3
Typical measured IV characteristics

Table 1
1N4148 Diode measurements
R
m
()
(spec.)
R
m
()
(meas.)
V
ps
(V)
(meas.)
V
R
(V)
(meas.)
I
D
(A)
(calc.)
V
D
(V)
(meas.)
V
DC
(V)
(calc.)
(%)
2M
820K
330K
200K
82K
33K
20K
8.2K
3.3K
2K
820
330
200
E
2


1.0E06
1.0E05
1.0E04
1.0E03
1.0E02
1.0E01
1.0E+00
0.3 0.4 0.5 0.6 0.7 0.8 0.9
I
D

(
A
)
VD (V)
- 34 -


Figure 4
Typical measured and calculated IV characteristics

0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0E06 1.0E05 1.0E04 1.0E03 1.0E02 1.0E01 1.0E+00
V
D

&

V
D
C


(
V
)
ID (A)
VD
VDC
- 35 -

IV. NPN BJ T Gummel Measurements
The schematic for an NPN BJT dc test circuit is shown in Figure 5. This circuit is the basis for the stimulus-
measurement unit (SMU) employed in semiconductor parameter analyzers (SPA) such as the HP4145 or newer Agilent
4142. Its application of the OP-07 operational amplifier allows the collector current (I
C
) of the NPN BJT DUT to be
varied while maintaining a constant collector-emitter voltage (V
CE
). With I
C
swept over a wide dynamic range, the base
current (I
B
) and the base-emitter voltage (V
BE
) are measured and graphed for display of the Gummel plots (I
C
and I
B

versus V
BE
) and the characteristics ( versus I
C
). These plots are very important in BJT characterization and modeling.
In the circuit shown below, the voltage at the op-amps negative input terminal (V
n
) is fixed at 5V by the voltage divider
R
1
and R
2
. Since the op-amp forces this voltage to be mirrored at its positive input terminal (V
p
= V
n
), then V
CE
of the
DUT is also fixed at 5V. The OP-07 employs an input bias current cancellation scheme such that the currents into the
positive and negative input terminals are very small and have no effect on the DUT currents. Therefore, the DUTs
collector current is set by the resistor R
C
where


psp p
C
C
C C
V V
V
I
R R

= = (5)

The base current is determined by measuring the voltage across R
B
so that


B
B
B
V
I
R
= (6)

For typical values of , I
B
can be on the order of nano-amps (nA) to micro-amps ( A). This suggests that R
B
should be
in the range of 100K to 10M to allow precise measurements for V
B
. The results from these two equations are
combined to calculate the DUT measured at the dc bias condition specified by I
C
and V
CE
; that is


,
C CE
C
B
I V
I
I
= (7)

The base-emitter voltage is easily measured at the corresponding DUT terminals. Finally, a compensation capacitor C
c
is
connected between the output and negative input terminals to insure circuit stability by preventing unwanted oscillations.
1. Measurements:
(a) At the beginning of the experiment, the GTA will provide you a MPS8098 NPN BJT and an assortment of
resistors.
(b) Build the test circuit shown in Figure 5 to measure the forward Gummel characteristics of the MPS8098. A photo
of the correct way to build this circuit on a breadboard is shown in Figure 6. Request the GTA to verify your
circuit prior to making measurements.
(c) With the resistors provided by the GTA, measure the variables listed in Tables 2(a) and 2(b) for specified values of
R
C
and R
B
. Record these values in the table in order to obtain the Gummel characteristics.
(Hint: for neatness, you must record these values in your lab notebook before you transfer them to the printed
table. You may redraw the tables in Word if you wish.)
2. Data processing:
(a) Use the Windows Excel program to plot your measured data in the form of
(i.) I
C
and I
B
versus V
BE
for the Gummel plot (typical plot shown in Figure 7), and
(ii.) versus I
C
for the forward plot (typical plot shown in Figure 8).
Copy the style of the example graphs exactly as shown.
3. Lab report: Your lab report on this section of the lab should consist of the following:
(a) Tables 2(a) and 2(b) completely filled out.
(b) Measured Gummel and plots.
(c) A conclusion and comments on the accuracy of your measurements.
(d) An appendix containing copies of pages from your lab notebook containing all data and calculations made during
the experiment.

- 36 -

V
psp
10V R
C
V
C
I
C
R
1
R
2
200K
200K
R
B
V
B
I
B
V
BE
C
c1
220pF
V
CE
I
C
DUT
OA
1
OA
1
=OP-07
V
n
V
p
V
o
Agilent power supply
C
c2
220pF
V
psn
10V

Figure 5
NPN BJT Gummel test circuit


Figure 6
Correct breadboard layout



- 37 -

Table 2(a)
MPS8098 measurements
R
C
(spec.) 51K 20K 8.2K 5.1K 2K
R
B
(spec.) 2M 820K 300K 200K 82K
R
C
*

R
B

V
psp

V
psn

V
n

V
p
(V
CE
)
V
C

I
C

V
o

V
B

I
B

V
BE


* Measured values of these variables.

Table 2(b)
MPS8098 measurements
R
C
(spec.) 820 510 200 82 51
R
B
(spec.) 30K 20K 8.2K 3K 2K
R
C
*

R
B

V
psp

V
psn

V
n

V
p
(V
CE
)
V
C

I
C

V
o

V
B

I
B

V
BE


- 38 -



Figure 7
Typical Gummel plot


Figure 8
Typical plot

1.0E07
1.0E06
1.0E05
1.0E04
1.0E03
1.0E02
0.5 0.6 0.7 0.8
I
C

&

I
B

(
A
)
VBE (V)
IC
IB
10
100
1000
1.0E05 1.0E04 1.0E03 1.0E02
B
e
t
a

(
A
/
A
)
IC (A)
- 39 -

V. PNP BJ T Gummel Measurements
The schematic for an PNP BJT dc test circuit is shown in Figure 9. Build this test circuit on your breadboard, and repeat
the measurement and data processing procedure described for the MPS8098 NPN for a MPS8598 PNP. Reproduce the
data tables (Tables 3(a) and 3(b)) and graphs for the Gummel and plots for this device. Generate an identical lab report
for this section of the experiment describing the measurements taken from the MPS8598.

V
psp
10V
R
C
V
C
I
C
R
1
R
2
200K
200K
R
B
V
B
I
B
V
EB
C
c
220pF
V
EC
I
C
DUT
OA
1
OA
1
=OP-07
V
p
V
n
V
o
Agilent power supply
C
c2
220pF
V
psn
10V

Figure 9
PNP BJT Gummel test circuit

Table 3(a)
MPS8598 measurements
R
C
(spec.) 51K 20K 8.2K 5.1K 2K
R
B
(spec.) 2M 820K 300K 200K 82K
R
C
*

R
B

V
psp

V
psn

V
n

V
p
(V
CE
)
V
C

I
C

V
o

V
B

I
B

V
BE




- 40 -

Table 3(b)
MPS8598 measurements
R
C
(spec.) 820 510 200 82 51
R
B
(spec.) 30K 20K 8.2K 3K 2K
R
C
*

R
B

V
psp

V
psn

V
n

V
p
(V
CE
)
V
C

I
C

V
o

V
B

I
B

V
BE





- 41 -

Lab Experiment No. 2 MOSFET Characterization

I. Introduction
The purpose of this lab is to gain familiarity with MOSFET devices. The experiments involved in this lab address the
forward dc transfer characteristics of n-channel and p-channel devices and how these characteristics are used in device
modeling. The theory and equations associated with these devices are covered in a class handout. Your job in this
session is to build, test, and evaluate each of the given test circuits in order to expand your hands-on experience working
with MOSFETs. For each test circuit, make use of the parts supplied by the GTA, and the DMM and dc power supply
located on the lab bench.

II. Components and Instruments
The components and instruments required for this lab are listed below.
Components:
MOS measurement circuits
Op-amp: OP-07 (2)
n-ch: ALD1103/n-ch
p-ch: ALD1103/p-ch
Capacitors: 220pF (2)
Resistors:
68 (1/2 watt) 100 (1/2 watt) 200 270 680
2K 6.8K 20K 30K (2) 68K
120K 200K 10K trimpot

Instruments:
Power supply Multimeter
Agilent E3620A Agilent 34401A

Additional:
Breadboard
Tool box
Hook-up wire

III. ENMOS Measurements
The schematic for an enhancement mode, n-channel, MOSFET (ENMOSFET) dc test circuit is shown in Figure 1. This
circuit is the basis for the stimulus-measurement unit (SMU) employed in semiconductor parameter analyzers (SPA)
such as the HP4145 or newer Agilent 4142. Its application of the OP-07 operational amplifier (OA
1
) allows the drain
current (I
D
) of the DUT to be varied while maintaining a constant drain-source voltage (V
DS
). With the source-body
voltage (V
SB
) set to a constant value by a voltage reference circuit and with I
D
swept over a wide dynamic range, the
gate-source voltage (V
GS
) is measured and graphed for display of the forward transfer characteristics plot (I
D
versus V
GS

and V
SB
). This plot is very important in MOSFET characterization and modeling. In the circuit shown below, the
voltage at the op-amps negative input terminal (V
n
) is fixed at 8V by the voltage divider R
1
and R
2
. Since the op-amp
forces this voltage to be mirrored at its positive input terminal (V
p
= V
n
), then V
DS
of the DUT is also fixed at 8V. Op-
amp OA
2
and the 10K trimpot R
T
make up a unity-gain buffer with an adjustable output voltage V
o2
to set the source-
body voltage V
SB
. The OP-07 employs an input bias current cancellation scheme such that the currents into the positive
and negative input terminals of OA
1
are very small and have no effect on the DUT currents. Therefore, the DUTs drain
current is set by the resistor R
D
where


psp p
D
D
D D
V V
V
I
R R

= = (1)

- 42 -

The model for the drain current I
D
in the saturation region is given by

( ) ( )
2
1
D GS TH DS
I V V V = + (2)

The gate-source voltage is easily measured at the corresponding DUT terminals. Finally, 220pF compensation
capacitors C
c1
and C
c2
are connected to OA
1
and DUT as indicated to insure circuit stability by preventing unwanted
oscillations.
1. Measurements:
(a) At the beginning of the experiment, the GTA will provide you with an ALD1103 and an assortment of resistors
1
.
(b) Build the test circuit shown in Figure 1 to measure the forward transfer characteristics of one of the n-channel
MOSFET on the chip. Request the GTA to verify your circuit prior to making measurements.
(c) With the resistors provided by the GTA, measure the variables listed in Tables 1(a) and 1(b), and Tables 2(a) and
2(b) for specified values of R
D
and V
SB
. Record these values in the tables in order to obtain the transfer
characteristics.
(Hint: for neatness, you must record these values in your lab notebook before you transfer them to the printed
table. You may redraw the tables in Word if you wish.)
2. Data processing:
(a) Use the Windows Excel program to plot your measured data in the form of
(i) I
D
versus V
GS
for the forward transfer characteristics plot for V
SB
= 0V, and
(ii) I
D
versus V
GS
for the forward transfer characteristics plot for V
SB
= 2V.
(b) Model parameter extraction (assume V
DS
<< 1)
(i) extract the threshold voltage V
TH
and the transconductance parameter from the transfer characteristics data
for V
SB
= 0V, and
(ii) extract the threshold voltage V
TH
and the transconductance parameter from the transfer characteristics data
for V
SB
= 2V.
3. Lab report: Your lab report on this section of the lab should consist of the following:
(a) Tables 1 and 2.
(b) Measured forward transfer characteristics plots for the two V
SB
values.
(c) Extracted V
TH
and for the two V
SB
values.
(d) Calculated forward transfer characteristics plots for the two V
SB
values (apply the parameters in (c.) to equation
(2)).
(e) A conclusion and comments on the accuracy of your measurements and extracted parameters.
(f) An appendix containing copies of pages from your lab notebook containing all data and calculations made during
the experiment.

V
psp
10V
R
D
V
D
I
D
R
1
R
2
30K
120K
C
c1
220pF
DUT
OA
1
OA
1
, OA
2
=OP07
V
n
V
p
V
o1
Agilent power supply
DUT =ALD1103/n-ch
C
c2
220pF
V
GS
V
SB
I
D
V
DS
R
3
R
T
10K
30K
V
psn
10V
OA
2
V
o2

Figure 1
Forward transfer characteristics test circuit

1
Download the ALD1103 data sheet from the Advanced Linear Devices, Inc. website www.aldinc.com.
- 43 -

Table 1(a)
ALD1103/n-ch measurements (V
SB
= 0V)
R
D
(spec.) 200K 68K 20K 6.8K 2K
V
SB
*

R
D
*

V
psp

V
psn

V
n

V
p
(V
DS
)
V
D

I
D

V
o1

V
GS

* Measured values of these variables.

Table 1(b)
ALD1103/n-ch measurements (V
SB
= 0V)
R
D
(spec.) 680 270 200 100 68
V
SB
*

R
D
*

V
psp

V
psn

V
n

V
p
(V
DS
)
V
D

I
D

V
o1

V
GS

* Measured values of these variables.

- 44 -

Table 2(a)
ALD1103/n-ch measurements (V
SB
= 2V)
R
D
(spec.) 200K 68K 20K 6.8K 2K
V
SB
*

R
D
*

V
psp

V
psn

V
n

V
p
(V
DS
)
V
D

I
D

V
o1

V
GS

* Measured values of these variables.

Table 2(b)
ALD1103/n-ch measurements (V
SB
= 2V)
R
D
(spec.) 680 270 200 100 68
V
SB
*

R
D
*

V
psp

V
psn

V
n

V
p
(V
DS
)
V
D

I
D

V
o1

V
GS

* Measured values of these variables.

- 45 -

IV. EPMOS Measurements
The schematic for a p-channel, enhancement mode MOSFET dc test circuit is shown in Figure 2. Build this test circuit
on your breadboard, and repeat the measurement and data processing procedure described for the n-channel MOS for
one of the p-channel MOSFETs on the ALD1103 chip. Reproduce the data tables (Tables 3(a) and 3(b), and Tables 4(a)
and 4(b)) and the forward transfer characteristics plots for the device. Generate an identical lab report for this section of
the experiment describing the measurements taken from the p-channel device.
V
psp
10V
R
D
V
D
I
D
R
1
R
2
30K
120K
V
SG
C
c1
220pF
V
SD
I
D
DUT
OA
1
OA
1
, OA
2
=OP07
V
p
V
n
V
o1
C
c2
220pF
V
BS
DUT =ALD1103/p-ch
V
psn
10V
Agilent power supply
R
3
R
T
10K
30K
OA
2
V
o2


Figure 2
Forward transfer characteristics test circuit

Table 3(a)
ALD1103/p-ch measurements (V
BS
= 0V)
R
D
(spec.) 200K 68K 20K 6.8K 2K
V
BS
*

R
D
*

V
psp

V
psn

V
n

V
p
(V
SD
)
V
D

I
D

V
o1

V
SG

* Measured values of these variables.

- 46 -

Table 3(b)
ALD1103/p-ch measurements (V
BS
= 0V)
R
D
(spec.) 680 270 200 100 68
V
BS
*

R
D
*

V
psp

V
psn

V
n

V
p
(V
SD
)
V
D

I
D

V
o1

V
SG

* Measured values of these variables.

Table 4(a)
ALD1103/p-ch measurements (V
BS
= 2V)
R
D
(spec.) 200K 68K 20K 6.8K 2K
V
BS
*

R
D
*

V
psp

V
psn

V
n

V
p
(V
SD
)
V
D

I
D

V
o1

V
SG

* Measured values of these variables.

- 47 -

Table 4(b)
ALD1103/p-ch measurements (V
BS
= 2V)
R
D
(spec.) 680 270 200 100 68
V
BS
*

R
D
*

V
psp

V
psn

V
n

V
p
(V
SD
)
V
D

I
D

V
o1

V
SG

* Measured values of these variables.




- 48 -

Lab Experiment No. 3 Biased Current Sinks and Sources

I. Introduction
The purpose of this lab is to evaluate the performance of biased dc constant currents sinks and sources. The circuits
presented here represent a variety of commonly-used current sinks/sources built with BJTs and op-amps. The theory and
equations associated with these circuits are covered in class lectures and Chapter 1 of your course notes. Your job in this
session is to build, test and evaluate each of the given current sink/source circuits in order to expand your hands-on
experience in working with these circuits. For each circuit, make use of the parts supplied by the GTA, and the DMM
and dc power supply located on the lab bench.

II. Components and Instruments
The components and instruments required for this lab are listed below.
Components:
Op-amp: TLC274
NPN BJT: MPS8098 (4)
PNP BJT: MPS8598 (4)
Diode: 1N4148 (4)
Capacitors:
220pF 10uF
Resistors:
330 360 1K 7.5K 8.2K
9.1K 20K

Instruments:
Power supply Multimeter
Agilent E3620A Agilent 34401A

Additional:
Breadboard
Tool box
Hook-up wire

III. Characterization of Constant Current Sinks/Sources
Current sinks and sources are characterized with respect to their ability to maintain a constant output current in the
presence of varying power supply voltages. Metrics for gauging this ability are provided by measuring the change in the
output current with respect to changes in the supply voltage. The relative strength of these changes is formulated in
terms of regulation factors known as line or input regulation and load or output regulation. In addition to these factors is
the range of supply voltage for which the circuit can adequately operate. This is known as the voltage compliance range
where the minimum value in this range is more important. The equivalent circuit of a simple constant current sink is
shown in Figure 1(a) where the input and output stages are indicated. According to the voltage substitution theorem
2
, the
power supply voltage V
CC
is split into two voltage sources to bias the input and output stages separately. This is shown
in Figure 1(b) where V
CCi
and V
CCo
are initially equal to V
CC
. The circuit model of the sink is shown in Figure 1(c)
where the output current I
o
is expressed as

( ) ( ) ,
CCo
o CCi CCo C CCi
o
V
I V V I V
R
= + (1)

For an ideal current sink, I
C
is completely independent of V
CCi
and R
o
has an infinite value. However, for a non-ideal
sink, the current I
C
(V
CCi
) represents the component of I
o
generated in the input stage and controlled by the supply voltage
(V
CCi
) that biases this stage while the finite output resistance R
o
represents the component of I
o
controlled by the supply
voltage V
CCo
. Changes in these voltages produce corresponding changes in I
o
that can be measured independently. The

2
S.P. Chan, S.Y. Chan, and S.G. Chan, Analysis of Linear Networks and Systems, Addison-Wesley Publishing Co., Reading, MA, 1972.
- 49 -

input regulation S
3i
(I
o
,V
CCi
) is defined as the per-unit change in I
o
caused by a per-unit change in V
CCi
with V
CCo
held
constant at the nominal operating voltage of V
CC
; that is

( )
( )
( )
( )
( )
( )
( )
3
,
,
,
CCo CCi CC
o o
CCo CCi CC
o o
o CCi CCo
o CCi CCo o CCi
i o CCi
V V V nom CCi
o CCi
I I nom
V V V nom CCi
I I nom
I V V
I V V I V
S I V
V
I V
V
= =
=
= =
=

= =

(2)

Based on the ratio of these changes, input regulation has no units although it has a magnitude and sign that measure the
relative change in I
o
with respect to V
CCi
. The output regulation S
3o
(I
o
,V
CCo
) is defined as the per-unit change in I
o

caused by a per-unit change in V
CCo
with V
CCi
held constant at the nominal operating voltage of V
CC
; that is

bias
circuit
input
stage
output
stage
V
CC
Q
1
R
E
I
o
bias
circuit
input
stage
output
stage
V
CCi
V
CCo
R
E
I
o
(b) (a)
R
o
(c)
V
CCo
I
o
(V
CCi
,V
CCo
)
I
C
(V
CCi
)
Q
1
V
o
V
o
V
o

Figure 1
(a) Simple current sink
(b) Current sink with separate stage bias
(c) Current sink circuit model

( )
( )
( )
( )
( )
( )
( )
3
,
,
,
CCo CCi CC
o o
CCo CCi CC
o o
o CCi CCo
o CCi CCo o CCo
o o CCo
V V V nom CCo
o CCo
I I nom
V V V nom CCo
I I nom
I V V
I V V I V
S I V
V
I V
V
= =
=
= =
=

= =

(3)

It is clear that output regulation also has no units and is measure of the relative change in I
o
cause by a change in V
CCo
.
Output resistance R
o
is also used to characterize the performance of a current sink. From Figure1, R
o
is defined as


( )
( )
1
,
CCi CC
o
o CCi CCo
CCo
V V nom
R
I V V
V
=
=

(4)

- 50 -

The last metric is the minimum value of the output voltage V
o
(min) which defines the low end of the output compliance
voltage. This voltage is the minimum value of V
CCo
for which the transistor is not in deep saturation; that is,

( ) ( )
o CCo
V min V min = (5)

IV. Measurements
Photos of the breadboard layout of a typical current sink circuit are shown in Figures 2 and 3. The input and output
stages of this sink are biased with separate supply voltages according to Figure 1(b). The supply voltages are labeled
under the binding posts on the breadboard.
A. Input regulation
1. Set the power supply voltages V
CCi
and V
CCo
equal to the nominal voltage for V
CC
(V
CC
(nom)). Measure the
nominal value of the output current I
o
(nom).
2. With V
CCo
held constant, change V
CCi
by V
CCi
and measure I
o
; label as I
o
(V
CCi
).
3. Calculate the input regulation S
3i
(I
o
,V
CCi
) from

( )
( )
( )
( ) ( )
3
,
CCi o CCi o
i o CCi
o CCi
V nom I V I nom
S I V
I nom V

=

(6)

B. Output regulation
1. Set the power supply voltages V
CCi
and V
CCo
equal to the nominal voltage for V
CC
(V
CC
(nom)). Measure the
nominal value of the output current I
o
(nom).
2. With V
CCi
held constant, change V
CCo
by V
CCo
and measure I
o
; label as I
o
(V
CCo
).
3. Calculate the output regulation S
3o
(I
o
, V
CCo
) from

( )
( )
( )
( ) ( )
3
,
CCo o CCo o
o o CCo
o CCo
V nom I V I nom
S I V
I nom V

=

(7)

C. Output resistance
1. Set the power supply voltages V
CCi
and V
CCo
equal to the nominal voltage for V
CC
(V
CC
(nom)). Measure the
nominal value of the output current I
o
(nom).
2. With V
CCi
held constant, change V
CCo
by V
CCo
and measure I
o
; label as I
o
(V
CCo
).
3. Calculate the output resistance R
o
(I
o
, V
CCo
) from

( )
( ) ( )
1
,
o o CCo
o CCo o
CCo
R I V
I V I nom
V
=

(8)

D. Minimum output compliance voltage
1. Set the power supply voltages V
CCi
and V
CCo
equal to the nominal voltage for V
CC
(V
CC
(nom)). Measure the
nominal value of the output current I
o
(nom).
2. With V
CCi
held constant, decrease V
CCo
until the base-collector junction of the output transistor becomes
forward biased.
3. Label V
o
(min) with this value of V
CCo
.

- 51 -


Figure 2
Current sink breadboard layout


Figure 3
Current sink breadboard layout

- 52 -

V. DC Constant Current Sinks
A collection of three dc constant current sinks are shown in Figures 4 through 6. Design and build each of these circuits
on your breadboard according to the bias and output current specifications listed below. Take the necessary
measurements on each of these circuits to calculate the performance parameters listed in Table 1.

(a) I
bias
= 1mA, I
o
= 2mA.
(b) With a nominal voltage for V
CC
= 10V, measure and record all node to ground voltages for a voltage and current
map of each current sink circuit.
(c) Vary V
CCi
and V
CCo
to measure values for the input and output regulation factors, and the output resistance. Record
these values in Table 1 for each current sink.
(d) Set V
CCi
to its nominal V
CC
value and vary V
CCo
to measure the minimum compliance voltage V
o
(min). Record this
value in Table 1 for each current sink.

Make use of these parameters in this table to determine which current sink performs the best.

V
CC
10V Q
2
Q
1
R
1
I
o
R
2
D
1
Q
1
, Q
2
=MPS8098
D
1
=1N4148
V
o
I
bias

Figure 4
Simple current sink with diode bias

V
CC
10V
R
1
Q
1
Q
3
Q
2
R
2
R
3
20K D
1
V
o
I
o
Q
1
- Q
3
=MPS8098
D
1
=1N4148
I
bias

Figure 5
Buffered current sink with diode bias

- 53 -

V
CC
10V
R
1
D
1
R
3
C
C1
C
C2
10F
220pF
OA
1
Q
1
V
o
I
bias
OA
1
=TLC274
Q
1
=MPS8098
D
1
=1N4148
I
o

Figure 6
Current sink with current-boosting transistor

Table 1
Current sink parameters
Figure S
3i
(I
o
,V
CCi
) S
3o
(I
o
,V
CCo
) R
o
(I
o
,V
CCo
) () V
o
(min) (V)
4
5
6

VI. DC Constant Current Sources
A collection of three dc constant current sources are shown in Figures 7 through 9. Design and build each of these
circuits on your breadboard according to the bias and output current specifications listed below. Take the necessary
measurements on each of these circuits to calculate the performance parameters listed in Table 2.

(a) I
bias
= 1mA, I
o
= 2mA.
(b) With a nominal voltage for V
CC
= 10V, measure and record all node to ground voltages for a voltage and current
map of each current source circuit.
(c) Vary V
CCi
and V
CCo
to measure values for the input and output regulation factors, and the output resistance. Record
these values in Table 2 for each current source.
(d) Set V
CCi
to its nominal V
CC
value and vary V
CCo
to measure the minimum compliance voltage V
o
(min). Record this
value in Table 2 for each current source.

Make use of these parameters in this table to determine which current source performs the best.

- 54 -

V
CC
10V
D
1
Q
1
Q
2
R
1
R
2
I
o
V
o
Q
1
, Q
2
=MPS8598
D
1
=1N4148
I
bias

Figure 7
Simple current source with diode bias

V
CC
10V
D
1
R
3
20K R
2
Q
1
Q
2
Q
3
R
1
V
o
I
o
Q
1
- Q
3
=MPS8598
D
1
=1N4148
I
bias

Figure 8
Buffered current source with diode bias

V
CC
10V
R
1
D
1
C
C1
C
C2
220pF
10F
R
3
I
o
V
o
Q
1
OA
1
=TLC274
Q
1
=MPS8598
D
1,2,3
=1N4148
OA
1
I
bias
D
2
D
3

Figure 9
Current source with current-boosting transistor
- 55 -


Table 2
Current source parameters
Figure S
3i
(I
o
,V
CCi
) S
3o
(I
o
,V
CCo
) R
o
(I
o
,V
CCo
) () V
o
(min) (V)
7
8
9

VII. Example
The schematic of the current sink shown in Figure 1(a) is shown below in Figure 10. This sink is biased with voltage
sources V
CCi
and V
CCo
according to the circuit in Figure 1(b).

V
CCi
Q
2
Q
1
R
1
I
o
R
2
D
z
Q
1
, Q
2
=2N3904
D
z
=1N750A
V
o
I
bias
V
CCo
V
C1
V
E1
V
E2
7.4514K
1.7853K
I
E

Figure 10
Simple current sink with separate input and output bias

(a) Design target:
I
bias
= 800A
I
o
= 2mA.
Values shown for R
1
and R
2
are measured values.

(b) Measured values for a voltage and current map under nominal operating conditions:
V
CCi
= 10.089V V
CCo
= 10.0615V
V
C1
= 4.2758V V
E1
= 3.6261V
V
E2
= 3.6113V V
R1
= 5.8076V
I
bias
= 779.3972A I
o
= 2.0128mA

(c) Measured values for regulation factors, output resistance and minimum output voltage compliance:
(i.) input regulation:

Table 3
Measurements for S
i
(I
o
,V
CCi
) (V
CCo
= 10.069V)
Point V
CCi
(V) I
o
(A)
1 (nom) 10.0906 2.013m
2 9.063 1.972m

- 56 -


( )
( )
( )
( )
1 1 2
3
1 1 2
3
,
10.0906 2.013 1.972
, 0.2
2.013 10.0906 9.063
CCo CCo
CCi o CCi o o
i o CCi
o CCi o CCi CCi
V V
i o CCi
V nom I V I I
S I V
I nom V I V V
V mA mA
S I V
mA V V

= =




= =

(9)

(ii.) output regulation:

Table 4
Measurements for S
o
(I
o
,V
CCo
) (V
CCi
= 10.0901V)
Point V
CCo
(V) I
o
(A)
1 (nom) 10.067 2.013m
2 9.0418 2.0123m


( )
( )
( )
( )
1 1 2
3
1 1 2
3
,
10.067 2.013 2.0123
, 0.003413
2.013 10.067 9.0418
CCi CCi
CCo o CCo o o
o o CCo
o CCo o CCo CCo
V V
o o CCo
V nom I V I I
S I V
I nom V I V V
V mA mA
S I V
mA V V

= =




= =

(10)

(iii.) output resistance

( )
1 2
1 2
1 1 1
, 1.465143
2.013 2.0123
10.067 9.0418
CCi CCi
o o CCo
o o o
CCo CCo CCo
V V
R I V M
mA mA
I I I
V V
V V V
= = = =

(11)

(iv.) minimum compliance voltage:
V
CCi
= 10.0704V
V
CCo
= 4.3933V
V
CB2
0V
V
o
(min) = 4.3933V





- 57 -

Lab Experiment No. 4 Self-Biased Current Sinks and Sources

I. Introduction
The purpose of this lab is to evaluate the performance of self-biased dc constant currents sinks and sources. The circuits
presented here represent two commonly-used current sinks/sources built with self-biased n and p-channel JFETs. The
theory and equations associated with these circuits are covered in class lectures and Chapter 1 of your course notes.
Your job in this session is to build, test and evaluate each of the given current sink/source circuits in order to expand your
hands-on experience in working with these circuits. For each circuit, make use of the parts supplied by the GTA, and the
DMM and dc power supply located on the lab bench.

II. Components and Instruments
The components and instruments required for this lab are listed below.
Components:
NJFET: 2N3819 (2)
PJFET: J271 (2)
Resistors:
470 820 1.2K 5.1K 9.1K
10K 15K
Potentiometer (trim pot):
10K

Instruments:
Power supply Multimeter
Agilent E3620A Agilent 34401A

Additional:
Breadboard
Tool box
Hook-up wire

III. Single-Stage, Source-Biased J FET Current Sink/Source
The schematic of a single-stage n-channel JFET current sink biased with a resistor in the source is shown in Figure 1.
This circuit is known as the single-stage, source-biased JFET current sink. It is also known as a current diode. For the
device in the saturation region where the drain-source voltage V
DS
is defined by

J
1
I
o
V
DS
V
GS
R
S
V
o
R
o

Figure 1
Single-stage, source-biased current sink
( )
DS P GS
V V V (1)

the sinks output current I
o
is identical to J
1
s drain current I
D
and is expressed as

- 58 -


( )
( )
2
1 1
GS
o D DSS DS
P
V
I I I V
V


= = +



(2)

In these equations, V
P
is the device pinch-off voltage, I
DSS
is the drain-source saturation current with the gate shorted to
the source and is the channel-length modulation parameter in V
-1
. With the gate shorted to ground, the gate-source
voltage is


GS S o
V R I = (3)

If the source resistor R
S
is known, equations (2) and (3) are combined under the assumption V
DS
<<1 to produce a
quadratic equation for the output current


2 2
2
2 1
0
S P P
o o
S P DSS S
R V V
I I
R V I R

+ + =


(4)

The combination of these two equations represents the intersection of a parabola (equation (2)) with a straight line
(equation (3)). Therefore, the solution of this quadratic equation yields two values for I
o
determined from the
intersection points. However, only one I
o
value is correct since the other lies outside the valid operating region of the
JFET. The value of R
S
that will produce a value for I
o
which will be less than or equal to I
DSS
is calculated from

1
o P
S
o DSS
I V
R
I I

=


(5)

If V
P
and I
DSS
are not known, a variable resistor (potentiometer) is placed in the source and adjusted to produce the
desired value for I
o
. The potentiometer is then replaced by a fixed resistor that closely matches the resistance of the
adjusted value. The small-signal output resistance R
o
of the sink is calculated from


( )
1
o o S mf o
R r R g r = + + (6)

In this expression, r
o
is the output resistance of the JFET determined from the slope of the output characteristics curve
and g
mf
is the forward transconductance. These small-signal bias-dependent components are calculated from


1
DS
o
D
V
r
I

+
= (7)

and


2
DSS D
mf
P
I I
g
V
= (8)

where I
D
is equal to I
o
. Finally, the minimum output voltage compliance is

( )
o P
V min V = (9)

The schematic for the current source version of this circuit is shown in Figure 2 where a p-channel JFET is used.

- 59 -

R
S
V
SG
J
1
V
SD
V
o
R
o
I
o

Figure 2
Single-stage, source-biased PJFET current source

IV. Cascode, Source-Biased J FET Current Sink/Source
While the output resistance of the single-stage current sink in Figure 1 can be reasonably large, another source-biased
JFET current sink is capable of producing an output resistance that is several orders of magnitude greater. This is the
cascode, source-biased JFET current sink shown in Figure 3. In this circuit, J
1
and J
2
are connected in the cascode
configuration such that the output current I
o
is identical to the drain currents of both JFETs. To insure J
1
is operating in
the saturation region, it is necessary that

J
2
J
1
I
o
R
S
V
GS2
V
GS1
V
DS1
V
o
R
o

Figure 3
Cascode, source-biased current sink


1 1
1
o
DS P
DSS
I
V V
I
(10)

To insure J
2
is operating similarly, I
o
is restricted by


2
1
1 2
1 2
P
o
p p
DSS DSS
V
I
V V
I I

+


(11)
- 60 -

Under these conditions, the output current is determined from the solution of a quadratic equation similar to that in
equation (4); that is,


2 2
2 2 2
2 2
2 1
0
S P P
o o
S P DSS S
R V V
I I
R V I R

+ + =


(12)

where V
P2
and I
DSS2
are the pinch-off voltage and drain-source saturation current, respectively, of device J
2
. If these
values are known, the source resistor R
S
is determined from an equation similar to equation (5)


2
2
1
o P
S
o DSS
I V
R
I I

=


(13)

The small-signal output resistance R
o
of the cascode sink is calculated from


( ) ( )
1 2 1 1 2 2 1 1
1 1 1
o o o mf o S mf o mf o
R r r g r R g r g r

= + + + + +

(14)
which is much larger than R
o
in equation (6) for the single-stage sink. The minimum output voltage compliance is
determined from

( )
1 o P S o
V min V R I = + (15)

Clearly, the minimum compliance for the cascode design is greater than that for the single stage design. A cascode
current source using PJFETs is shown in Figure 4.

R
S
I
o
J
1
J
2
V
SG2
V
SG1
V
SD1
V
o
R
o

Figure 4
Cascode, source-biased current source

- 61 -

V. NJ FET Current Sink Measurements
Schematics for single-stage and cascode source-biased NJFET current sinks are shown in Figure 5. Design and build
each of these circuits on your breadboard according to the output current specifications listed below. Take the necessary
measurements listed below on each of these circuits.

J
2
J
1
I
o
R
S
V
o
R
o
J
1
, J
2
=2N3819
R
S
=10K trim pot
V
DD
10V
J
1
I
o
R
S
V
o
R
o
V
DD
10V
J
1
=2N3819
R
S
=10K trim pot
(a) (b)

Figure 5
(a) Single-stage source biased current sink
(b) Cascode source biased current sink

(a) Set V
DD
to 10V and adjust the potentiometer R
S
for a nominal value of I
o
of 2mA.
(b) Measure R
S
and replace the pot with a fixed resistance as close as possible to the measured value. Record the value
of this resistance in Table 1.
(c) Measure V
DD
and I
o
for their nominal values; V
DD
(nom) and I
o
(nom). Record these values in Table 1.
(d) Vary V
DD
to measure values for the output resistance R
o
and the output regulation factor S
3o
(I
o
, V
DD
). Record these
values in Table 1 for each current sink.


( )
( )
( )
( )
( ) ( )
( )
3
1
1
,
o
o DD
DD
DD o DD DD
o o DD
o DD o o
R
I V
V
V nom I V V nom
S I V
I nom V I nom R
=

= =

(16)

(e) Set V
DD
to its nominal value and reduce it to measure the minimum compliance voltage V
o
(min). Record this value
in Table 1 for each current sink.

Make use of these parameters in this table to determine which current sink performs the best.

- 62 -


Table 1
Current sink parameters
Parameter Single-stage (Figure 5(a)) Cascode (Figure 5(b))
R
S
(fixed) ()
V
DD
(nom) (V)
I
o
(nom) (A)
R
o
()
S
3o
(I
o
,V
DD
)
V
o
(min)

VI. PJ FET Current Source Measurements
Schematics for single-stage and cascode source-biased PJFET current sources are shown in Figure 6. Design and build
each of these circuits on your breadboard according to the output current specifications listed below. Take the necessary
measurements listed below on each of these circuits.

(a) Set V
DD
to 10V and adjust the potentiometer R
S
for a nominal value of I
o
of 2mA.
(b) Measure R
S
and replace the pot with a fixed resistance as close as possible to the measured value. Record the value
of this resistance in Table 2.
(c) Measure V
DD
and I
o
for their nominal values; V
DD
(nom) and I
o
(nom). Record these values in Table 2.
(d) Vary V
DD
to measure values for the output resistance R
o
and the output regulation factor S
3o
(I
o
, V
DD
). Record these
values in Table 2 for each current sink.


( )
( )
( )
( )
( ) ( )
( )
3
1
1
,
o
o DD
DD
DD o DD DD
o o DD
o DD o o
R
I V
V
V nom I V V nom
S I V
I nom V I nom R
=

= =

(17)

(e) Set V
DD
to its nominal value and reduce it to measure the minimum compliance voltage V
o
(min). Record this value
in Table 2 for each current sink.

Make use of these parameters in this table to determine which current sink performs the best.
- 63 -

R
S
J
1
V
o
R
o
I
o
V
DD
10V
J
1
=J 271
R
S
=10K trim pot
R
S
I
o
J
1
J
2
V
o
R
o
V
DD
10V
J
1
, J
2
=J 271
R
S
=10K trim pot
(a) (b)


Figure 6
(a) Single-stage source biased current source
(b) Cascode source biased current source

Table 2
Current source parameters
Parameter Single-stage (Figure 6(a)) Cascode (Figure 6(b))
R
S
(fixed) ()
V
DD
(nom) (V)
I
o
(nom) (A)
R
o
()
S
3o
(I
o
,V
DD
)
V
o
(min)



- 64 -

Lab Experiment No. 5 Current Mirrors

I. Introduction
The purpose of this lab exercise is to investigate the operation and performance of transistor current mirrors. The circuits
presented here represent a variety of commonly-used current mirrors built with NPN and PNP BJTs. The theory and
equations associated with these circuits are covered in class lectures and Chapter 1 of your course notes. Your job in this
session is to design, build, and test each current mirror to expand your hands-on experience in working with these
circuits. Make use of the parts supplied by the GTA and the instruments located on the lab bench to perform this
investigation.

II. Components and Instruments
The components and instruments required for this lab are listed below.
Components:
Resistors:
160 330 (2) 620 10K

Transistors
NPN: MPS8098 (8) PNP: MPS8598 (8)
NJFET: 2N3819 PJFET: J271

Instruments:
Power supply Multimeter
Agilent E3620A Agilent 34401A

Additional:
Breadboard
Tool box
Hook-up wire

III. Characterization of Current Mirrors
Current mirrors play important roles in a wide variety of analog circuits both discrete and integrated. These subcircuits
are instrumental in transferring and scaling bias and signal currents around the host circuit for the realization of precise
high-speed responses. Due to design similarities, current mirrors share common characteristics with current sinks and
sources. Output resistance R
o
and minimum compliance voltage V
o
(min) are two important parameters associated with
mirrors. Precise current scaling and sensitivity to load changes are also important mirror parameters.


- 65 -

IV. NPN Current Mirror Topologies
Schematics for three multiple output NPN current mirrors are shown in Figure1 through 3. These mirrors are the
buffered Widlar, the cascode, and the four transistor Wilson. The reference current (I
ref
) supplied to each of these
mirrors is 2mA while the outputs are scaled replicas of I
ref
ranging from 1mA to 4mA as indicated. The circuit shown in
Figure 4 is a current source that provides I
ref
to these mirrors. Your job is to do the following.
(a) Design each mirror to replicate (mirror) the 2mA input reference I
ref
into the unloaded output currents I
oa
, I
ob
, and I
oc

of 4mA, 2mA, and 1mA, respectively. Generate I
ref
from the single-stage, source-biased PJFET current source
built in Lab 2(b). You will have to design this circuit as well.
(b) Test the performance of each mirror by measuring the output currents (I
oa
, I
ob
, and I
oc
), the output resistance of each
output (R
oa
, R
ob
, and R
oc
) and the minimum compliance voltage of each output (V
oa
(min), V
ob
(min), and V
oc
(min)).
Enter these values into Table 1 where indicated.
(c) Draw schematics for all circuits (mirrors and current sources) complete with component values.

+V
CC
+15V
I
ref
2mA
Q
1
Q
2
Q
a
Q
b
Q
c
R
E1
R
E2
R
Ea
R
Eb
R
Ec
I
oa
I
ob
I
oc
4mA 2mA 1mA

Figure 1
NPN buffered Widlar current mirror

+V
CC
+15V
I
ref
2mA
Q
1
Q
2
Q
b1
R
E1
R
Ea
R
Ec
R
Eb
I
oc
I
oa
I
ob
4mA 2mA 1mA
Q
a1
Q
c2
Q
a2
Q
b2
Q
c1

Figure 2
NPN cascode current mirror
- 66 -


+V
CC
+15V
I
ref
2mA
Q
1
Q
2
Q
3
Q
4
Q
b
R
E1
R
E2
R
Ea
R
Ec
R
Eb
I
oc
I
oa
I
ob
4mA 2mA 1mA
Q
a
Q
c

Figure 3
NPN Wilson current mirror

V
CC
15V
R
S
I
ref
=2mA
J
1
J
1
=J 271
NPN
current
mirror

Figure 4
I
ref
source for an NPN current mirror


- 67 -

Table 1
NPN current mirror parameters
Parameter Buffered Widlar Cascode Wilson
I
ref

I
oa

I
ob

I
oc

R
oa

R
ob

R
oc

V
oa
(min)
V
ob
(min)
V
oc
(min)


- 68 -

V. PNP Current Mirror Topologies
Schematics for three multiple output PNP current mirrors are shown in Figure5 through 7. These mirrors are the
buffered Widlar, the cascode, and the four transistor Wilson. The reference current (I
ref
) supplied to each of these
mirrors is 2mA while the outputs are scaled replicas of I
ref
ranging from 1mA to 4mA as indicated. The circuit shown in
Figure 8 is a current sink that provides I
ref
to these mirrors. Your job is to do the following.
(a) Design each mirror to replicate (mirror) the 2mA input reference I
ref
into the unloaded output currents I
oa
, I
ob
, and I
oc

of 4mA, 2mA, and 1mA, respectively. Generate I
ref
from the single-stage, source-biased NJFET current sink
built in Lab 2(b). You will have to design this circuit as well.
(b) Test the performance of each mirror by measuring the output currents (I
oa
, I
ob
, and I
oc
), the output resistance of each
output (R
oa
, R
ob
, and R
oc
) and the minimum compliance voltage of each output (V
oa
(min), V
ob
(min), and V
oc
(min)).
Enter these values into Table 2 where indicated.
(c) Draw schematics for all circuits (mirrors and current sources) complete with component values.

+V
CC
+15V
I
ref
2mA
Q
1
Q
2
Q
a
Q
b
Q
c
R
E1 R
E2
R
Ea
R
Eb
R
Ec
I
oa
I
ob
I
oc
4mA 2mA 1mA

Figure 5
PNP buffered Widlar current mirror

+V
CC
+15V
I
ref
2mA
Q
1
Q
2
Q
b1
R
E1
R
Ea
R
Ec
R
Eb
I
oc
I
oa
I
ob
4mA 2mA 1mA
Q
a1
Q
c1
Q
a2
Q
b2
Q
c2

Figure 6
PNP cascode current mirror
- 69 -

+V
CC
+15V
I
ref
2mA
Q
1
Q
3
Q
b
R
E1
R
E2
R
Ec
R
Eb
I
oc
I
oa
I
ob
4mA 2mA 1mA
Q
a
Q
c
Q
2
Q
c2
Q
4
R
Ea

Figure 7
PNP Wilson current mirror

V
CC
15V
R
S
J
1
J
1
=2N3819
I
ref
=2mA
PNP
current
mirror

Figure 8
I
ref
circuit for a PNP current mirror



- 70 -

Table 2
PNP current mirror parameters
Parameter Buffered Widlar Cascode Wilson
I
ref

I
oa

I
ob

I
oc

R
oa

R
ob

R
oc

V
oa
(min)
V
ob
(min)
V
oc
(min)



- 71 -

Lab Experiment No. 6 Single-Stage Amplifiers

I. Introduction
The purpose of this lab exercise is to design single-stage BJT amplifiers. The circuits presented here are single-stage
BJT class-A amplifiers biased with preferred biasing methods. The theory and equations associated with these circuits
are covered in class lectures and Chapter 3 of your course notes. Your job in this session is to design, build, and test each
amplifier to expand your hands-on experience in working with these circuits. Make use of the parts supplied by the GTA
and the instruments located on the lab bench to produce these amplifiers.

II. Components and Instruments
The components and instruments required for this lab are listed below.
Components:
Resistors:
200 470 620 1K 1.3K 1.6K
4.7K 10K 39K 270K 300K 680K
750K

BJTs:
NPN BJT: MPS8098
PNP BJT: MPS8598

Capacitors:
10uF (2) 50uF

Potentiometer:
1K trim pot

Instruments:
Power supply Multimeter
Agilent E3620A Agilent 34401A

Additional:
Breadboard
Tool box
Hook-up wire

- 72 -

III. Voltage Divider Bias Amplifier Circuit
A single-stage NPN amplifier biased by the voltage divider circuit is shown in Figure 1. The amplifier is driven by a
transducer consisting of the ac signal source V
S
(s) and the 200 source resistance R
S
. The load driven by the amplifier
is the 10K load resistor R
L
.

Definitions


( )
( )
( )
( )
( )
( )
( )
( )
0
200
10
L
S
unloaded terminal voltage gain
loaded transducer voltage gain
input impedance with R connected
output impedance with R connec
S
L
S
L
o
vt
R in
R
o
vs
R S
R K
in
out
V s
A s
V s
V s
A s
V s
Z s
Z s
=
=
=
=
=
=
=
= ted


Device model parameters
Model parameters for Q
1
:


150
0.65 @500
0
F
BE
CBO
V V A
I

=
=
=


Amplifier specifications
Design this amplifier to meet the following specifications:


( )
( )
10V dc supply voltage
max
500 dc collector current
2
0 75 input impedanc
CC
C
CQ
in
V
I
I A
Z K

=
= =
=
( )
( )
3 CQ F
0
3
e at dc
, 0.3 sensitivity of I with respect to
3 10.0V/V unloaded terminal voltage gain at 3KHz
S
L
CQ F
o
vt
R
in
R
f KHz
S I
V
A KHz
V

=
=
=
=
= =


(a) Trim the values of R
B1
and /or R
B2
to obtain a dc collector current I
CQ
of 500A within 5% (475A I
CQ

525A).
(b) To adjust the magnitude of the terminal voltage gain A
vt
at 3KHz, apply the emitter circuit shown in Figure 2 where
R
Ep
is a 1K trim pot.
Measurements
(a) Provide a hand-drawn schematic of your design with all component values.
(b) Measure and record all dc node voltages and branch currents in the voltage and current map Table 1(a).
(c) Measure and record in Table 1(b) the indicated amplifier parameters. Include drawn schematics illustrating how
these parameters are measured.

- 73 -

+V
CC
V
S
(s)
R
B2
R
B1
R
C
R
E1
R
E2
C
i
C
o
C
E
R
S
200
10K
R
L
V
o
(s)
10F
10F
50F
I
CQ
transducer load
V
in
(s)
Z
out
(s) Q
1
amplifier
Q
1
=MPS8098 NPN
Z
in
(s)
V
B
V
C
V
E

Figure 1
Voltage divider bias circuit

R
E1
R
E2
C
E
C
E
R
Ep
R
E3
R
E1
+R
E2
=R
Ep
+R
E3
=R
E
1K

Figure 2
Adjustable emitter circuit

Table 1(a)
Measured voltage and current map
Variable Value
V
CC

V
C

V
B

V
E

I
RB1

I
RB2

I
CQ

I
B

I
E

- 74 -


Table 1(b)
Amplifier parameters
Parameter 1KHz 3KHz 10KHz
|A
vt
()|
|A
vs
()|
|Z
in
()|
|Z
out
()|

IV. Self-Bias Amplifier Circuit
A single-stage amplifier that employs a PNP BJT biased in the self-bias circuit is shown in Figure 3. This amplifier is
driven by a transducer similar to the one in Figure 1 and also drives a 10K load resistor R
L
. Definitions of the various
voltage gains and driving-point impedance functions are identical to those for the previous amplifier.

Device model parameters
Model parameters for Q
1
:


150
0.65 @1.5
0
F
BE
CBO
V V mA
I
=
=
=


Amplifier specifications
Design this amplifier to meet the following specifications:


( )
3
15V dc supply voltage
1.5 dc collector current
, 0.2 sens
CC
CQ
CQ F
V
I mA
S I R
=
=
=
( )
CQ F
C E
0
3
itivity of I with respect to R
6 R to R ratio
3 10.0V/V unloaded terminal voltage gain at 3KHz
S
L
C
E
o
vt
R
in
R
f KHz
R
R
V
A KHz
V
=
=
=
=
= =


(a) Trim the value of R
B
to obtain a dc collector current I
CQ
of 1.5mA within 5% (1.425mA I
CQ
1.575mA).
(b) To adjust the magnitude of the terminal voltage gain A
vt
at 3KHz, apply the emitter circuit shown in Figure 2 where
R
Ep
is a 1K trim pot.
Measurements
(a) Provide a hand-drawn schematic of your design with all component values.
(b) Measure and record all dc node voltages, branch currents, and the sensitivity of I
CQ
with respect to R
B
(S
3
(I
CQ
,R
B
)) in
the voltage and current map Table 2(a).
(c) Measure and record in Table 2(b) the indicated amplifier parameters. Include drawn schematics illustrating how
these parameters are measured.

- 75 -

V
S
(s)
R
S
200
C
i
C
E
R
E1
R
E2
R
C
R
B
R
L
+V
CC
C
o
50F
10F
10F
10K
V
o
(s)
Q
1
V
in
(s)
Z
in
(s) Z
out
(s)
transducer load
I
CQ
amplifier
Q
1
=MPS8598 PNP
V
B
V
C
V
E

Figure 3
Self-bias circuit

Table 2(a)
Measured voltage and current map
Variable Value
V
CC

V
C

V
B

V
E

I
RB

I
RC

I
CQ

I
B

I
E

S
3
(I
CQ
,R
B
)


- 76 -


Table 2(b)
Amplifier parameters
Parameter 1KHz 3KHz 10KHz
|A
vt
()|
|A
vs
()|
|Z
in
()|
|Z
out
()|


- 77 -

Lab Experiment No. 7 Operational Amplifier Design

I. Introduction
The purpose of this lab exercise is to build and test an operational amplifier (op-amp). The op-amp presented here is a
voltage feedback type constructed from discrete PJFET (J271), NPNBJT (MPS8098), and PNPBJT (MPS8598). Your
job in this session is to build and test the given circuit to expand your hands-on experience in working with op-amps.
Make use of the parts supplied by the GTA and the instruments located on the lab bench to perform this experiment.

II. Components and Instruments
The components and instruments required for this lab are listed below.
Components:
NPN BJT: MPS8098 (11)
PNP BJT: MPS8598 (9)
PJFET: J271
Capacitors: 120pf
Resistors:
270 (2) 390 (4) 560 1K (3) 3.3K (3)
5.1K (2) 8.2K 10K (5)

Instruments:
Power supply Multimeter
Agilent E3620A Agilent 34401A
Function generator Oscilloscope
Agilent 33120A Agilent 54621A

Additional:
Breadboard
Tool box
Hook-up wire

III. The OP3444c Op-Amp
The schematic and symbol for the OP3444c BJT voltage feedback operational amplifier (VFOA) is shown in Figure 1(a)
and (b), respectively. The nominal operating conditions for this amplifier are given below.


5.0
27
CC EE
V V V
T C
= =
=
(1)

In this lab session, you will become familiar with important procedures and steps involved in the actual design cycle of
an op-amp such as this one.

Part 1. Design. Calculate the value of the resistor R
bias
in the source of J
1
that will set the amplifier bias current (I
bias
) to
2mA. Assume J
1
has the model parameters listed below.


( )
10
2.5
0
DSS
P GS off
I mA
V V V

=
= =
=
(2)

Record the value of R
bias
in first column of Table 1 where indicated.

Part 2. Analytical. With I
bias
of 2mA, perform a first-order pencil and paper circuit analysis of the op-amp in the open-
loop test circuit shown in Figure 2(a). Use the transistor parameters below for this analysis.

- 78 -


7 8
7 8
(for all transistors except Q and Q )
100
0.65
BE
V V

=
= =
=
(3)

You may assume the op-amp is nearly ideal so that when placed in this test circuit the input voltages (V
p
and V
n
), and the
output voltage and current (V
out
and I
out
) are zero. Use these conditions to calculate the complete dc voltage and current
map of the op-amp in the open-loop configuration. Record these voltages and currents in the first column of Table 1.

Part 3. Simulation. Simulate the OP3444c with PSPICE. Use the SPICE Gummel-Poon (SGP) model for the MPS8098
(NPN) and MPS8598 (PNP) BJTs, and the Shichman-Hodges model for the J271 PJFET provided in the PSPICE
library.
(a) Place a battery (V
id
) across the differential input terminals as shown in Figure 2(b). Adjust R
bias
to set I
bias
to 2mA.
Record the value of R
bias
in the second column of Table 1 where indicated.
(b) Sweep the voltage V
id
to generate and plot the open-loop output voltage transfer curve (VTC). From the VTC,
calculate the input offset voltage (V
os
) and the differential mode voltage gain (G
vdm
).
(c) In the circuit in Figure 2(b), set V
id
equal to V
os
in order to set V
out
to zero; that is V
id
= V
os
so that V
out
= 0V.
Perform a dc operating point simulation on the amplifier to obtain the open-loop dc voltages and currents shown on
the schematic in Figure 1(a). Record these voltages and currents in the second column of Table 1.

Part 4. Breadboard. Build the OP3444c on a breadboard with J271, MPS8098, and MPS8598 transistors, 1% discrete
resistors, and 5% capacitors.
(a) Bias the breadboard op-amp with the closed-loop circuit shown in Figure 3(a). Adjust R
bias
to set I
bias
to 2mA.
Record the value of R
bias
in the third column of Table 1 where indicated.
(b) Measure the complete dc voltage and current map. Record these voltages and currents in the third column of Table
1.
(b) Place the op-amp in the inverting-gain configuration in Figure 3(b)
(1) generate the Bode plot of the closed-loop voltage gain magnitude (dB), and
(2) record values for the closed-loop parameters in Table 2.

Part 5. Compare and comment.
(a) Compare the values of R
bias
, and the dc voltages and currents recorded in Table 1. Comment on the accuracy of
analytical calculations versus simulation versus actual breadboard measurements. How close are the values from
calculations and simulations to the actual measured values?
(b) Comment on the inverting gain amplifier performance results recorded in Table 2.
(c) Comment on any major differences among the data in the tables. Determine reasons for these differences.


- 79 -

R
bias
V
p
V
n
Q
1
Q
2
J
1
Q
4
Q
5
Q
6
Q
19
Q
20
+V
CC
V
out
-V
EE
I
p
I
n
I
bias
V
E2
V
C8
V
E1
V
E3
I
C7
V
C7
V
E18
R
E3
10K R
E1
R
E2
R
E18
560
390 270
I
C3
I
C14
I
C6
V
S1
V
E12
V
E16
V
E17
V
E5
C
c
V
C13
V
E4
V
E9
I
C18
I
C15
390 R
E6
270
I
E19
I
E20
I
VEE
I
VCC
(a)
(b)
120pF
I
out
390 10K
10K
10K
390
Q
3
R
E4
R
E5
Q
7
Q
8
Q
9
Q
10
Q
11
Q
12
Q
13
Q
14
Q
15
Q
16
Q
17
Q
18
R
E14
R
E15
R
E12
R
E9
V
E6
V
E14
V
E15
V
B5
V
B2
I
C8
+V
CC
-V
EE
V
out
V
p
V
n
I
p
I
n
I
VEE
I
VCC
OP3444c
V
C6
I
C2
I
C5
I
C9
I
C12
I
C13
I
C16
I
C17

Figure 1
(a) OP3444c schematic
(b) Symbol
- 80 -

OP3444c
V
p
V
n
V
out
+V
CC
-V
EE
5V
5V
OP3444c
V
p
V
n
V
out
+V
CC
-V
EE
5V
5V
V
id
(a)
(b)

Figure 2
Open-loop test circuit for
(a) pencil and paper analysis
(b) simulation of the VTC

OP3444c
R
F
R
Gn
R
Gp
10K
5.1K
3.3K
V
out
+V
CC
-V
EE
5V
5V
V
n
V
p
(a)
(b)
OP3444c
R
F
R
Gn
R
Gp
10K
5.1K
3.3K
V
out
+V
CC
-V
EE
5V
5V
V
n
V
p
V
in

Figure 3
(a) Closed-loop zero input test circuit for dc measurements
(b) Inverting gain amplifier configuration
- 81 -


Table 1
DC Voltage and Current Map
Voltage/
current
Analytical Simulation Breadboard
R
bias

V
CC
5V
V
EE
5V
V
S1

V
B2

V
E1

V
E2

V
E3

V
B5

V
E4

V
E5

V
E6

V
C6

V
C7

V
C8

V
E9

V
E12

V
C13

V
E14

V
E15

V
E16

V
E17

V
E18

V
p
0.0V
V
n
0.0V
- 82 -

V
out
0.0V
I
bias

I
C2

I
C3

I
C5

I
C6

I
C7

I
C8

I
C9

I
C12

I
C13

I
C14

I
C15

I
C16

I
C17

I
C18

I
E19

I
E20

I
p

I
n

I
out
0.0A
I
VCC

I
VEE



- 83 -


Table 2
Inverting gain amplifier performance
Parameter Description Breadboard Units
G
VI
(0) DC voltage gain V/V
f
AI
-3dB Bandwidth Hz
GBW
I
Gain-bandwidth product Hz
SR
p
Positive slope slew-rate V/s
SR
n
Negative slope slew-rate V/s



- 84 -

Lab Experiment No. 8 Amplifier Networks

I. Introduction
The purpose of this lab session is to gain familiarity with several well-known amplifier circuits built with standard
operational amplifiers. The theory and derivations associated with each of the circuits listed below has been covered
both in class and in homework assignments. Basically, your job in this session is to design (where necessary), build, test,
and evaluate each of these circuits in order to expand your hands-on experience in working with operational amplifiers.
For each circuit listed below, use TLC274 operational amplifiers, standard 5% resistors, a 5 volt dc power supply, and
an ac signal generator. For measurements, use ac voltmeters, DVMs, and oscilloscopes.

II. Components and Instruments
The components and instruments required for this lab are listed below.
Components:
Op-amp:
TLC274
Resistors:
510 5.1K 10K 18K 20K
30K 39K 51K
10K single-turn potentiometer

Instruments:
Function generator Oscilloscope
Agilent 33120A 15MHz Agilent 54621A 60MHz dual-channel
Power supply Multimeter
Agilent E3620A Agilent 34401A

Additional:
Breadboard
Tool box
Hook-up wire
Oscilloscope probes

III. Lab Assignment
Build and perform measurements on the following amplifier networks.

A. Amplifier No. 1. An inverting-gain amplifier with a dc voltage gain of -5.0 and an input resistance of 10.0K.
Measure and plot the magnitude of the voltage gain (dB) over frequency from 10Hz to 15MHz. Indicate on this plot
the -3dB bandwidth and calculate the amplifier GBW.
B. Amplifier No. 2. A non-inverting-gain amplifier with a dc voltage gain of +4.0 and an input resistance of 10.0K.
Measure and plot the magnitude of the voltage gain (dB) over frequency from 10Hz to 15MHz. Indicate on this plot
the -3dB bandwidth and calculate the amplifier GBW.
C. Amplifier No. 3. A dual-input difference amplifier with a dc voltage gain of 2.0 and input resistances of 10.0K.
Measure and plot the magnitude of the voltage gain (dB) for each input over frequency from 10Hz to 15MHz.
Indicate on this plot the -3dB bandwidth and calculate the GBW for each input.
D. Amplifier No. 4. The dual-output audio panpot amplifier (see problem 1.25 Ref .1) shown in Figure 1. Determine
the 1KHz voltage gain at each output as the pot R
P
is varied over its full range.
E. Amplifier No. 5. The bridge amplifier (see problem 1.74 Ref. 1, Ref. 2) shown in Figure 2. Design this amplifier
for a differential output voltage gain of 8. Determine the maximum undistorted peak-to-peak voltage swing across
the load resistor R
L
at 1KHz.

IV. References
1. S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, 3rd Ed., The McGraw-Hill
Companies, Inc., New York, NY, 2002, (ISBN 0-07-232084-2).
2. NSC data sheet, LM4991, 3W Audio Power Amplifier with Shutdown Mode, Audio Power Amplifier Series,
National Semiconductor Corporation, 2003.
- 85 -

R
2L
R
1L
R
3L
R
P
R
1R
R
3R
R
2R
20K
10K 5K
+5V
+5V
10K
OA
L
OA
R
V
oR
V
oL
20K
10K 5K
V
in
-5V
-5V
right channel
left channel

Figure 1
Audio panpot amplifier

V
in
R
1a
10K
R
2a
V
o1
V
o2
R
L
510
R
1b
10K
R
2b
OA
1
OA
2
+5V
+5V
-5V
-5V
V
o

Figure 2
Bridge amplifier
(aka Boomer Amplifier)



- 86 -

Lab Experiment No. 9 Op-Amp Test and Measurement

I. Introduction
The purpose of this lab exercise is to test an operational amplifier (op-amp) and to measure a set of its open-loop
parameters. The results of these measurements provide important parameters for an op-amp data sheet. Your job in this
lab experiment is to apply test circuit OATC1 shown in Figure 1 to a given device under test (DUT). The description of
this test circuit and the procedures for taking measurements from the DUT are explained in the paper OATC1: A
Universal Test Circuit for Measuring Op-Amp Parameters attached to this experiment. Make use of the parts and the
DUT supplied by the GTA, and the instruments located on the lab bench to perform this experiment.

II. Components and Instruments
The components and instruments required for this lab are listed below.
Components:
Op-amp: OP-07 (3) LM741 DUT
Capacitors: 300nF, NPO multilayer ceramic
Resistors:
100 (2) 2K (5) 30K 51K (3) 100K (2)
Potentiometer:
10K, trimpot

Instruments:
Power supply Multimeter
Agilent E3620A Agilent 34401A
Function generator Oscilloscope
Agilent 33120A Agilent 54621A

Additional:
Breadboard
Tool box
Hook-up wire

III. Op-amp Parameters and the Data Sheet
Download the data sheet for the LM741 op-amp. From this data sheet, extract the parameters listed in Table 1. Fill out
the first column in Table 1 with these parameters. Build test circuit OATC1 on your breadboard with the LM741
connected as the device under test (DUT). Apply the procedures outlined in the attached paper to measure the
parameters listed in Table 1. Fill out the second column of Table 1 with these measured values.

IV. Compare and Comment
(a) Compare the parameter values listed in Table 1. How close are the LM741 data sheet parameters to those from
actual measurements? How useful is the test circuit OATC1 for generating a data sheet for an op-amp?
(b) Comment on any major differences among the data in Table 1. Determine reasons for these differences.

V. References
1. V. Pua, H.T. Russell, Jr., W.A Davis, and R.L. Carter, A Comparison of Operational Amplifier Test Circuits, 9th
IEEE Emerging Technologies Conference (ETC 2006), Richardson, TX, September 15, 2006.
2. S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, 3rd Ed., The McGraw-Hill
Companies, Inc., New York, NY, 2002, (ISBN 0-07-232084-2).

VI. Attachments
1. H.T. Russell, Jr., OATC1: A Universal Test Circuit for Measuring Op-Amp Parameters, Department of EE,
UTA, November, 2009.

- 87 -

DUT
R
2
R
3
R
7
R
5
R
6
R
8
R
9
+5V +5V
-5V -5V
+V
psp
-V
psn
OP07 V
o2
V
id
R
4
R
1
V
ic
V
o
I
p
I
n
S
4
S
2
R
C
C
C
30K
100
100
100K
100K
2K
2K
2K
2K
51K
OP07
V
o1
U1 U2
OP07
U3
+5V
-5V
R
F3
2K
R
p
10K
V
id
or V
ic
(a)
(b)
300nF
1
2

Figure 1
Op-amp test circuit OATC1

Table 1
DUT parameters
(V
psp
/V
psn
= 10V, R
L
= 2K, T = 27C)
Parameter Description
LM741
Data sheet
OATC1 Units
V
os
Input offset voltage V
I
B
Input bias current A
I
BOS
Input bias offset current A
P
diss
Power dissipation W
CMRR Common-mode rejection ratio dB
PSRR
p
Positive power supply rejection ratio dB
PSRR
n
Negative power supply rejection ratio dB
G
vdm
(0) Open-loop dc differential-mode voltage gain V/V
G
vcm
(0) Open-loop dc common-mode voltage gain V/V


- 88 -

The University of Texas at Arlington
Department of Electrical Engineering

Dr. H.T. Russell, Jr. OPAL
tx

November 2009

OATC1: A Universal Test Circuit for
Measuring Op-Amp Parameters

The circuit shown in Figure 1(a) is the test circuit OATC1 for the measurement of a variety of operational
amplifier parameters. This circuit is an adaptation of the one shown on Intersil Corporations application note
AN551.1 entitled Recommended Test Procedures for Operational Amplifiers. You may download this note from
the company web site www.intersil.com. A similar circuit may be found in problem 5.27 on pages 246-247 of
Sergio Francos textbook
3
.

DUT
R
2
R
3
R
7
R
5
R
6
R
8
R
9
+5V +5V
-5V -5V
+V
psp
-V
psn
OP07 V
o2
V
id
R
4
R
1
V
ic
V
o
I
p
I
n
S
4
S
2
R
C
C
C
30K
100
100
100K
100K
2K
2K
2K
2K
51K
OP07
V
o1
U1 U2
OP07
U3
+5V
-5V
R
F3
2K
R
p
10K
V
id
or V
ic
(a)
(b)
300nF
1
2

Figure 1
(a) OATC1 op-amp test circuit
(b) dc voltage generator

The V
psp
and V
psn
dc voltage rails are nominal power supply voltages required to bias the device under test
(DUT) while V
id
and V
ic
represent differential-mode and common-mode input voltages to the DUT. These voltages
are obtained from the circuit shown in Figure 1(b) which generates a low-impedance dc voltage set by R
p
. Resistor
values shown on the schematic are typical with 1% tolerances and can be changed if necessary. Assuming that the
OP07s in this circuit are ideal op-amps, routine circuit analysis produces the following low-frequency, small-signal
expression for the output voltage V
o2
.

3
S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, 3
nd
Ed., The McGraw-Hill Companies, Inc., New York, NY,
2001.
- 89 -

V
R
R
R
R R
G V V
R
R
G V
R
R
G V R I R I
id vdm o ic vcm ic vdm os p p n n
=
F
H
G
I
K
J
+
F
H
G
I
K
J

F
H
G
I
K
J
+
F
H
G
I
K
J
+
6
5
3
3 7
2
6
5
6
5
b g d i
(1)

where


R R R
R R
R R
R R
p
n
= +
= +
+
1 2
4
3 7
3 7
(2)

These equations are used in the procedures that follow to measure a series of low-frequency op-amp parameters. In
these procedures, the indicated changes in V
id
and V
ic
are provided by the dc voltage generator with values.

1. Input offset voltage V
os

a. close switches S
2
and S
4
,
b. set V
ic
and V
id
to zero by connecting pins 1 and 2 to ground,
c. measure V
o2
with a dc voltmeter,
d. calculate V
os
from

V
R
R R
V
os o
=
+
F
H
G
I
K
J
3
3 7
2
(3)

2. Open-loop differential-mode voltage gain G
vdm

a. close switches S
2
and S
4
,
b. set V
ic
to zero by connecting pin 1 to ground,
c. connect the output of the signal generator to pin 2 for V
id
,
d. adjust R
p
to change the dc value of V
id
to get

V V V
id id id
= 1 2 a f a f (4)

e. measure the corresponding dc values of V
o2
to get

V V V
o o o 2 2 2
1 2 = a f a f (5)

f. calculate G
vdm
from

G
R
R
R
R
V
V
vdm
o
id
=
F
H
G
I
K
J
+
F
H
G
I
K
J
F
H
G
I
K
J
5
6
7
3
2
1
1

(6)

3. Common-mode rejection ratio CMRR
a. close switches S
2
and S
4
,
b. set V
id
to zero by connecting pin 2 to ground,
c. connect the output of the signal generator to pin 1 for V
ic
,
d. adjust R
p
to change the dc value of V
ic
to get

V V V
ic ic ic
= 1 2 a f a f (7)

e. measure the corresponding dc values of V
o2
to get

V V V
o o o 2 2 2
1 2 = a f a f (8)

- 90 -

f. calculate CMRR from
CMRR
R
R
V
V
o
ic
= +
F
H
G
I
K
J

F
H
G
I
K
J
1
1
1
7
3
2

(9)

4. Positive input terminal current I
p

a. open switch S
2
, close switch S
4
,
b. set V
ic
and V
id
to zero by connecting pins 1 and 2 to ground,
c. measure V
o2
with a dc voltmeter,
d. calculate I
p
from

I
R
R
R R
V V
p
p
o os
=
+
F
H
G
I
K
J
+
L
N
M
M
O
Q
P
P
1
3
3 7
2
(10)

5. Negative input terminal current I
n

a. close switch S
2
, open switch S
4
,
b. set V
ic
and V
id
to zero by connecting pins 1 and 2 to ground,
c. measure V
o2
with a dc voltmeter,
d. calculate I
n
from

I
R
R
R R
V V
n
n
o os
=
+
F
H
G
I
K
J
+
L
N
M
M
O
Q
P
P
1
3
3 7
2
(11)

6. Input bias current I
B
and input bias offset current I
BOS

a. calculate I
B
and I
BOS
from


I
I I
I I I
B
p n
BOS p n
=
+
=
2 (12)

Example. Four 741-type op-amps were tested with this circuit. Circuit values for the DUT are given below.


V V
V V
R K
CC
EE
=
=
=
5 06
5 05
51
7
.
.

(13)

Data for V
os

Unit V
o2
(V) V
os
(V)
7001 -0.294 575.3
7014A -0.238 465.7
2E23 -0.157 307.2
D34 -0.0634 124.1


- 91 -

Data for G
vdm

Unit V
id
(1) (V) V
o2
(1) (V) V
id
(2) (V) V
o2
(2) (V) G
vdm
(V/V)
7001 -1.012 -0.316 +1.023 -0.276 26.00K
7014 -1.001 -0.258 +1.069 -0.221 28.59K
2E23 -1.049 -0.1603 +1.038 -0.1599 2.67M
D34 -1.093 -0.0668 +1.096 -0.0666 5.59M

Data for CMRR
Unit V
ic
(1) (V) V
o2
(1) (V) V
ic
(2) (V) V
o2
(2) (V) CMRR
7001 -1.029 -1.294 +1.069 0.757 22.81K
7014 -1.075 -1.301 +1.069 0.819 45.65K
2E23 -1.016 -1.162 +1.044 0.878 52.63K
D34 -1.018 1.065 +1.048 0.974 39.10K






- 92 -

Appendix 1 Breadboard Layout Examples

EE 1105
Bread board layout techniques
September 13, 2008
HTR, Jr.

binding post
(red)
binding post
(black)
R
1
R
2
R
3
1K 200K
33K

Figure 1
Resistor network schematic


Figu re 2
Wrong way off the board with loops
- 93 -


Figure 3
Right way - low to the board and tight


Figure 4
Right way low to the board and even tighter


- 94 -

Breadboard layout examples
HTR, Jr.
February, 25, 2009






- 95 -









- 96 -

Appendix 2 Lab Measurement Example

Lab Measurement Example 1

A
B
1 4
3 2
R
1
R
2
R
3
R
4
R
5
R
6
V
ps
10K 3.3K
680 56K
56K 51K
10V

Figure 1
Network schematic


Figure 2
Breadboard layout


- 97 -

Table 1
Voltage, current, and power map





Element




Specified
value




Measured
value
Element voltage Element current




Element
power (W)
Nodes


Measured
value (V)
Nodes


Calculated
value (A)
+ +
R
1
10K 9.8251K
R
2
3.3K 3.2624K
R
3
680 684.22
R
4
51K 50.294K
R
5
56K 55.175K
R
6
56K 55.158K
V
ps
10V A B

Table 2
Kirchhoff current law
Node
Total current
into (I
in
) (A)
Total current
out of (I
out
) (A)
KCL
(I
in
I
out
) (A)
1
2
3
4
A
B


- 98 -

Table 3
Kirchhoff voltage law
Circuit
Total cw voltage
drop (V
cw
) (V)
Total ccw voltage
drop (V
ccw
) (V)
KVL
(V
cw
V
ccw
) (V)
V
ps
, R
1
,
R
5
, R
6


R
5
, R
2
, R
3
,
R
4


V
ps
, R
1
,
R
2
, R
3
, R
4
,
R
6




- 99 -

Lab Measurement Example 1

Solutions

A
B
1 4
3 2
R
1
R
2
R
3
R
4
R
5
R
6
V
ps
10K 3.3K
680 56K
56K 51K
10V

Figure 1
Network schematic


Figure 2
Breadboard layout

- 100 -

Table 1
Voltage, current, and power map





Element




Specified
value




Measured
value
Element voltage Element current




Element
power (W)
Nodes


Measured
value (V)
Nodes


Calculated
value (A)
+ +
R
1
10K 9.8251K A 1 1.09245 A 1 111.1897 121.4692
R
2
3.3K 3.2624K 1 4 0.18271 1 4 56.00478 10.23263
R
3
680 684.22 4 3 38.073m 4 3 55.64438 2.118549
R
4
51K 50.294K 3 2 2.8199 3 2 56.06832 158.1071
R
5
56K 55.175K 1 2 3.0406 1 2 55.10829 167.5623
R
6
56K 55.158K 2 B 6.1287 2 B 111.1117 680.9704
V
ps
10V 10.0147V A B 10.2831 A B -111.4 1.145537m

Table 2
Kirchhoff current law
Node
Total current
into (I
in
) (A)
Total current
out of (I
out
) (A)
KCL
(I
in
I
out
) (A)
1
(I
R1
)
111.1897
(I
R2
+ I
R5
)
111.1131
76.63n
(0.069%)
2
(I
R4
+ I
R5
)
111.1766
(I
R6
)
111.1117
64.91n
(0.058%)
3
(I
R3
)
55.64438
(I
R4
)
56.06832
423.9366n
(0.762%)
4
(I
R2
)
56.00478
(I
R3
)
55.64438
360.4n
(0.648%)
A 0
(I
R1
+ I
ps
)
210.3n
210.3n
(0.189%)
B
(I
ps
+ I
R6
)
-288.3n
0
288.3nA
(0.259%)


- 101 -

Table 3
Kirchhoff voltage law
Circuit
Total cw voltage
drop (V
cw
) (V)
Total ccw voltage
drop (V
ccw
) (V)
KVL
(V
cw
V
ccw
) (V)
V
ps
, R
1
, R
5
, R
6

(V
R1
+ V
R5
+ V
R6
)
10.26175
(V
ps
)
10.2831
21.35m
(0.208%)
R
5
, R
2
, R
3
, R
4

(V
R2
+ V
R3
+ V
R4
)
3.040683
(V
R5
)
3.0406
83
(0.0027%)
V
ps
, R
1
, R
2
, R
3
,
R
4
, R
6

(V
R1
+ V
R2
+ V
R3
+ V
R4
+ V
R6
)
10.26183
(Vps)
10.2831
21.267m
(0.207%)

A
B
1 4
3 2
R
1
R
2
R
3
R
4
R
5
R
6
V
ps
10K 3.3K
680 56K
56K 51K
10V

Figure 3
Oriented network schematic

Total power dissipated by resistors (delivered to resistors) = 1.14046mW
Total power delivered by the power supply = 1.145537mW
Absolute difference (%) = 5.076W (0.445%)


- 102 -

Appendix 3 Bills of Material

Lab 1
Bill of materials (BOM)

Diode measurement circuit
Diode: 1N4148

Resistors:
200 (1/2W) 2K 20K 200K 2M
330 (1/2W) 3.3K 33K 330K
820 (1/2W) 8.2K 82K 820K

NPN and PNP measurement circuits
Op-amp: OP-07
NPN: MPS8098
PNP: MPS8598

Capacitors: 220pF (2)

Resistors:
51 (1/2W) 82 (1/2W) 200 510 820
2K (2) 3K 5.1K 8.2K (2) 20K (2)
30K 51K 82K 200K (3) 300K
820K 2M




- 103 -

Lab 2
Bill of materials (BOM)

MOS measurement circuits
Op-amp: OP-07 (2)
n-ch: ALD1103/n-ch
p-ch: ALD1103/p-ch

Capacitors: 220pF (2)

Resistors:
68 (1/2 watt) 100 (1/2 watt) 200 270 680
2K 6.8K 20K 30K (2) 68K
120K 200K 10K trimpot



- 104 -

Lab 3
Bill of materials (BOM)

Op-amp: TLC274
NPN BJT: MPS8098 (4)
PNP BJT: MPS8598 (4)
Diode: 1N4148 (4)

Capacitors:
220pF 10uF

Resistors:
330 360 1K 7.5K 8.2K
9.1K 20K




- 105 -

Lab 4
Bill of materials (BOM)

NJFET: 2N3819 (2)
PJFET: J271 (2)

Resistors:
470 820 1.2K 5.1K 9.1K
10K 15K

Potentiometer (trim pot):
10K



- 106 -

Lab 5
Bill of materials (BOM)

Resistors:
160 330 (2) 620 10K

Transistors
NPN: MPS8098 (8) PNP: MPS8598 (8)
NJFET: 2N3819 PJFET: J271



- 107 -

Lab 6
Bill of materials (BOM)

BJTs:
NPN BJT: MPS8098
PNP BJT: MPS8598

Capacitors:
10uF (2) 50uF

Resistors:
200 470 620 1K 1.3K 1.6K
4.7K 10K 39K 270K 300K 680K
750K

Potentiometer:
1K trim pot


- 108 -

Lab 7
Bill of materials (BOM)

Transistors:
NPN BJT: MPS8098 (11)
PNP BJT: MPS8598 (9)
PJFET: J271

Capacitors:
120pF

Resistors:
270 (2) 390 (4) 560 1K (3) 3.3K (3)
5.1K (2) 8.2K 10K (5)


Lab 7 Bill of Materials
Part Description Count
PJFET
J271 p-channel junction field effect
transistor, plastic encapsulated
1
BJT
MPS8098 NPN bipolar junction
transistor, plastic encapsulated
11
BJT
MPS8598 PNP bipolar junction transistor,
plastic encapsulated
9
Resistor 270, 1/4W, 5%, carbon film resistor 2
Resistor 390, 1/4W, 5%, carbon film resistor 4
Resistor 560, 1/4W, 5%, carbon film resistor 1
Resistor 1K, 1/4W, 5%, carbon film resistor 3
Resistor 3.3K, 1/4W, 5%, carbon film resistor 3
Resistor 5.1K, 1/4W, 5%, carbon film resistor 2
Resistor 8.2K, 1/4W, 5%, carbon film resistor 1
Resistor 10K, 1/4W, 5%, carbon film resistor 5
Capacitor 120pF, NPO multilayer ceramic capacitor 1


- 109 -

Lab 8
Bill of materials (BOM)

Op-amp: OP-07 (3)

Capacitors: 300nF, NPO multilayer ceramic

Resistors:
100 (2) 2K (5) 30K 51K (3) 100K (2)

Potentiometer:
10K, trim-pot

Lab 8 Bill of Materials
Part Description Count
Op-amp OP07, 8-pin DIP 3
Resistor 100, 1/4W, 5%, carbon film resistor 2
Resistor 2K, 1/4W, 5%, carbon film resistor 5
Resistor 30K, 1/4W, 5%, carbon film resistor 1
Resistor 51K, 1/4W, 5%, carbon film resistor 1
Resistor 100K, 1/4W, 5%, carbon film resistor 2
Potentiometer 10K, trim-pot 1
Capacitor 300nF, NPO multilayer ceramic capacitor 1



- 110 -

Lab 9
Bill of materials (BOM)

Active devices:
OP-07 op-amp (3) LM741 DUT

Resistors:
100 (2) 2K (5) 30K
51K (3) 100K (2) 10K trimpot

Capacitors:
300nF, NPO multilayer