TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.

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TSMC Hierarchical
Design Flow
Diagram
TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0 2
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RC Correlation
(StarRCXT->Apollo->FE)
flattened prototyping (FE)
IR drop analysis (MarsRail)
hierarchical prototyping (FE)
Netlist, Timing Constraint, Size
top level trial route (APO)
floorplanning (FE)
Prototyping
RC Correlation(FE->PC)
block frame view and pdb
generation(APO)
block preCTSimplementation (PC):
placement, timing optimization
block timing model generation
top preCTSimplementation (PC):
placement, timing optimization
top/block implementation (APO):
CTS, track assign, SDF
RC Correlation
(APO->PC)
block/top post CTS
implementation (PC)
block/top detail route (APO):
double via, xtalk, antenna
fullchipSTA (PT, StarRCXT, NDC)
characterizing
timing-violated
blocks(PT)
budgeting (PT)
Hierarchical Timing Closure
full chip verification:
IR analysis (Voltage Storm)
DRC LVS (Calibre)
Formal Verification (Formality, Verplex)
xtalk (CeltIc)
Fullchip Verification
APO: Apollo
FE: First Encounter
NDC: Nautilus DC
PC: Physical Compiler
PT: PrimeTime
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RC Correlation
(StarRCXT->Apollo->FE)
flattened prototyping
(FE)
floorplanning (FE)
hierarchical prototyping (FE)
Netlist, Timing Constraint, Size
Prototyping
Hierarchical Timing Closure Fullchip Verification
original netlist
timing constraint (sdc)
timing library(.lib)
standard cell
library(.cdump)
technology file
initial floorplan
(I/O, critical macro
placement)
Amoeba Place
congestion OK?
design import
CTS
trial route
Extract RC
Timing Analysis
IPO
Is Timing Met?
no
yes
yes
no
t
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m
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g

r
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p
a
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l
o
o
p
c
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g
e
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n

r
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p
a
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r
l
o
o
p
trial route
save route
save place
saved initial
placement
saved initial
routing
createfences
(shaping, resizing)
specify partition
macro placement
refinement
Amoebaplace
power planning
trial route
feed-through buffer insertion,
refineplacement, trial route
savefloorplan
saveplacement
savenetlist
commit partition
top level route
Congestion OK?
floorplan file(.fp)
placement file(.place)
netlist(.v)
load placement, load routing
saved initial
placement and
routing
c
o
n
g
e
s
t
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n

r
e
p
a
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l
o
o
p
CTS
trial route
Extract RC
Timing Analysis
IPO
Is Timing Met?
yes
no
t
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m
i
n
g

r
e
p
a
i
r
l
o
o
p
no
yes
SavePartition
Partitioned netlist,
constraint,
floorplan
original netlist
timing constraint (sdc)
timing library(.lib)
standard cell
library(.cdump)
technology file
design import
IR drop analysis
(MarsRail)
top level trial route (APO)
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Prototyping
Hierarchical Timing Closure Fullchip Verification
1. partitioned netlist
2. partitioned timing
constraint
3. standard cell library
4. macro library
5. timing library
Design Import
Load Floorplan
AmoebaPlace
Partitioned Floorplan(.fp)
CTS
TrialRoute
congestion OK?
Extract RC
Timing Analysis
IPO
Is timing met?
modify top level
floorplan
Macro Placement
PT:Budgeting
RC Correlation
Extract RC
SPEF
Setload
Delay Calculation SDF
Save netlist
Save Placement
Netlist
PDEF
no
yes
no
yes
Create Stamp Model
Model Definition
Model Data
RC Correlation
(StarRCXT->Apollo->FE)
flattened prototyping (FE)
floorplanning (FE)
hierarchical prototyping
(FE) (Block Level)
Netlist, Timing Constraint, Size
IR drop analysis (MarsRail)
top level trial route (APO)
TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0 5
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Prototyping
Hierarchical Timing Closure Fullchip Verification
Stamp Models of
Each Partition
1.Macro Libraries of
Each Partition
(.cdump)
2.Top Level Netlist
3.Top Level Timing
Constraints
1. Standard Cell
Library
2. Timing Library
3. Technology file
Top Level
Floorplan
Design Import
Load Floorplan
AmoebaPlace
CTS
Trial Route
congestion OK?
Extract RC
Timing Analysis
IPO
Is timing met?
PT:Budgeting
RC Correlation
Extract RC
SPEF
Setload
Delay Calculation SDF
Save netlist
Save Partition
Netlist
no
yes
no
yes
Save IO File
(pin locations)
.tdf
RC Correlation
(StarRCXT->Apollo->FE)
flattened prototyping (FE)
floorplanning (FE)
hierarchical prototyping
(FE) (Top Level)
Netlist, Timing Constraint, Size
IR drop analysis (MarsRail)
top level trial route (APO)
TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0 6
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Hierarchical Timing Closure
Prototyping Fullchip Verification
RC Correlation(FE->PC)
block frame view and
pdbgeneration(APO)
block level preCTS
implementation (PC):
placement, timing optimization
block timing model extraction
top level preCTS
implementation (PC):
placement, timing optimization
top/block level
implementation (APO):
CTS, track assign, SDF
RC Correlation(APO->PC)
block/top post CTS
implementation (PC)
block/top detail route (APO):
double via, xtalk, antenna
fullchipSTA
(PT, StarRCXT, NDC)
characterizing
timing-violated
blocks (PT)
budgeting (PT)
PC
netlist
timing constraint
design import
write boundary
parasitics
PC
.SPEF
remove SDF
on boundary
1.boundary net
transition time
2.boundary
capacitance
load boundary
parasitics
extract timing model
PC
.SDF
PC
TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0 7
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Hierarchical Timing Closure
Prototyping Fullchip Verification
RC Correlation(FE->PC)
block frame view and
pdb generation(APO)
block level preCTS
implementation (PC):
placement, timing optimization
block timing model extraction
top level preCTS
implementation (PC):
placement, timing optimization
top/block level
implementation (APO):
CTS, track assign, SDF
RC Correlation(APO->PC)
block/top post CTS
implementation (PC)
block/top detail route (APO):
double via, xtalk, antenna
fullchipSTA
(PT, StarRCXT, NDC)
characterizing
timing-violated
blocks (PT)
budgeting (PT)
Create Lib (Ref =Std)
NetlistIn
load floorplan script
Make Macro
Create Timing Model
Load Timing
Constraint
Load Timing CLF
Dump LEF
(dumpLibLEF.scm)
.CLF
.CLF with clock
port capacitance,
clock port subtype,
port direction
lef2plib
.LEF
PLIB
Read PLIB
write PDB
PDB
FE
netlist(simplified)
floorplan script
tdf files
Timing constraints
(Clock information
only)
APO CTS
PC
metal_case.pl
TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0 8
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Hierarchical Timing Closure
Prototyping Fullchip Verification
RC Correlation(FE->PC)
block frame view and
pdbgeneration(APO)
block level preCTS
implementation (PC):
placement, timing optimization
block timing model extraction
top level preCTS
implementation (PC):
placement, timing optimization
top/block level
implementation (APO):
CTS, track assign, SDF
RC Correlation(APO->PC)
block/top post CTS
implementation (PC)
block/top detail route (APO):
double via, xtalk, antenna
fullchipSTA
(PT, StarRCXT, NDC)
characterizing
timing-violated
blocks (PT)
budgeting (PT)
NetlistIn
*_cts_fixed.pdef
PC
netlist
.pdef
Load floorplan script
Load power plan script
Load timing constraints
Read PDEF
(readPDEF3.scm)
Purge clock net/
default TranDelay
CTS
Report skew
Dump PDEF
(dumpPDEF3.scm)
Hierarchical Netlist Out
Write SDF/Setload
1.floorplanscript
2.power plan script
3.tdf
FE
FE
timing constraint
(clock information only)
*.hvout
*_cts_fixed.sdf
*_cts_fixed.dc
Define
Synchronous Pin
pdef_pc2apo.pl
pdef_apo2pc.pl
sdf_apo2pc.pl
dc_apo2pc.pl
Create Lib
(RefLib =Std)
Block level
Create Lib
(RefLib =Std cell,
generated pdblibrary)
Top level
CTS related files
metal_case.pl
PC
TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0 9
Confidential-Security C
Hierarchical Timing Closure
Prototyping Fullchip Verification
RC Correlation(FE->PC)
block frame view and
pdbgeneration(APO)
block level preCTS
implementation (PC):
placement, timing optimization
block timing model extraction
top level preCTS
implementation (PC):
placement, timing optimization
top/block level
implementation (APO):
CTS, track assign, SDF
RC Correlation(APO->PC)
block/top post CTS
implementation (PC)
block/top detail route (APO):
double via, xtalk, antenna
fullchipSTA
(PT, StarRCXT, NDC)
characterizing
timing-violated
blocks (PT)
budgeting (PT)
Create Lib
(RefLib =Std)
Create Lib
(RefLib =Std cell,
generated pdblibrary)
NetlistIn
Read PDEF
preRoute CTS
APO
CTS related files
generated after CTS
Route
Xtalk reduction route
Antenna-fixing route
PC
netlist
.pdef
Block level Top level
Define Synchronous Pin
(Top level only)
*_cts_fixed.pdef
Dump PDEF
(dumpPDEF3.scm)
Write SDF/Setload
*_cts_fixed.sdf
*_cts_fixed.dc
pdef_apo2pc.pl
sdf_apo2pc.pl
dc_apo2pc.pl
Write SPEF *_route.SPEF
Load floorplan script
Load power plan script
1.floorplanscript
2.power plan script
3.tdf
FE
metal_case.pl
PC
STA