Cadence Design System Tutorial I

Alex Yang
Northwestern Polytechnic University
Fremont CA
Copyright 2010, All Rights Reserved






Table of Contents


Step I: Design Environment Setup
Step 2: Build up circuit schematic
Step 3: Create your design
Step 4: Simulate your design
Step 5: Layout Design for R_div

Step 6: Extract the cell layout

Step 7: Extract R_div layout

Step 8: LVS


Step I: Design Environment Setup
1. Copy design kit NCSU-CDK-1.5.1.tar from
% cp /home/yangjh/NCSU-CDK-1.5.1.tar .

2. Untar file by
% tar xvf NCSU-CDK-1.5.1.tar
% tar zxvf ncsu-cdk-1.5.1.tar.gz
3. Set up environment
% vi .cshrc
Put the following lines in this file
setenv CDS_Netlisting_Mode Analog
setenv SPECTRE_DEFAULTS E
setenv CDS_LOAD_ENV CWDElseHome
setenv CDK_DIR $HOME/ncsu-cdk-1.5.1

4. % source .cshrc

5. %mkdir cdscad

6. %cp $HOME/ncsu-cdk-1.5.1/cdssetup/* $HOME/cdscad/

7. % cd cdscad

8. %mv cdsinit .cdsinit
% mv simrc .simrc
% mv cdsenv .cdsenv

9. % vi cds.lib
Check if the following lines exist
DEFINE basic $CDK_DIR/lib/basic
DEFINE NCSU_Analog_Parts $CDK_DIR/lib/NCSU_Analog_Parts
DEFINE NCSU_Digital_Parts $CDK_DIR/lib/NCSU_Digital_Parts
DEFINE MOSIS_Layout_Test $CDK_DIR/lib/MOSIS_Layout_Test
DEFINE NCSU_TechLib_ami06 $CDK_DIR/lib/NCSU_TechLib_ami06
DEFINE NCSU_TechLib_ami16 $CDK_DIR/lib/NCSU_TechLib_ami16
DEFINE NCSU_TechLib_hp06 $CDK_DIR/lib/NCSU_TechLib_hp06
DEFINE NCSU_TechLib_tsmc02 $CDK_DIR/lib/NCSU_TechLib_tsmc02
DEFINE NCSU_TechLib_tsmc02d $CDK_DIR/lib/NCSU_TechLib_tsmc02d
DEFINE NCSU_TechLib_tsmc03 $CDK_DIR/lib/NCSU_TechLib_tsmc03
DEFINE NCSU_TechLib_tsmc03d $CDK_DIR/lib/NCSU_TechLib_tsmc03d
DEFINE NCSU_TechLib_tsmc04_4M2P
$CDK_DIR/lib/NCSU_TechLib_tsmc04_4M2P

10. % cd $HOME/cdscad

11. %source /ee/setup/cadence/ic_setup.cmd

12. icfb &

Step 2: Build up circuit schematic
1. Generate a new library:
Give a name Tutorial_1_demo, for instance. Click OK.


2. Attach a techfile: Click OK

3. Select NCSU_TechLib_ami06.

Step 3: Create your design
1. Generate a new cell: select Cell Vhew

2. Give a new name, R_div, to the cell: Click OK

3. Instantiate components by Add -> Instance

4. Select NCSU_Analog_Parts library and click R_L_C

5. Choose res and give the value, such as 10K. Click Hide.

6. Put 2 resirTors on the Schematic EdIting panel.

7. Add the GND in Supply_Nets


8. Add input and output pins



9. Connect all components together by wire

10. Add wire name, in and out


11. Finish the circuit schematic. Then click Save

12. Create R_div symbol by From Cellview

Click OK

Delete all lines and boxes.

13. Finish the symbol drawing. Then save and quit

Step 4: Simulate your design
1. Generate a new cell sim_R_div by File -> new -> cell view

2. Create a simulation circuit by adding voltage source and divider
symbol



3. Finish the schematic. Click Save

4. Delete warning by Check -> Find Marker

Click ignore, and then save above schematic. Warning will disappear

5. Simulation environment setup by Tools -> Analog Environment


6. Setup -> Simulator/Directory/Host

Select spectre, click OK

7. Analysis setup by Analyses -> Choose

Select tran, type in 1 in Stop Time and Enabled. Click OK


8. Plot signals we want by Outputs -> To Be Plotted -> Select On
Schematic



9. Save simulation info by Session -> Save State

Select Cellview, click OK

10. Simulate by Simulation -> Netlist and Run

The waveform will be shown in the following windows.

Step 5: Layout Design for R_div

1. Create a new cell for layout by File -> New -> Cell View

Type in the following name and select proper options. Click OK



2. Layout display setup by Options -> Display

Selection the following options

3. Use the n-well layer (Rsh = 800 ohms) for the 10k resistor.

The minimum width of n-well is 12 lambda (3.6 microns since lambda here
is 300 nm) so lets make a 10k resistor using a width of 4.5 um and a length
56 um.
Select nwell in LSW window and Create -> rectangle. Draw
rectangle nwell resister with any size.


4. Highlight nwell and click Properties . Type in the following size,
click OK.
As calculated above we want a resistor that is 56 um long and 4.5 um wide.

Press key F to fit nwell into your window

5. Design rule check by Verify -> DRC

Click OK

Four errors were found.

6. Find the errors by Verify -> Markers -> Find

Select Zoom To Markers and then click Apply


Click Zoom in, you may find nwell edge is not on grid.

7. Fix the errors
Since the X and Y snapping is 0.15 microns in display setup, the length of the
resistor is 56 and 56/.15 = 373.3333. To make this a whole number, lets increase
the length to 56.1 (so we enter 28.05 in the Left/Right above). For the width we
used 4.5 and 4.5/.15 = 30 so we are okay there.

Design rule check, errors have been fixed.



8. Add the connections by Create -> Instance

Select the following cell by Browse

Adding these connections to the ends of the n-well resistor we get the
following.

9. Reset up display option by Option -> Display

Type in 10 in Stop box. Click OK

Highlight the 2 connections and move them by Stretch

10 Design rule check again to make sure no error

11. Add pins to the layout by Create -> Pin


Type in L in Terminal Names box

Select Hide and then draw a rectangle around the metal1 on the ntap
placing the Pin Name on the center of the metal1 rectangle.


Repeat, but use a Pin Name of R (right), for the other side.

12. Next select the layer res_id (to identify resistors). Select r to
draw a rectangle. Zoom in and start drawing a rectangle.


Step 6: Extract the cell layout

1. Verify -> Extract

Click OK


An extracted view is created in the R_n_well_10k cell group

2. Open this view. Zoom in to see the resistors value is 10.21k.



Step 7: Extract R_div layout

Close the extracted view. Save and close the layout view of the resistor.

1. Create layout cell of R_div



2. Instantiate two of the 10k n-well resistor layouts

DRC your layout to ensure the resistors are far enough apart.

3. Select the metal1 layer in the LSW to connect the resistors
together

The rectangles dont have to overlap the Pins, just touch (abut) the
metal1 Pins on the n-well resistors. (I like to overlap the Pins with
metal1.) One example is seen below. DRC the design to ensure no
errors.


4. Press key e and set the Stop Depth to zero results in
showing the outlines of the cells.


Press e again and set the Stop Depth back to 10.

5. Add Pins on the metal1 layer named in, out, and gnd. Set
the rectangle size of the Pin to the same size as the metal1
seen above.

6. DRC your layout. Extract your layout by Verify -> Extract.
Click OK



Step 8: LVS

1. Select Verify -> LVS


2. Set LVS cells name. Clikc Run

Click OK


Click OK



3. While the LVS succeeded to run this does not tell us if the layout
and schematic match! After pressing Output above LVS window
we get the following.

4. Find the error information because the net-lists failed to match.

Scrolling down in the above file shows the problems.


5. Fix the errors.

Relabel gnd in the layout gnd!
Our in pin should have characteristics of input (not input/output) and the out pin
should be an output (not input/output).






6. Extracting the layout again, and then running the LVS again we
get the following.



Congratulation!
This ends our first tutorial.
In this tutorial weve covered the fundamental operation of Cadence.
Mastering the topics before moving on to the other Tutorials is
important.