VLSI IMPLEMENTATION OF NONLINEAR VARIABLE CUTOFF HIGH PASS

FILTER ALGORITHM

KalaiPriya.O
1
, S.Ramasamy
2
, D.Ebenezer
3
Department of electronics and communicaton,
R.M.K.Engineering College, Kavaraipettai,
Thiruvallur District, Tamilnadu, India.
Kalaiomprakash@gmail.com, srs.ece@rmkec.ac.in, der.ece@rmkec.ac.in


Abstract The focus of this paper is the actual
implementation of the algorithm onto FPGA hardware. A
simple nonlinear median based high pass filter algorithm has
been implemented using Xilinx ISE 12.2 targeted for FPGA
xc6slx4-3tqg144. The filter structure consists of a median filter
followed by a high pass filter. The signal to be filtered is the
input to median filter and its output becomes the input to high
pass filter. The high pass filter algorithm identifies and
separates the high frequency components by sliding a time
ordered window of size-3 over the median filters output
samples. This high pass filter preserves the details of filtered
low frequency components for reconstruction and not lost as
in the case of conventional high pass filter. The hardware
performance is studied using Spartan 6.

Keywords Median filter, High pass filter, Impulsive
noise, FPGA
I. INTRODUCTION
It is often desirable to be able to perform some kind of
noise reduction on an image or signal. The median filter is a
nonlinear digital filtering technique, often used to remove
noise. Such noise reduction is a typical pre-processing step
to improve the results of later processing (for example, edge
detection on an image). Median filtering is very widely used
in digital image processing because under certain conditions,
it preserves edges while removing noise. Median smother
has been shown to be an effective alternative to linear
smoother for filtering signals having wide spectrum
(homogenous regions to sharp edges in time domain).
Median filters are successfully employed in many areas of
digital signal processing, including speech processing where
impulsive type of noise had long been a problem and in
image processing where edge preservation is essential.
The block diagram of the filter is shown in Fig.3.1.

High Frequency
Input, x[i] Median output
output
Difference
Output

Figure 1. Median High Pass Filter
The filter [1] has two outputs, namely, high frequency
output and difference output. The high pass filter algorithm
accepts the median filter output m[i] as its input. It separates
the high frequency components and low frequency
components (defined as difference components or low
frequency details in this paper). High frequency components
are passed on to the high frequency output of the filter. The
low frequency components are differenced (process of
finding algebraic difference in amplitudes) and the result is
available at the difference output preserves the details of low
frequency components. Since the details of the filtered low
frequency components are preserved and not eliminated as
in the case of conventional high pass filter, it is possible to
reconstruct the median filter output with a reconstruction
algorithm. The high pass filter algorithm is simulated using
Xilinx tools to be implemented on FPGA.
II. MEDIAN HIGH PASS FILTER
The high pass filter[1] consists of 2 stages as shown in
Fig.1. Input samples stored in an array x[i] are passed
through a median filter with a desired window size. Median
filtering is a discrete time process in which a 2N+1 points
wide window is slided across the input signal. At each step,
the points inside the window are sorted and the middle or
median value is used as the filter output associated with the
sample at the centre of the window.
The output of median filter m[i] is the input to the high
pass filter algorithm. A time ordered window of size-3 is
slided over the median filter output by the high pass filter
algorithm to separate the high frequency and low frequency
components. The samples inside the window to reach the
front and rear ends of the median filter output, a sample with
zero value are appended to the front and rear end. The
separation of high frequency and low frequency is done by
the high pass filter algorithm.
When the amplitude difference between the centre
sample and anyone of its two neighbouring samples exceeds
or equals a value called threshold (defined by the user) the
centre sample becomes the high frequency component. In
other words, the centre sample q is a high frequency
component if |q-p| >= threshold OR |r-q | >= threshold. As
the window slides over the median filter output samples, the
samples which satisfy the condition for high frequency
components are passed on to high frequency component
Median
Filter
High Pass
Filter
Algorithm
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978-1-4244-8679-3/11/$26.00 2011 IEEE
output and stored in an array h[i]. The samples which do not
satisfy the condition for high frequency components are low
frequency components. When the centre sample is a low
frequency component, the algebraic difference between the
centre sample and the first sample i.e. (q-p) is computed,
passed on to the difference output and stored in an array d[i].
The pseudo code description of the segment of algorithm
which does this task is given below:

for (i=0 to (ns-1)) /* ns is the no. of input
samples */
{
P m[i] /* for the given value of
index index i,
3 samples are
Q m [i+1] picked out from the
median filter
output m[i] and
r m [i+2] placed inside the
window */


if ( | q-p| >= threshold OR | r-q | >= threshold )
{
h[i] q
d[i] 0
}
Else
{
h[i] ( q-p )
}
}
III. STRUCTURE OF HIGH PASS FILTER ALGORITHM
Input stage is basically a shift register which generates
the successive window elements from incoming sample
stream (medians). At every clock pulse, it reads one sample
value from the median output and discards the sample value
read 3 cycles earlier and thus slides the window over the
incoming sample stream. Initially, the shift register is reset
to zero. The block arithmetic operations as directed by the
high pass filter algorithm. There are 2 units within the block.
The first unit consists of 2 subtractors one to find ( q-p )
and other to find (r-p). Absolute values of (q-p) and (r-q) are
passed on to the second unit. There are 2 comparators in the
second unit one to compare | q-p | and the other to compare
| r-q| with the threshold input. The outputs of the
comparators indicate whether the centre sample q is a high
frequency component or low frequency component. If it is a
high frequency component, the centre sample stored in the
input shift register is passed on to the high frequency output.
Otherwise, the algebraic difference (q-p) stored in the
subtractor unit is sent to the difference output. Either the
high frequency output or difference output is obtained for
every clock pulse. The high level structure is shown in Fig 2.


Figure 2. High Level Structure
IV. FPGA DESIGN OPTIONS
Prior to a full hardware realization of the algorithms [1],
some initial non - algorithm work was necessary. This work
included an overall VHDL/Verilog hierarchy concept, the
development of a moving window unit for image data, a
VHDL test bench for testing purposes, MATLAB interfaces
for file input/output through HDL file handling techniques,
and an analysis of the project data.
The median filter is developed using VHDL and
synthesized for the FPGAs. A 3x3 window size was chosen
because it is considered large enough to be effective for
most commonly used image sizes. With larger window
sizes, more FIFOs and flip -flops must be used, which
increases the FPGA resources used significantly. Similarly
the high pass filter algorithm is modelled using verilog
behavioural and then the final structure is synthesized and
simulated.
Simulation takes the HDL code and simulates how it
would work in hardware. A test bench for an algorithm is
responsible in stimulating essential input signals to that
algorithm. The designs used in this algorithm [1] are all
synchronous and so a clock signal must be stimulated. Since
the algorithm used takes input images and produce some
kind of output image, some method of data input and output
must be provided for functional simulation. To process
images with a HDL algorithm, a test bench is created first
that can read in the file containing this data. To view the
processed image, another feature must be included into the
test bench to allow file writing. These are the key features
to show how test benches are used in this work. Then the
output pixel values are paired with a program such as
MATLAB, which provides efficient image representation
and viewing capabilities.

A m-file is created to take an input file in the bitmap
format and convert it to a file containing the image pixel
values. Data in this format could then be read into the HDL
test bench by using standard HDL file handling functions.
After this data has been run through the simulator , the
output data of the algorithm is written by the test bench into
another file formatted in the same way. Then another m-file
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is coded to read that data and convert it back into a matrix in
MATLAB. This allows analysis and comparison of HDL
processed images with MATLAB processed images. This
analysis allows to verify hardware algorithm accuracy, for
determining proper functionality of the algorithms and is
also useful in determining whether hardware design
compromises to produce valid results. The memory is
faclitated by means of data2mem gen tool in Xilinx.

V. RESULTS
The filter structure [1] consists of 2 stages: first stage
being a median filter and the second stage being a high pass
filter algorithm. The output of the first stage serves as input
to the second stage. That is, the output of median filter is the
input to the high pass filter algorithm. A lena image is taken
as an input image from standard web sources and using
MATLAB 90% noise is added to it. Figure 3(a) shows
original image. Figure 3(b) shows 90% noisy input image.


(a) (b)
Figure 3. (a) Original image (b) Noisy image

The median filter output image obtained after simulation
is shown in figure 4.



Figure 4. Median filter image after simulation

The data used consisted of 8 bit grayscale image data of
size 256 by 256. For any real-time image processing system,
the data size used greatly affects the projects hardware
performance, as well as the number of resources used on that
hardware. Figure 5 shows median filter simulation report.




Figure 5. Median filtering simulation report

The high pass filter algorithm structure consists of
subtractor, D-flip flop and comparator modules. The
structure is split into the above said sub modules and coded
using verilog in behavioural modelling and these sub
modules are integrated together to form the high pass filter
structure. Then the median output is passed on to the high
pass filter algorithm to obtain the results of complete high
pass filter structure. They are simulated using Xilinx version
12.2. Figure 6 shows the simulation results of high pass filter



Figure 6. High pass filter simulation report


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This output is then passed onto the Spartan Board to
study the hardware performance. The hardware resources for
implementing the high pass filter are listed as below.

TABLE I. HARDWARE RESOURCES UTILISED

Logic Resources Used/Available

Flip Flops

758

LUT-FFs Pairs

420/751

Slice LUTs

676/2400

Critical path delay of 8.54nS is reported from timing
simulation indicating the high pass filter is capable of
operating at 90.9 MHz. The performance metrics are to be
calculated to prove better performance.

V. CONCLUSIONS
The filter structure consists of a median filter followed
by a high pass filter. The signal to be filtered is the input to
median filter and its output becomes the input to high pass
filter. A time ordered window of size-3 is slided over the
medians output samples. They are modelled using HDL
language and simulated using Xilinx version 12.2 and
downloaded into Spartan 6 kit. The output image has been
observed and compared with the original image.
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