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Code No: A109211002 R09 Set No. 2
II B.Tech I Semester Examinations,December 2011
SWITCHING THEORY AND LOGIC DESIGN
Common to Instrumentation And Control Engineering, Electronics And
Computer Engineering, Electronics And Instrumentation Engineering
Time: 3 hours Max Marks: 75
Answer any FIVE Questions
All Questions carry equal marks

1. (a) Write short notes on Unused states and Dont care conditions.
(b) Design a synchronous Decade counter. [8+7]
2. (a) State the purpose of reducing the switching functions to minimal form
(b) Write the Dual of
i. (A+BC

+AB)
ii. (AB+B

C+CD)
(c) Give the truth table for the Boolean expression (X

+Y)

[4+7+4]
3. Determine the canonical Product of sum form for the function and simplify using
k-map
(a) Y(x,y,z) = x(y

+z)
(b) Y(a,b,c) = ab

+ bc
(c) Y(w,x,y,z) = wxy

+x(y

+z)
(d) Y(a,b,c) = (ab+c

)(ac+b

) [15]
4. (a) Dene logic circuits. Dierentiate Combinational logic circuits and synchronous
logic circuits.
(b) Design a 2 to 4 decoder. Draw the circuit diagram, function table, symbol.
[8+7]
5. (a) Give a brief description about the following number systems with suitable
examples.
i. Decimal number system
ii. Binary number system
iii. Octal number system
iv. Hexadecimal system
(b) i. Convert (2598.675)
10
to hexadecimal
ii. Convert (10010.1011)
2
to decimal
iii. Convert (10111101.01101001)
2
to octal
iv. Convert (465.0647)
8
to Binary
[8+7]
1
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Code No: A109211002 R09 Set No. 2
6. Minimize the following incompletely specied machine using Merger Graph method.
[15]
PS NS,Z
I1 I2 I3 I4
A - C,1 E,1 B,1
B E,0 - - -
C F,0 F,1 - -
D - - B,1 -
E - F,0 A,0 D,1
F C,0 - B,0 C,1
7. Design the ASM chart, Data path circuit, Control circuit using multiplexers for
Binary multiplier. [15]
8. Given the switching function
F(w,x,y,z) = m (2,3,6,7,10,12,14,15). Find a minimal threshold-logic realization.
[15]

2
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Code No: A109211002 R09 Set No. 4
II B.Tech I Semester Examinations,December 2011
SWITCHING THEORY AND LOGIC DESIGN
Common to Instrumentation And Control Engineering, Electronics And
Computer Engineering, Electronics And Instrumentation Engineering
Time: 3 hours Max Marks: 75
Answer any FIVE Questions
All Questions carry equal marks

1. (a) What is meant by Lock out condition? What are the basic precautions that
are to be taken to avoid this lockout condition?
(b) Design a Modulo 6 counter, where the 6
th
and 7
th
states are considered as
dont care conditions. If the counter goes to any of these states what are the
methods to be followed in the design to avoid Lock out condition. [8+7]
2. Design a combinational circuit whose input is a 3 input binary number and whose
output is a 2s complement of the input number. [15]
3. Design a combinational logic circuit which is dened by the functions
F1 = a

d + a

+ ab

cd

F2 = a

c + b

cde

+ a

bcde

F3 = abcd

+ ab

cd

+ abcde

[15]
4. Construct the compatibility graph and obtain the minimal cover table for the in-
completely specied sequential machine specied in the state table given below.
[15]
PS NS,Z
J1 J2
A E,1 B,1
B F,1 A,1
C E,- C,1
D F,0 D,1
E C,0 C,1
F D,- B,1
5. What are Error detecting codes? What is the meaning of party checking? Construct
the even parity code and odd parity code. [15]
6. Simplify the Boolean expression using Boolean postulates
(a) AB

C + B + BD

+ ABD

+ A

C
(b) (AB

(A+C))

+ A

B(A+B

+C)

(c) (AB)

(B + C)
(d) (((AB)

C)

(B

C)

[15]
3
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Code No: A109211002 R09 Set No. 4
7. Design a synchronous sequential circuit which can add 3 binary digits and produce
a sum bit and an output carry. Design the ASM chart to implement the above
mentioned design. Design the control unit using PLA control. [15]
8. Design a circuit which can be used to add and subtract two 4 bit binary numbers.
Explain the procedure of the design. [15]

4
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Code No: A109211002 R09 Set No. 1
II B.Tech I Semester Examinations,December 2011
SWITCHING THEORY AND LOGIC DESIGN
Common to Instrumentation And Control Engineering, Electronics And
Computer Engineering, Electronics And Instrumentation Engineering
Time: 3 hours Max Marks: 75
Answer any FIVE Questions
All Questions carry equal marks

1. (a) Design a Serial binary adder.
(b) What is race around condition? How can we avoid race around problem?
[8+7]
2. (a) Draw an ASM chart to convert D-Flip op to T ip op.
(b) Give the procedure to design a data processing unit and a control unit [8+7]
3. (a) Design a combinational logic circuit using a decoder which acts as a code
converter to convert a Hexa decimal number to a Decimal number.
(b) Explain the disadvantages of an Encoder. Discuss the procedure to over come
the disadvantage of the Encoder. [8+7]
4. (a) Prove the following identity
XY + X

+YZ = XY +X

+X

Z
(b) Dene Switching functions. Consider a 3 variable switching function and
create a Truth table for all possible values of the input.
(c) Consider 2 functions, f = x

y +xyz

& g = xy

+ xz. For all possible values of

x,y,z create a truth table for the outputs f, g, f+g and f

. [4+4+7]
5. (a) Solve for X
i. (F3A7C2)
16
= (X)
10
ii. (2AC5)
16
= (10949)
X
iii. (0.93)
10
= (X)
8
iv. (4057.06)
8
= (X)
10
(b) The message given below has been coded in the Hamming code and transmit-
ted through a noisy channel. Decode the message assuming that at most a
single error has occurred in each code word of 8 bits.
1 0 0 1 0 0 1 0 1 1 1 0 0 1 1 1 1 0 1 1 0 0 0 1 1 0 1 1 [8+7]
6. Consider the machine whose state table is given below.
5
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Code No: A109211002 R09 Set No. 1
PS NS,Z
X = 0 X = 1
A E,0 D,1
B F,0 D,0
C E,0 B,1
D F,0 B,0
E C,0 F,1
F B,0 C,0
Explain the state equivalence determination. When the 2 states are distinguishable
and when the states are equivalent. [15]
7. Design a combinational logic circuit that has 3 inputs. The output is required to
go HIGH whenever the number of inputs have even number of 1s. Draw the Truth
table. Minimize the Boolean function using K-map. Draw the circuit diagram.
[15]
8. Design a combinational logic circuit which performs the Binary multiplication that
multiplies two 4-bit numbers. Use ROM to implement this design. [15]

6
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Code No: A109211002 R09 Set No. 3
II B.Tech I Semester Examinations,December 2011
SWITCHING THEORY AND LOGIC DESIGN
Common to Instrumentation And Control Engineering, Electronics And
Computer Engineering, Electronics And Instrumentation Engineering
Time: 3 hours Max Marks: 75
Answer any FIVE Questions
All Questions carry equal marks

1. (a) Dierentiate Characteristic table and Excitation table.
(b) Design a BCD counter using T Flipops. [8+7]
2. (a) Draw an ASM chart to implement the function of a SR ip op.
(b) Dierentiate Conventional ow chart and Algorithmic state machine chart.
[8+7]
3. (a) Design a combinational logic circuit using ROM. The circuit accepts BCD
number and generates an output binary number equal to the 2s complement
of the input number.
(b) Explain advantages of Mask programming. Give the Hardware procedure for
PROMs and EPROMs. [8+7]
4. (a) Explain the complement representation of negative numbers with examples
(b) Obtain the 1s complement and 2s complement of the binary numbers
i. 1010111
ii. 0111001
iii. 1001
iv. 00010 [4+11]
5. (a) State and explain with examples the state equivalence and distinguishable
theorems.
(b) Give the procedure to nd the compatibility graph and minimal cover table.
[8+7]
6. Use a Karnaugh map to simplify the logic expression F = A(BC + BC) + ABC.
Determine the Prime implicants and essential prime implicants. Check the result
using Boolean algebra. [15]
7. (a) Write short notes on Universal gates
(b) Implement Y = AB

+CD + (A

B+C

) using NAND gates

(c) Verify the following Boolean algebraic expression. Justify each step with a
reference to a theorem or postulate.
(AB +C +D) (C

+D) (C

+D +E) = ABC

+ D [4+4+7]
8. (a) Realize the full subtractor using decoder and other required logic gates.
7
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Code No: A109211002 R09 Set No. 3
(b) With the help of two 16 to 1 multiplexers, design a 32 to 1 multiplexer. [8+7]

8
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