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Analogue amplification is used to achieve necessary voltage and power gain, when a certain
input of a system is too small to be fed to one of the subsystems [1]. The motive of using
two stages is to get voltage amplification from input stage and then buffer that stage’s output
in the output stage making the final output impedance low while keeping the voltage gain to
required level. For acquiring such criteria using Bipolar Junction Transistors (BJT), common
emitter circuit configuration as the input stage (to get voltage gain with high output
impedance) and then emitter follower circuit configuration (to get a gain ≤ 1 with low output
impedance) can be used. This particular lab exercise was focused on designing and building
similar two stage analogue amplifier according to the given specification.
The lab instruction contained specific design criteria and circuit configuration.
3. Theoretical analysis:
Vo1
In such configuration, R1 and R2 works as a potential divider making the base voltage
(VB) constant. This causes a current iB to flow making the voltage VB = VBE + IE
(Re1+Re2). As VBE is constant and VB is made constant, it is apparent from the
equation that the transistor becomes stabilized in terms of I E and accordingly the
voltage drop across Re1+Re2. Thus the configuration sets the transistor to be in active
region irrespective to the value of β. [3]
Along with this, the transistor provides a voltage gain making the output voltage to be
Vo1 with high output impedance.
Assumptions made:
Any capacitors behave like open circuit.
No AC sources are present in the circuit.
IB
IE
IB
IE
Here,
R1 R2
Rth = R1 || R2 = (Equivalent resistance between Base and GND)
R1 + R2
R2
Vth = Vcc (Voltage drop across R2)
R1 + R2
Vth – VB
IB = - II
Rth
From II;
VB = Vth - IBRth
Therefore;
So,
Vth - VBE
IB =
Rth + (1+β) RE
We know;
IC = β IB
β (Vth - VBE)
=
Rth + (1+β) RE
(Vth - VBE)
= (Assuming, Rth<< (1+β) RE and (1+β) RE ≈ β RE)
RE
Assumptions made:
Any capacitors behave like closed circuit.
All DC sources are grounded.
RS is small making the voltage drop across it infinitesimal, i.e.;
negligible.
ib rπ
ie
Now,
ib = vbe / rπ
ie = ib + gmvbe
ve = ieRe2
Now;
Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09
vs = vb
Therefore;
vs = vbe + ve
= vbe [1 + Re2 (gπ + gm)]
vo1 = - gmvbeRc
Therefore;
To measure the input impedance, the impedance at base was measured first.
After that the total impedance was calculated from the input. [4]
ib
C
rπ gmvbe
Zb1
Zin
Now,
ib = vbe / rπ
Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09
Therefore,
Therefore;
The total input impedance;
Zin1 = R1 || R2 || Zb1
To find the output impedance, the output nodes C and D were observed.
Thévenin theorem was applied to find the equivalent resistance, i.e.; output
impedance of the circuit (figure 6).
Here,
Therefore;
vo1
In such configuration, the output is taken from the emitter and there is no collector
resistance. Thus it works as a buffer presenting a gain < 1 with low output
impedance.
Assumptions made:
Any capacitors behave like open circuit.
No AC sources are present in the circuit.
IB
1
1
VB
VE
IE
Here,
R3 R4
Rth1 = R3 || R4 = (Equivalent resistance between Base and GND)
R3 + R4
Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09
R4
Vth1 = Vcc (Voltage drop across R2)
R3 + R4
Vth1 – VB
IB = - II
Rth1
From II;
VB = Vth1 - IBRth1
Therefore;
So,
Vth1 - VBE
IB =
Rth1 + (1+β) Re
We know;
IC = β IB
β (Vth1 - VBE)
=
Rth1 + (1+β) Re
(Vth1 - VBE)
= (Assuming, Rth1<< (1+β) Re and (1+β) Re ≈ β Re)
Re
Assumptions made:
Any capacitors behave like closed circuit.
All DC sources are grounded.
RS is small making the voltage drop across it infinitesimal, i.e.;
negligible.
The assumptions result in the following circuit:
gmvbe
ib
rπ
ie
Here,
ib = vbe / rπ
ie = ib + gmvbe
ve = ieRe
= vbe Re (gπ+gm) = vo
vo1 = vbe + ve
Av2 = vo / vo1
Re (gπ+gm)
= ≈1 (Since, Re (gπ+gm) >> 1)
1 + Re (gπ+gm)
This derivation shows that the circuit configuration of this stage is working
like a buffer.
vb gmvbe
rπ
ib
Zin
Zb2
ve
ie
Here,
ib = vbe / rπ
Therefore,
Therefore;
The total input impedance;
Zin2 = R3 || R4 || Zb2
Assumptions made:
Source for this stage vo1 = 0.
Source resistance (output impedance of first stage) was counted.
The dependent current source’s (gmvbe) resistance = 1 / gm
Zout
Therefore;
The overall gain can be calculated by multiplying the gain of both stages. Along with
that another factor called loading effect should be accounted for, as it tends to reduce
the overall gain. [5] The loading effect in this scenario was,
Zin2
Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09
Zin2 + Zout1
Therefore;
Zin2
Overall gain, Av(total) = Av1 Av2
Zin2 + Zout1
VAC
(peak) IB (uA)
Cut-Off region
VCE VCC
VBE
Figure 13: Ic and VCE consideration for active mode of operation from I-V
characteristics of BJT
The value of VCE must be greater than VBE in order to keep the BJT in active
region. Since, an AC signal is expected as output, the maximum peak of that
signal should also be considered i.e.; the output always stays in active region.
VC VCE VE
VCC = 10
Now,
Now,
Again,
Estimated values;
RC = 3.3 kΩ
Re2 = .56 kΩ
Re1 = .1 kΩ
Therefore;
AV1 = 5.9 ≥ 5
Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09
Now,
Ic = 1.8 mA
Therefore;
IB = Ic / β = 1.8 m / 200 = 9 uA
Hence;
gm = Ic / (kT / q) = (1.8/25m) mS = 72 mS
Vth - VBE
IB =
β RE
Therefore;
Vth = β RE IB + VBE
= 1.89 V
R2
Vth = Vcc
R1 + R2
Therefore;
R1 / R2 = (Vcc / Vth) – 1
= 4.29
Estimated values:
R1 = 390 kΩ
R2 = 100 kΩ
Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09
VCE VE
VCC = 10
VCE = 10 – IE Re
Now,
Now,
VBE + VAC(peak-maximum) = 10 - IC Re -I
Ic = 1.8 mA
Therefore;
IB = Ic / β = 1.8 m / 200 = 9 uA
Hence;
gm = Ic / (kT / q) = (1.8/25m) mS = 72 mS
Re (gπ+gm)
Av2 = = 0.99 ≈ 1
1 + Re (gπ+gm)
Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09
Vth1 - VBE
IB =
β Re
Therefore;
Vth1 = β Re IB + VBE
= 7.72 V
Again from previous calculation:
R4
Vth = Vcc
R3 + R4
Therefore;
R4 / R3 = 1 / [(Vcc / Vth) – 1]
= 3.3
Estimated values:
R4 = 330 kΩ
R3 = 100 kΩ
Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09
vSp-p = 0.2 V
Therefore;
Gain = 1 / 0.2 = 5
Zin1 = R1 || R2 || Zb1
= R1 || R2 || rπ + (β+1) Re2
Zout1 = RC = 3.3 k Ω
It is apparent that Zout1 is slightly out of range. This was because, lower
value of Re2 was making Zin1 to go below the required range and for that
Re2 had to be increased and the increase in RC followed the previous
increase to maintain the gain.
Vo1p-p = 1 V
Therefore;
Zin2 = R3 || R4 || Zb1
= R3 || R4 || rπ + (β+1) Re
Zout2 = RC = 3.3 k Ω
Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09
4.3.3 Multistage:
5. Reference:
1. http://www.electronicsinschools.org/page.php?ps=92&p=348
2. Lab notes, D3, University of Southampton
3. ELEC1005 Analogue electronics notes, University of Southampton
4. http://209.85.229.132/search?q=cache:xbtJOMSsnJcJ:notes.ump.edu.my/fkee/BE
E2213_Farizan/6.%2520BJT%2520small%2520signal.ppt+loading+effect+bjt&cd=7&
hl=en&ct=clnk
5. http://en.wikipedia.org/wiki/Loading_effect#Loading_effect
6. Mr. Tim Forcer, University of Southampton