SOLUTION FOR PROBLEMS IN CHAPTER 9 : MSI LOGIC CIRCUITS

9-1 : Refer to Figure 9-3 Determine the levels at each decoder output for the following sets of input
conditions :
a. Input : All LOW output : All HIGH
b. Input : LOW except E3= HIGH output : O3=LOW
c. Input : All inputs HIGH except E1=E2=LOW Output : All HIGH
d. Input : All HIGH Output : All LOW
9-3 : For a 74LS138, what input conditions will produce the following outputs :
a. Output : LOW at O6 Input : E3E2E1 = 100, [A]=110 (MSB)
b. Output : LOW at O3 Input : E3E2E1 = 100, [A]=011 (MSB)
c. Output : LOW at O5 Input : E3E2E1 = 100, [A]=101 (MSB)
d. Output : LOW at O0 and O7, simultaneously Input : E3E2E1 = 100, [A]= 111 (MSB)
9-4 : Show how to use 74LS138s to form a 1-of-16 decoder :


Inputs A, B, C are used to select which output on either decoder will be at logic 1 (HIGH) and input Dis used
with the enable input to select which encoder either the first or second will output the 1.
However, there is a limit to the number of inputs that can be used for one particular decoder, because
as n increases, the number of AND gates required to produce an output also becomes larger resulting in the fan-
out of the gates used to drive them becoming large.
This type of active-HIGH decoder can be implemented using just Inverters, ( NOT Gates ) and AND gates. It
is convenient to use an AND gate as the basic decoding element for the output because it produces a HIGH or
logic 1 output only when all of its inputs are logic 1.
But some binary decoders are constructed using NAND gates instead of AND gates for their decoded output,
since NAND gates are cheaper to produce than ANDs as they require fewer transistors to implement within
their design.
The use of NAND gates as the decoding element, results in an active-LOW output while the rest will be
HIGH. As a NAND gate produces the AND operation with an inverted output, the NAND decoder looks like
this with its inverted truth table.
9.5: Figure 9-70 shows how a decoder can be used in the generation of control signals . Assume that s
RESET pulse has occurred at time t0, and determine the CONTROL waveform for 32 clock pulses :




9.8 : Consider the waveform in Figure 9-72 . Apply these signals to the 74LS138 as follow :
AA0, BA1, CA2, DE3
9-13 : Drill question : For each item, indicate whether it is referring to a decoder or an encoder :
(a),(b): Decoder ; (c),(d),(e) : Encoder
9-15: Apply the signals of Figure 9-72 to the inputs of a 74147 as follows : AA7, BA4, CA2,
DA1 :
9-16:
9-24:
9-25:
9-27:
9-29:
9-31:
9-35:
9-36:
9-37:
9-38:
9-39:
9-41:
9-43:
9-44:
9-56:
9-57:
9-58
9-62: