Digital Logic Design

CS-302
3-0-0 : 3 Credit
Switching Circuits: Logic families: TTL, nMOS, CMOS, dynamic CMOS and pass transistor logic
(PTL) circuits, inverters and other logic gates, area, poer and delay characteristics, concepts of fan!in,
fan!out and noise margin"
Switching theory: #oolean alge$ra, logic gates, and sitching functions, truth ta$les and
sitching e%pressions, minimi&ation of completely and incompletely specified sitching functions,
'arnaugh map and (uine!McClus)ey method, multiple output minimi&ation, representation and
manipulation of functions using #**s, to!level and multi!level logic circuit synthesis"
Combinational logic circuits: +eali&ation of #oolean functions using ,-,*.,O+ gates,
*ecoders, multiple%ers" logic design using +OMs, PL-s and /P0-s" Case studies"
Sequential circuits: Cloc)s, flip!flops, latches, counters and shift registers, finite!state machine
model, synthesis of synchronous se1uential circuits, minimi&ation and state assignment,
asynchronous se1uential circuit synthesis"
ASM charts: +epresentation of se1uential circuits using -SM charts, synthesis of output and
ne%t state functions, data path control path partition!$ased design"
Syllabus
Book:
# Digital Design- Moris Mano & Michael D Ciletti
# Digital Electronics William leit!
References
1. H. Taub and D. Schilling, Digital Integrated lectr!nics, "c#ra$-Hill .
%. &. '!ha(i, S$itching and )inite *ut!+ata The!ry, Tata "c#ra$-Hill.
3. Randy H. 'at, and #aetan! -!rriell!, C!nte+.!rary /!gic Design, 0rentice Hall !f India.
1. #i!(anni De "icheli, Synthesis and 2.ti+i,ati!n !f Digital Circuits, Tata "c#ra$-Hill.
(aluati!n 0r!cedure :
Class test : %0
*ttendance: 03
Class 0erf!r+ance : 03
4a+inati!n: 50 6"id7nd8
Digital Logic Design
3-9
"ransistor: B#il$ing Block o% Com&#ters
Micro&rocessors contain millions o% transistors
: Intel 0entiu+ 1 6%0008: '( million
: I-" 0!$er0C 530); 6%00%8: 3( million
:
I-"<*..le 0!$er0C #3 6%0038: )( million
Logicall*+ each transistor acts as a s,itch
Com-ine$ to im&lement logic %#nctions
: ./D+ 01+ /0"
Com-ine$ to -#il$ higher-le2el str#ct#res
: .$$er+ m#lti&le3er+ $eco$er+ register+ 4
Com-ine$ to -#il$ &rocessor
: LC-3
Moore's Law
2n 3456, 0ordon Moore co!founder of the 2ntel corporation predicted
that "The number of transistors and resistors on a single chip will
double eery !" months" regarding the development of
semiconductor gate technology" 7hen Moore made his famous
comment ay $ac) in 3456 there ere appro%imately only 58
individual transistor gates on a single silicon chip or die" Today, the
2ntel Corporation have placed around 9"8 #illion individual transistor
gates onto its ne (uad!core 2tanium 5:!$it microprocessor chip and
the count is still rising;"
Logic 5amilies
6n or$er to ass#re correct o&eration ,hen gates are
interconnecte$ the* are normall* &ro$#ce$ in %amilies
"he most ,i$el* #se$ %amilies are:
- com&lementar* metal o3i$e semicon$#ctor 7CM0S8:
the '000 series o% chi&s
- transistor-transistor logic 7""L8: the 9'00 series
- emitter-co#&le$ logic 7ECL8
Logic Families
Logic Families
""L 7"ransistor "ransistor Logic8 6ntegrate$-circ#it technolog*
that #ses the -i&olar transistor as the &rinci&al circ#it element:
CM0S 7Com&limentar* Metal 03i$e Semicon$#ctor8 6ntegrate$-
circ#it technolog* that #ses the %iel$-e%%ect transistor as the &rinci&al
circ#it element:
ECL 7Emitter Co#&le$ Logic8 6ntegrate$-circ#it technolog* that #ses
the -i&olar transistors con%ig#re$ as a $i%%erential am&li%ier: "his
eliminates sat#ration an$ im&ro2es s&ee$ -#t #ses more &o,er than
other %amilies:
Logic 5amil* Characteristics
Com&lementar* metal o3i$e semicon$#ctor 7CM0S8
most ,i$el* #se$ %amil* %or large-scale $e2ices
com-ines high s&ee$ ,ith lo, &o,er cons#m&tion
#s#all* o&erates %rom a single s#&&l* o% ) ;) <
e3cellent noise imm#nit* o% a-o#t 30= o% s#&&l* 2oltage
can -e connecte$ to a large n#m-er o% gates 7a-o#t )08
man* %orms some ,ith t
PD
$o,n to ; ns
&o,er cons#m&tion $e&en$s on s&ee$ 7&erha&s ; mW8
"ransistor-transistor logic 7""L8
-ase$ on -i&olar transistors
one o% the most ,i$el* #se$ %amilies %or small- an$ me$i#m-scale
$e2ices rarel* #se$ %or <LS6
t*&icall* o&erate$ %rom )< s#&&l*
t*&ical noise imm#nit* a-o#t ; ;:> <
man* %orms+ some o&timise$ %or s&ee$+ &o,er+ etc:
high s&ee$ 2ersions com&ara-le to CM0S 7? ;:) ns8
lo,-&o,er 2ersions $o,n to a-o#t ; mW@gate
Emitter-co#&le$ logic 7ECL8
-ase$ on -i&olar transistors+ -#t remo2es &ro-lems o% storage time
-* &re2enting the transistors %rom sat#rating
2er* %ast o&eration - &ro&agation $ela*s o% ;ns or less
high &o,er cons#m&tion+ &erha&s >0 mW@gate
lo, noise imm#nit* o% a-o#t 0:2-0:2) <
#se$ in some high s&ee$ s&ecialist a&&lications+ -#t no, largel*
re&lace$ -* high s&ee$ CM0S
D6A6".L 6C SBEC656C."60/S
<
Dri2e Ca&a-ilities- sometimes re%erre$ to as %an-in
or %an-o#t:
<
5an o#t- n#m-er o% in&#ts o% a logic %amil* that can
-e $ri2en -* a single o#t&#t: "he $ri2e ca&a-ilit*
o% o#t&#ts:
<
5an in- the loa$ an in&#t &laces on an o#t&#t:
<
Bro&agation $ela*- has to $o ,ith the Cs&ee$D o%
the logic element: Lo,er &ro&agation $ela*s mean
higher s&ee$ ,hich is a $esira-le characteristic:
<
Bo,er Dissi&ation- generall*+ as &ro&agation
$ela*s decrease+ &o,er cons#m&tion an$ heat
generation increase. CM0S is note$ %or lo, &o,er
cons#m&tion:
. Com&arison o% Logic 5amilies
%3.3
Barameter CM0S ""L ECL
-asic gate =*=D<=2R =*=D 2R<=2R
)an-!ut >30 10 %3
0!$er .er gate 6+?8 1 @ 1 "H, 1 - %% 1 - 33
=!ise i++unity 4cellent Aery g!!d #!!d
t
PD
6ns8 1 - %00 1.3 B 33 1 - 1
;: "he $ri2e ca&a-ilit* o% logic $e2ice o#t&#ts is
sometimes calle$ EEE 7%an in+ %an o#t8: 6t is the
n#m-er o% in&#ts o% a logic %amil* that can -e
$ri2en -* a single o#t&#t:
(Left click mouse for questions and answers)
5an 0#t
2: CM0S $e2ices are note$ %or their e3tremel*
EEE 7high+ lo,8 &o,er cons#m&tion:
Lo,
3: . logic $e2ice ,ith a lo, &ro&agation $ela*
,o#l$ -e consi$ere$ to -e a EEE 7high+ lo,8
s&ee$ $e2ice:
Figh
': Se2eral $esira-le characteristics o% logic
$e2ices are goo$ $ri2e ca&a-ilities+ lo,
&o,er cons#m&tion+ an$ EEE 7high+ lo,8
&ro&agation $ela*s:
Lo,
"ES"
e* Boints
Bh*sical gates are not i$eal com&onents
Logic gates are man#%act#re$ in a range o% logic %amilies
"he a-ilit* o% a gate to ignore noise is its Gnoise
imm#nit*H
Both M0S5E"s an$ -i&olar transistors are #se$ in gates
.ll logic gates e3hi-it a &ro&agation $ela* ,hen
res&on$ing to changes in their in&#ts
"he most ,i$el* #se$ logic %amilies are CM0S an$ ""L
CM0S is a2aila-le in a range o% %orms o%%ering high
s&ee$ or 2er* lo, &o,er cons#m&tion
""L logic is also &ro$#ce$ in man* 2ersions+ each
o&timise$ %or a &artic#lar characteristic
Classi%ication o% 6ntegrate$ Circ#its:
Small Scale 6ntegration or 7SS68 - Contain #& to ;0 transistors or a %e, gates ,ithin a single
&ackage s#ch as ./D+ 01+ /0" gates:
Me$i#m Scale 6ntegration or 7MS68 - -et,een ;0 an$ ;00 transistors or tens o% gates ,ithin a
single &ackage an$ &er%orm $igital o&erations s#ch as a$$ers+ $eco$ers+ co#nters+ %li&-%lo&s
an$ m#lti&le3ers:
Large Scale 6ntegration or 7LS68 - -et,een ;00 an$ ;+000 transistors or h#n$re$s o% gates an$
&er%orm s&eci%ic $igital o&erations s#ch as 6@0 chi&s+ memor*+ arithmetic an$ logic #nits:
<er*-Large Scale 6ntegration or 7<LS68 - -et,een ;+000 an$ ;0+000 transistors or tho#san$s o%
gates an$ &er%orm com&#tational o&erations s#ch as &rocessors+ large memor* arra*s an$
&rogramma-le logic $e2ices:
S#&er-Large Scale 6ntegration or 7SLS68 - -et,een ;0+000 an$ ;00+000 transistors ,ithin a
single &ackage an$ &er%orm com&#tational o&erations s#ch as micro&rocessor chi&s+ micro-
controllers+ -asic B6Cs an$ calc#lators:
Iltra-Large Scale 6ntegration or 7ILS68 - more than ; million transistors - the -ig -o*s that are
#se$ in com&#ters CBIs+ ABIs+ 2i$eo &rocessors+ micro-controllers+ 5BA.s an$ com&le3
B6Cs:
3-1C
Sim&le S,itch Circ#it
S,itch o&en:
: /o c#rrent thro#gh circ#it
: Light is o%%
: <
o#t
is J2:K<
S,itch close$:
: Short circ#it across s,itch
: C#rrent %lo,s
: Light is on
: <
o#t
is 0<
Switch-based circuits can easily re.resent t$! states:
!n<!ff, !.en<cl!sed, (!ltage<n! (!ltage.
3-1D
n-t*&e M0S "ransistor
M0S L Metal 03i$e Semicon$#ctor
: t,o t*&es: n-t*&e an$ &-t*&e
n-t*&e
:
,hen Aate has &ositi2e 2oltage+
short circ#it -et,een #; an$ #2
7s,itch close$8
:
,hen Aate has !ero 2oltage+
o&en circ#it -et,een #; an$ #2
7s,itch o&en8
Gate = 1
Gate = 0
Ter+inal E% +ust be
c!nnected t! #=D 60A8.
3-%0
&-t*&e M0S "ransistor
&-t*&e is complementary to n-t*&e
: ,hen Aate has &ositi2e 2oltage+
o&en circ#it -et,een #; an$ #2
7s,itch o&en8
: ,hen Aate has !ero 2oltage+
short circ#it -et,een #; an$ #2
7s,itch close$8
Gate = 1
Gate = 0
Ter+inal E1 +ust be
c!nnected t! 7%.DA.
3-%1
Logic Aates
Ise s,itch -eha2ior o% M0S transistors
to im&lement logical %#nctions: ./D+ 01+ /0":
Digital s*m-ols:
:
recall that ,e assign a range o% analog 2oltages to each
$igital 7logic8 s*m-ol
: assignment o% 2oltage ranges $e&en$s on
electrical &ro&erties o% transistors -eing #se$

t*&ical 2al#es %or M;M: J)<+ J3:3<+ J2:K<

%rom no, on ,eNll #se J2:K<

3-%%
CM0S Circ#it
Com&lementar* M0S
Ises -oth n-t*&e an$ &-t*&e M0S transistors
:
&-t*&e

.ttache$ to J 2oltage

B#lls o#t&#t 2oltage IB ,hen in&#t is !ero

:
n-t*&e

.ttache$ to A/D

B#lls o#t&#t 2oltage D0W/ ,hen in&#t is one

)!r all in.uts, +aFe sure that !ut.ut is either c!nnected t! #=D !r t! 7,
but n!t b!thG
CM0S 6n2erter
.
n
#=D
A
DD
*
H I *J
Since the gate is essentially an !.en circuit it dra$s n! current,
and the !ut.ut (!ltage $ill be eKual t! either gr!und !r t! the
.!$er su..ly (!ltage, de.ending !n $hich transist!r is
c!nducting.
?hen in.ut * is gr!unded 6l!gic 08, the =-channel "2S)T is
unbiased, and theref!re has n! channel enhanced $ithin itself. It
is an !.en circuit, and theref!re lea(es the !ut.ut line
disc!nnected fr!+ gr!und. *t the sa+e ti+e, the 0-channel
"2S)T is f!r$ard biased, s! it has a channel enhanced $ithin
itself, c!nnecting the !ut.ut line t! the 7Asu..ly. This .ulls the
!ut.ut u. t! 7A 6l!gic 18.
?hen in.ut * is at 7A 6l!gic 18, the 0-channel "2S)T is !ff
and the =-channel "2S)T is !n, thus .ulling the !ut.ut d!$n
t! gr!und 6l!gic 08. Thus, this circuit c!rrectly .erf!r+s l!gic
in(ersi!n, and at the sa+e ti+e .r!(ides acti(e .ull-u. and .ull-
d!$n, acc!rding t! the !ut.ut state.
CM0S 6n2erter - 0&eration
3-%3
6n2erter 7/0" Aate8
6n 0#t
0 < 2:K <
2:K < 0 <
6n 0#t
0 ;
; 0
Truth table
3-%9
./D Aate
Add inverter to NAND.
. B C
0 0 0
0 ; 0
; 0 0
; ; ;
3-%5
01 Aate
Add inverter to NOR.
. B C
0 0 0
0 ; ;
; 0 ;
; ; ;
3-%C
. B C
0 0 ;
0 ; 0
; 0 0
; ; 0
=!te: Serial structure !n t!., .arallel !n b!tt!+.
/01 Aate
3-%D
. B C
0 0 ;
0 ; ;
; 0 ;
; ; 0
=!te: 0arallel structure !n t!., serial !n b!tt!+.
/./D Aate 7./D-/0"8
=8
Constr#cting Aates
"ransistor
. $e2ice that acts either as a ,ire that
con$#cts electricit* or as a resistor that -locks
the %lo, o% electricit*+ $e&en$ing on the 2oltage
le2el o% an in&#t signal
. transistor has no mo2ing &arts+ *et acts like
a s,itch
6t is ma$e o% a semicon$#ctor material+ ,hich
is neither a &artic#larl* goo$ con$#ctor o%
electricit* nor a &artic#larl* goo$ ins#lator
=3
Constr#cting Aates
. transistor has three
terminals
B
. so#rce
B
. -ase
B
.n emitter+ t*&icall*
connecte$ to a gro#n$ ,ire
6% the electrical signal is
gro#n$e$+ it is allo,e$ to
%lo, thro#gh an alternati2e
ro#te to the gro#n$ 7literall*8
,here it can $o no harm
5ig#re ':( "he connections o% a transistor
=9
Constr#cting Aates
"he easiest gates to create are the /0"+ /./D+
an$ /01 gates
5ig#re ':K Constr#cting gates #sing transistors
3-33
Basic Logic Aates
3-31
DeMorganNs La,
Con2erting ./D to 01 7,ith some hel& %rom /0"8
Consi$er the %ollo,ing gate:
A B
0 0 ; ; ; 0
0 ; ; 0 0 ;
; 0 0 ; 0 ;
; ; 0 0 0 ;
AB B A
AB
Sa+e as *7-G
To convert AND to OR
(or vice versa),
invert inputs and output.
3-33
More than 2 6n&#tsO
./D@01 can take an* n#m-er o% in&#ts:
: ./D L ; i% all in&#ts are ;:
: 01 L ; i% an* in&#t is ;:
:
Similar %or /./D@/01:
Can im&lement ,ith m#lti&le t,o-in&#t gates+
or ,ith single CM0S circ#it:
3-39
S#mmar*
M0S transistors are #se$ as s,itches to im&lement
logic %#nctions:
: n-t*&e: connect to A/D+ t#rn on 7,ith ;8 to &#ll $o,n to 0
: &-t*&e: connect to J2:K<+ t#rn on 7,ith 08 to &#ll #& to ;
Basic gates: /0"+ /01+ /./D
: Logic %#nctions are #s#all* e3&resse$ ,ith ./D+ 01+ an$ /0"
DeMorganNs La,
: Con2ert ./D to 01 7an$ 2ice 2ersa8
-* in2erting in&#ts an$ o#t&#t
3-35
B#il$ing 5#nctions %rom Logic Aates
o!binational "o#ic ircuit
:
o#t&#t $e&en$s onl* on the c#rrent in&#ts
:
stateless
Se$uential "o#ic ircuit
: o#t&#t $e&en$s on the seP#ence o% in&#ts 7&ast an$ &resent8
: stores in%ormation 7state8 %rom &ast in&#ts
WeNll %irst look at some #se%#l com-inational circ#its+
then sho, ho, to #se seP#ential circ#its to store
in%ormation:
3-3C
Deco$er
n in&#ts+ 2
n
o#t&#ts
: e3actl* one o#t&#t is ; %or each &ossi-le in&#t &attern
%-bit
decoder
3-3D
M#lti&le3er 7MIQ8
n--it selector an$ 2
n
in&#ts+ one o#t&#t
: o#t&#t eP#als one o% the in&#ts+ $e&en$ing on selector
&-to-' ()*
3-10
5#ll .$$er
.$$ t,o -its an$ carr*-in+
&ro$#ce one--it s#m an$ carr*-o#t:
A B C
in
S C
out
0 0 0 0 0
0 0 ; ; 0
0 ; 0 ; 0
0 ; ; 0 ;
; 0 0 ; 0
; 0 ; 0 ;
; ; 0 0 ;
; ; ; ; ;
3-11
5o#r--it .$$er
3-1%
Logical Com&leteness
Can im&lement ./R tr#th ta-le ,ith ./D+ 01+ /0":
A B C D
0 0 0 0
0 0 ; 0
0 ; 0 ;
0 ; ; 0
; 0 0 0
; 0 ; ;
; ; 0 0
; ; ; 0
1. AND combinations
that yield a "1" in the
truth table.
2. OR the results
of the AND gates.
3-13
Com-inational 2s: SeP#ential
Com-inational Circ#it
: al,a*s gi2es the same o#t&#t %or a gi2en set o% in&#ts

e3: a$$er al,a*s generates s#m an$ carr*+

regar$less o% &re2io#s in&#ts
SeP#ential Circ#it
:
stores in%ormation
:
o#t&#t $e&en$s on store$ in%ormation 7state8 &l#s in&#t

so a gi2en in&#t might &ro$#ce $i%%erent o#t&#ts+

$e&en$ing on the store$ in%ormation
:
example: ticket co#nter

a$2ances ,hen *o# &#sh the -#tton

o#t&#t $e&en$s on &re2io#s state

:
#se%#l %or -#il$ing Cmemor*D elements an$ Cstate machinesD
3-11
1-S Latch: Sim&le Storage Element
1 is #se$ to CresetD or CclearD the element set it to !ero:
S is #se$ to CsetD the element set it to one:
6% -oth 1 an$ S are one+ o#t co#l$ -e either !ero or one:
: CP#iescentD state -- hol$s its &re2io#s 2al#e
: note: i% a is ;+ - is 0+ an$ 2ice 2ersa
1
0
1
1
1
1
0
0
1
1
0
0
1
1
3-13
Clearing the 1-S latch
S#&&ose ,e start ,ith o#t&#t L ;+ then change 1 to !ero:
0#t&#t changes to !ero:
Then set R+' to ,store- value in $uiescent state.
1
0
1
1
1
1
0
0
1
0
1
0
0
0
1
1
3-19
Setting the 1-S Latch
S#&&ose ,e start ,ith o#t&#t L 0+ then change S to !ero:
0#t&#t changes to one:
Then set S+' to ,store- value in $uiescent state.
1
1
0
0
1
1
0
1
1
1
0
0
3-15
1-S Latch S#mmar*
R I S I 1
: hol$ c#rrent 2al#e in latch
S I 0, RI1
:
set 2al#e to ;
R I 0, S I 1
: set 2al#e to 0
R I S I 0
: -oth o#t&#ts eP#al one
: %inal state $etermine$ -* electrical &ro&erties o% gates
: Don.t do it/
3-1C
Aate$ D-Latch
",o in&#ts: D 7$ata8 an$ WE 7,rite ena-le8
: ,hen WE L ;+ latch is set to 2al#e o% D

S L /0"7D8+ 1 L D
:
,hen WE L 0+ latch hol$s &re2io#s 2al#e

S L 1 L ;
3-1D
1egister
. register stores a m#lti--it 2al#e:
: We #se a collection o% D-latches+ all controlle$ -* a common
WE:
: When WEL;+ n--it 2al#e D is ,ritten to register:
3-30
1e&resenting M#lti--it <al#es
/#m-er -its %rom right 708 to le%t 7n-;8
: S#st a con2ention -- co#l$ -e le%t to right+ -#t m#st -e consistent
Ise -rackets to $enote range:
DLl:rM $enotes -it l to -it r+ %rom left to right
Ma* also see .N11:D>+
es&eciall* in har$,are -lock $iagrams:
A = 0101001101010101
A[20! = 101
A[1"#! = 101001
0 1$
3-31
Memor*
/o, that ,e kno, ho, to store -its+
,e can -#il$ a memor* a logical k m arra* o%
store$ -its:

0 I %
n
l!cati!ns
! bits
.$$ress S&ace:
nu+ber !f l!cati!ns
6usually a .!$er !f %8
.$$ressa-ilit*:
nu+ber !f bits .er l!cati!n
6e.g., byte-addressable8
3-3%
2
2
3 3 Memor*
address
decoder
word select
word WE
address
write
enable
input
bits
output bits
3-33
More Memor* Details
"his is a not the ,a* act#al memor* is im&lemente$:
:
%e,er transistors+ m#ch more $ense+
relies on electrical &ro&erties
B#t the logical str#ct#re is 2er* similar:
:
a$$ress $eco$er
:
,or$ select line
:
,or$ ,rite ena-le
",o -asic kin$s o% 1.M 71an$om .ccess Memor*8
Static 1.M 7S1.M8
: %ast+ maintains $ata as long as &o,er a&&lie$
D*namic 1.M 7D1.M8
: slo,er -#t $enser+ -it storage $eca*s m#st -e &erio$icall*
re%reshe$
Also, non-volatile !e!ories1 RO(, PRO(, 2lash, 3
3-31
State Machine
.nother t*&e o% seP#ential circ#it
: Com-ines com-inational logic ,ith storage
: C1emem-ersD state+ an$ changes o#t&#t 7an$ state8
-ase$ on in&#ts an$ c#rrent state
State (achine
C!+binati!nal
/!gic Circuit
St!rage
le+ents
In.uts 2ut.uts
3-33
Com-inational 2s: SeP#ential
",o t*&es o% Ccom-inationD locks
1 1 C 1
30
13
3
10 %0
%3
Com-inational
Success de.ends !nly !n
the (alues, n!t the !rder in
$hich they are set.
SeP#ential
Success de.ends !n
the seKuence !f (alues
6e.g, R-13, /-%%, R-38.
3-39
State
"he state o% a s*stem is a sna&shot o%
all the rele2ant elements o% the s*stem
at the moment the sna&shot is taken:
E3am&les:
:
"he state o% a -asket-all game can -e re&resente$ -*
the score-oar$:

/#m-er o% &oints+ time remaining+ &ossession+ etc:

:
"he state o% a tic-tac-toe game can -e re&resente$ -*
the &lacement o% QHs an$ 0Hs on the -oar$:
3-35
State o% SeP#ential Lock
0#r lock e3am&le has %o#r $i%%erent states+
la-elle$ .-D:
.: "he lock is not o&en+
an$ no rele2ant o&erations ha2e -een &er%orme$:
B: "he lock is not o&en+
an$ the #ser has com&lete$ the 1-;3 o&eration:
C: "he lock is not o&en+
an$ the #ser has com&lete$ 1-;3+ %ollo,e$ -* L-22:
D: "he lock is o&en:
3-3C
State Diagram
Sho,s states an$
actions that ca#se a transition -et,een states:
3-3D
5inite State Machine
. $escri&tion o% a s*stem ,ith the %ollo,ing com&onents:
;: . %inite n#m-er o% states
2: . %inite n#m-er o% e3ternal in&#ts
3: . %inite n#m-er o% e3ternal o#t&#ts
': .n e3&licit s&eci%ication o% all state transitions
): .n e3&licit s&eci%ication o% ,hat $etermines each
e3ternal o#t&#t 2al#e
0%ten $escri-e$ -* a state $iagram:
: 6n&#ts trigger state transitions:
: 0#t&#ts are associate$ ,ith each state 7or ,ith each transition8:
3-90
"he Clock
5reP#entl*+ a clock circ#it triggers transition %rom
one state to the ne3t:
.t the -eginning o% each clock c*cle+
state machine makes a transition+
-ase$ on the c#rrent state an$ the e3ternal in&#ts:
: =!t al$ays reKuired. In l!cF e4a+.le, the in.ut itself triggers a transiti!n.
%1&
%0&
time
One
'ycle
3-91
6m&lementing a 5inite State Machine
Com-inational logic
: Determine o#t&#ts an$ ne3t state:
Storage elements
:
Maintain state re&resentation:
State (achine
C!+binati!nal
/!gic Circuit
St!rage
le+ents
In.uts 2ut.uts
Cl!cF
3-9%
Storage: Master-Sla2e 5li&%lo&
. &air o% gate$ D-latches+
to isolate next state %rom current state:
During 1
st
.hase 6cl!cFI18,
.re(i!usly-c!+.uted state
bec!+es current state and is
sent t! the l!gic circuit.
During %
nd
.hase 6cl!cFI08,
ne4t state, c!+.uted by
l!gic circuit, is st!red in
/atch *.
3-93
Storage
Each master-sla2e %li&%lo& stores one state -it:
"he n#m-er o% storage elements 7%li&%lo&s8 nee$e$
is $etermine$ -* the n#m-er o% states
7an$ the re&resentation o% each state8:
E3am&les:
: SeP#ential lock

5o#r states t,o -its

: Basket-all score-oar$

9 -its %or each score+ ) -its %or min#tes+ > -its %or secon$s+
; -it %or &ossession arro,+ ; -it %or hal%+ 4
3-91
Com&lete E3am&le
. -linking tra%%ic sign
: /o lights on
: ; & 2 on
:
;+ 2+ 3+ & ' on
:
;+ 2+ 3+ '+ & ) on
:
7re&eat as long as s,itch
is t#rne$ on8
D./AE1
"2A
RI#HT
1
%
3
1
3
3-93
"ra%%ic Sign State Diagram
State bit S
1
State bit S
0
S$itch !n
S$itch !ff
2ut.uts
Transition on each cloc0 c5cle.
3-99
"ra%%ic Sign "r#th "a-les
2ut.uts
6de.end !nly !n state: S
1
S
0
8
S
;
S
0
T R Q
0 0 0 0 0
0 ; ; 0 0
; 0 ; ; 0
; ; ; ; ;
/ights 1 and %
/ights 3 and 1
/ight 3
=e4t State: S
1
OS
0
O
6de.end !n state and in.ut8
6n S
;
S
0
S
;
H S
0
H
0 Q Q 0 0
; 0 0 0 ;
; 0 ; ; 0
; ; 0 ; ;
; ; ; 0 0
S$itch
?hene(er InI0, ne4t state is 00.
3-95
"ra%%ic Sign Logic
"aster-sla(e
fli.fl!.
3-9C
5rom Logic to Data Bath
"he $ata &ath o% a com&#ter is all the logic #se$ to
&rocess in%ormation:
: See the $ata &ath o% the LC-3 on ne3t sli$e:
Com-inational Logic
: Deco$ers -- con2ert instr#ctions into control signals
: M#lti&le3ers -- select in&#ts an$ o#t&#ts
: .LI 7.rithmetic an$ Logic Init8 -- o&erations on $ata
SeP#ential Logic
: State machine -- coor$inate control signals an$ $ata mo2ement
: 1egisters an$ latches -- storage elements
3-9D
LC-3 Data Bath
C!+binati!nal
/!gic
State "achine
St!rage