One Day National Conference on

VLSI Design Architectures and

Applications
School of Electronics Engineeering (SENSE)
VIT Chennai, India.
One day Pre Conference Workshop on
Analog IC Design using Cadence
School of Electronics Engineeering (SENSE)
VIT Chennai, India
Conveners
Dr. T. Vigneswaran
Prof. P. Reenamonica
VIT - A place to learn; A chance to grow
REGISTRATION FEE
Conference :
Industry/Faculty Partcipants : Rs. 1500/-
Academicians/Research scholars &
PG students : Rs.1000/-
Workshop :
Industry/Faculty Partcipants : Rs. 1000/-
Academicians/Research scholars &
PG students : Rs.750/-
Registraton Fee includes Proceedings, Courseware, Working
Lunch and Tea.
Conference and workshop will have separate
registraton.
Interested Partcipants from Colleges, Industry and Research
Insttutes are requested to fll the registraton form and
send the same to Dr. T. Vigneswaran, Convener, NCVDAA
2014. Registraton fee will be accepted by Demand Draf
drawn in favour of VIT Chennai, payable at Chennai along
with the completed registraton form. Registraton fee does
not include accommodaton charges.
DATES TO REMEMBER
Conference:
Last date for receipt of papers : 25
th
March, 2014
Acceptance intmaton : 31
st
March, 2014
Camera ready papers : 10
th
April, 2014
Workshop:
ORGANIZING SECRETARIES
Dr. V.S. Kanchana Bhaskaran, SENSE. VITCC.
Dr. A.Ravisankar, SENSE. VITCC.
Dr. Anith Nelleri, SENSE. VITCC.
Dr. S.R.S. Prabaharan, SENSE. VITCC.
Dr. R.Manojkumar, SENSE. VITCC.
VIT Chennai
VIT University for the past 25 years has made a mark in the feld
of higher educaton in India impartng quality educaton in a
cross cultural ambience, intertwined with extensive applicaton
oriented research. Established by well-known educatonalist
and former parliamentarian, Dr. G Viswanathan, Founder and
Chancellor is a visionary who transformed VIT into a center of
excellence in higher technical educaton. His dream has taken
the shape of VIT Chennai. Dr. V. Raju, Former Professor of State
University of New York, USA, currently the Vice Chancellor,
strives to internalize the world class educatonal standards.
Dr. Anand A. Samuel, Pro-Vice Chancellor leads the team in
Chennai with the following objectves:
To maximize the Industrial Connectvity
To Create Centers of Excellence in niche areas of
research
To enrich technological and Managerial Human Capital
nurtured in a multcultural ambience
To provide a common platorm for the agglomeraton
of ideas of personnel from various walks of life for
learning enrichment
To create opportunities and exploit the available
resources to beneft industry/society
To encourage partcipaton in the Natonal Agenda of
knowledge building
To foster International collaborations for mutual
benefts in areas of research.
WORKSHOP
One day Pre Conference Workshop on
Analog IC Design using Cadence
Organized
Prof. P. Manikandan Prof. S. Umadevi
and
Interested delegates can attend the workshop with prior
registaraton. The partcipants of the workshop will be given
certfcates.(limited to 50 seats as First come First Serve Basis)
18
th
April 2014
Organized By
VLSI Division,
17
th
April 2014
Organized by
One day Pre- workshop will be conducted by School of
Electronics Engineering (SENSE) on 17-4-2014.
Last date of Registraton : 10
th
April, 2014
Acceptance intmaton : 11
th
April, 2014
manikandan.p@vit.ac.in umadevi.s@vit.ac.in
8870702353 8939916003
ADDRESS FOR COMMUNICATION
Dr. T.Vigneswaran
Professor, VLSI Division,
School of Electronics Engineering (SENSE) VIT
Chennai, Vandalur - Kelambakkam Road Chennai - 600
127.
Phone : 9884222629 / 9840837624
Email id: vigneswaran.t@vit.ac.in
About SENSE
The School of Electronics Engineering was established
for impartng state-of-the-art educaton, training and
research in the field Electronics & Communication
Engineering and allied areas. It ofers B.Tech, M.Tech,
MS (By Research) & Ph.D in the domains of ECE, VLSI
Design & Embedded Systems .The expertse of faculty
members includes VLSI, Communicaton, Embedded
Systems & Signal Processing.
Conference Theme
The VLSI Design Architectures and Applications
Conference serving as a forum for researchers and
designers to present and discuss current topics in VLSI
design, electronic design automation, embedded
systems, and enabling technologies. It covers the entre
spectrum of actvites in the two vital areas of very large
scale integraton (VLSI) and embedded systems, which
underpin the semiconductor industry
Workshop Theme
The objectve of the program is to make the
partcipants understand the key principles, concepts
and techniques involved in analog IC design. The hands
on training using CADENCE, an industry standard CAD
tool, will help the participants to design analog IC
components to meet the given specifcaton.
Workshop Content
Design of CMOS OTA and its Applicatons
Basic & Diferental OTA
Realizaton of resistors & Inductors using OTA
Realizaton of actve R-C flters using OTA
Topics of interest include, but not limited to
Low Power VLSI.
Image/Signal Processing
Cryptography
Networking
Analog/Digital-Communicaton
Embedded Systems
MEMS/NEMS
NanoTechnology
NanoElectronics
Satellite Communicaton
Microwave Engineering
Robotcs
Neural Networks
VLSI/DSP Architectures
Analog VLSI
Cellular/Mobile Communicaton
Design, Simulaton and Test of Digital, Analog, Mixed
Mode and RF Circuits and Systems
VLSI, ASIC, FPGA, MPSoC and SoC
Computer Aided Design and Electronic Design
Automaton
Circuits and Systems for Low Power Applicatons
Circuits and Systems for Cryptography
Route Map
One Day National Conference on
VLSI Design Architectures and
Applications
&
One day Pre Conference Workshop on
Analog IC Design using Cadence
REGISTRATION FORM
Name : .............................................................................
Designation : .............................................................................
Organization : .............................................................................
Address for Correspondence :
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E-mail : ............................................................................
Registration For
a) Conference :
b) Workshop :
c) For Both :
PAYMENT DETAILS :
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DD No. : .................................. Date : ..............................
(In favour of VIT Chennai payable at Chennai)
Name of Bank & Branch :
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Date : Signature