VLSI

[B.
E]E&TC [SEMESTER II ] [VLSI]Manual

Department of Electronics and Telecommunication Engineering Page 1

J. T. Mahajan College Of Engineering, Faizpur

Department Of Electronics and Telecommunication Engineering

LAB MANUAL

Subject: VLSI
Class: B.E. (E&TC)

[B.E]E&TC [SEMESTER II ] [VLSI]Manual


INDEX

Sr
No.
Name of the Experiment Page
No.
Date Remark
1 Write VHDL code to realize all the
logic gates

2 Write VHDL code to describe
functions of Half Adder and Full
Adder Using Various Modeling Styles.

3 Implement scrolling of data on seven
segment display using keyboard.

4 Write a VHDL code for D-latch.
5 Write a VHDL code for SR-latch.
6 Write VHDL code to describe
functions of 4:1 Multiplexer.

7 Write VHDL code for 2:4 Decoder.
8 Write VHDL code for 3-bit UP/DOWN
counter.

9 Write VHDL code for 8-bit ALU
10
To study XILINX software.

11
To implement 2s complementor for
8 bit binary number using
behavioral.



Experiment No.: 1 Date:

TITLE: Write VHDL code to realize all the logic gates

OBJECTIVE: To understand the operators and architectures used in
VHDL.

Requirement:
1. Xilinx navigator
2. FPGA
3. CPLD kit.

Theory:Logical gates used in the circuit are the basic building blocks of
any digital circuit used . There are various types of gates Ex . Ex-OR ,
AND , OR etc.

Procedure:
1) Select Xilinx navigator
2) File > New > Project Name
3) Select Device and Design Flow for project
4) For CPLD
Device Family XC9500
Device XC9572
Package PC84
Speed Grade -15
For Spartan FPGA:
Package PC208
Speed Grade -4
5) Go to Project > New Source > VHDL module > File Name
6) Give I/P and O/P ports
7) Write down the program
8) Go to user constants
9) Launch Model Sim > Signal window > Edit > Input
10)See waveform on windows and then close
11) Go to generate program file , right click on it and return all
12)Select boundary scan mode>automatically connected to cable
and identify boundary scan change
13)Click on PROM and mes file for FPGA OR .jeo for CPLD .
14)Click on FPGA / CPLD And add bit file
15) Right click on PROM then Select Verify FPGA
16) Verify circuit in kit

Result:we can perform various logical operations like AND, OR,Ex-
OR,NOR


LOGIC GATES
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity logicgates is

Port ( a : in std_logic;

b : in std_logic;

p : out std_logic;

q : out std_logic;

r : out std_logic;

s : out std_logic);

end logicgates;

architecture dataflow of logicgates is

begin

p<=a and b;

q<=a or b;

r<=a nor b;

s<=a xor b;

end dataflow;
.




TITLE: Write VHDL code to describe functions of Half Adder and Full
Adder Using Various Modeling Styles.

OBJECTIVE: To understand various modeling styles in VHDL

Requirement:
1. Xilinx navigator
2. FPGA
3. CPLD kit.

Theory:
There are three types of modeling in VHDL
a. Structural Modeling Style : As a set of interconnected
components
b. Dataflow Modeling Style : As a set of concurrent assignment
statement
c. Behavioral Modeling Style : As a set of sequential assignment
We can also use mixed type of modeling as per the requirement
i.e. we could use component instantiation statement that
represents structures , concurrent signal assignment statement
that represent dataflow and process statement that represent
behavior
Procedure:
6) Write down program and source
7) User constraints > assign package pin > Close
8) Launch Model Sim > See O/P waveforms
9) Generate program file > return all
10) Configure Device
11) Select boundary scan mode > Automatically
12) Add .mcs and .jeo files and bit file
14)Verify circuit in kit

Result:Using various modeling styles in VHDL ,we perform the half & full
adder



FULL ADDER

library IEEE;




entity fulladder is


b : in std_logic;

c : in std_logic;

sum : out std_logic;

carry : out std_logic);

end fulladder;

architecture Dataflow of fulladder is

signal c1,c2,s1:std_logic;

begin

s1<=a xor b;

c1<=a and b;

c2<= c and s1;

sum<= s1 xor c;

carry<=c1 or c2;
end Dataflow;



HALF ADDER

library IEEE;




entity halfadder is


b : in std_logic;

sum : out std_logic;

carry : out std_logic);

end halfadder;

architecture Dataflow of halfadder is

begin

sum<=a xor b;

carry<=a and b;

end Dataflow;




TITLE: Implement scrolling of data on seven segment display using
keyboard.
.
OBJECTIVE: To understand the display properties and interfacing.

Requirement:
1. Xilinx navigator,
2. FPGA (Xilinx device XC25200)
3. CPLD kit.

Theory:
A seven segment LED display controlled by FPGA O/P. Each digit is
illuminated with individual control signals.
This is achieved by lighting the individual segment along with the
associated cathode control signal for that segment .

Procedure:

6) Write down program and save
7) Go to constraint > Assign Pin Package > save > close
8) Launch Model Sim see output waveform
9) Generate program file return all
10)Configure device
11) Select boundary scan mode > automatically
12)Add .jeo and .bit files
13)Right click PROM and Erase and verify

Result:
We can display data from the keyboard on the seven segment
display



VHDL CODE FOR BCD TO SEVEN SEGMENT DECODER

library IEEE;




entity BCD2LED is

Port ( D : in std_logic_vector (3 downto 0);

O : out std_logic_vector (6 downto 0);

end BCD2LED;

architecture Dataflow of halfadder is

begin

case D is

WHEN0000=>O<= 1111110;
WHEN0000=>O<= 0110000;
WHEN0000=>O<= 1101101;
WHEN0000=>O<= 1111001;
WHEN0000=>O<= 0110011;
WHEN0000=>O<= 1011011;
WHEN0000=>O<= 0011111;
WHEN0000=>O<= 1111110;
WHEN0000=>O<= 1110000;
WHEN0000=>O<= 1111111;
WHEN0000=>O<= 0000000;

END CASE;
END PROCESS;
END BEHAVIORAL;




TITLE: Write a VHDL code for D-latch.

OBJECTIVE: To understand various statements such as wait, if ,loop
etc.To understand the concept of Delta delay

Requirement:

Theory:Delta Delay: Delta delay is very small delay .This delay models
hardware where a minimal amount of time is needed for a change to
occur. It allows for ordering of events that occur at the same simulation
time during a simulation.
In D-latch, when E is inactive, the present value of Q is called the
current state and when E is active, the new value of Q is called the next
state Q+. The value of the next state depends on the value of the present
state and the value of the input D.
Truth Table:

Inputs Current
state
Next state
CLK D Q Q+
0 x 0 0
0 x 1 1
1 0 x 0
1 1 x 1

Procedure:
5)Give I/P and O/P ports
10) Configure device
12) Add .jeo and .bit files
13) Right click PROM and Erase and verify


Result:we can perform D-Latch using various VHDL styles of modeling

D-LATCH
library IEEE;




entity dlatch is

Port ( D : in std_logic;

En : in std_logic;

Q : inout std_logic);

end dlatch;

architecture Dataflow of dlatch is

signal s1,s2,s3,Qbar:std_logic;

begin

s1<=not En;

s2<=D and En;

s3<=s1 and Q;

Qbar<=s2 nor s3;

Q<=not Q;

end Dataflow;




TITLE: Write a VHDL code for SR-latch.

OBJECTIVE: To understand various statements such as wait, if ,loop
etc.To understand the concept of Delta delay

Requirement:
3. CPLD kit.
Theory:Delta Delay: Delta delay is very small delay .This delay models
hardware where a minimal amount of time is needed for a change to
occur. It allows for ordering of events that occur at the same simulation
time during a simulation.
SR-latch is a sequential circuit. It memorizes one of its state when
S=R=0. Memorization is achieved through feedback between the outputs
Q and its complement Qbar, and the inputs. The state where S=R=1 is
prohibited, since it may lead to unstable output.
Excitation Table:
Inputs Current
state
Next state
S R Q Q+
1 0 x 1
0 1 x 0
0 0 q q
1 1 x prohibited
Procedure:
10) Configure device
12) Add .jeo and .bit files
13) Right click PROM and Erase and verify

Result:We can perform SR-Latch using dataflow style of modeling


SR-LATCH
library IEEE;




entity srlatch is

Port ( S : in std_logic;

R : in std_logic;

Q : inout std_logic;

Qbar : inout std_logic);

end srlatch;

architecture Dataflow of srlatch is

begin

Q<=R nor Qbar;

Qbar<=S nor Q;

end Dataflow;




TITLE: Write VHDL code to describe functions of 4:1 Multiplexer.


Requirement:
1. Xilinx navigator
2. FPGA
3. CPLD kit.

Theory:
Multiplexer has many inputs and one output. 4:1 multiplexer
has four inputs and one output.

Procedure:


Result: We can perform 4:1 Multiplexer using various modeling styles in
VHDL



MULTIPLEXER
library IEEE;




entity MUX is

Port ( i : in std_logic_vector(3 down to 0);

o : out std_logic;

s : in std_logic_vector(1 down to 0));

end MUX;

architecture Behavioral of MUX is

begin
case s is,

when"00"=>o<=i0;

when "01"=>o<=i1;

when "10"=>o<=i2;

when others=>o<=i3;

end case;

end Behavioral;




TITLE: Write VHDL code for 2:4 Decoder.


Requirement:
1. Xilinx navigator
2. FPGA
3. CPLD kit.

Theory:
A decoder is a combinational circuit. A 2:4 decoder has two
inputs and four outputs. For any input, only one output is active; all
others are inactive. For an active-high output decoder, only one output is
high. The output can be deactivated or put in high impedance if the
decoder has enable.

Procedure:


Result: We can perform 2:4 Decoder using various modeling styles in
VHDL

\


2:4 DECODER
library IEEE;



entity decoder is

Port ( I1 : in std_logic;

I2 : in std_logic;

E : in std_logic;

O1 : out std_logic;

O2 : out std_logic;

O3 : out std_logic;

O4 : out std_logic);

end decoder;

architecture Dataflow of decoder is

signal I1bar, I2bar:std_logic;

begin

I1bar<=not I1;

I2bar<=not I2;

O1<=(I2bar and I1bar) and E;

O2<=(I1bar and I2) and E;

O3<=(I1 and I2bar) and E;

O4<=(I1 and I2) and E;


end Dataflow;


TITLE: Write VHDL code for 3-bit UP/DOWN counter.


Requirement:
1. Xilinx navigator
2. FPGA
3. CPLD kit.

Theory:
Counters are sequential circuits. For up counters, the next
state is the increment of the present state. For example, if the present
state is 101, then the next state is 110.For down counters; the next state
is the decrement of the present state. For example, if the present state is
101, then the next state is 100. A 3-bit binary up counter count from 0 to
7 (mod 8). Deacde counter count from 0 to 9 (mod 10). Synchronous
clear means that clear reset the counter when the clock is active; on
contrast, asynchronous clear reset the counter instantaneously.

Procedure:


Result:
We can perform 3-bit UP/DOWN counter using various modeling
styles in VHDL .



4 BIT UP COUNTER

library IEEE;




entity counter is

Port ( clk : in std_logic;

clr : in std_logic;

Q : out std_logic_vector(3 downto 0));

end counter;

architecture Behavioral of counter is

signal counter:std_logic_vector(3 downto 0);

begin

process(clk,clr)

begin

counter<="0000";

if(clk='1')then

if(clr='1')then

counter<="0000";

else if(clr='0')then


counter<=counter+1;

else if(counter="1111")then

counter<="0000";

else

counter<="0000";

end if;

end if;

end if;

end if;

end process;

Q<=counter;

end Behavioral;




TITLE: Write VHDL code for 8-bit ALU.

Requirement:
1. Xilinx navigator
2. FPGA
3. CPLD kit.

Theory:
Procedure:

Result:We perform the operations such as addition, subtraction,
multiplication, division etc. for 8-bit ALU using behavioral style of
modeling



ALU

library IEEE;




entity alu is

Port ( s : in std_logic(2 downto 0);

a : in std_logic(3 downto 0);

b : in std_logic(3 downto 0);

c : out std_logic;

f : out std_logic(3 downto 0));

end alu;

architecture Behavioral of alu is

begin

process(s)

begin

case s is

when "000"=>

f<="0000";

when "001"=>

f<=b-a;

when "010"=>

f<=a-b;

when "011"=>


f<=a+b;

when "100"=>

f<=a xor b;

when "101"=>

f<=a or b;

when "110"=>

f<=a and b;

when others=>

f<="1111";

end case;

end process;

end Behavioral;




TITLE : To study XILINX software.

THEORY:

Xilinx, Inc. (NASDAQ: XLNX) is the worlds largest supplier of
programmable logic devices, the inventor of the field programmable gate
array (FPGA) and the first semiconductor company with a flawless
manufacturing model. Founded in Silicon Valley in 1984 and
headquartered in San Jose, California, U.S.A.; Dublin, Ireland; Singapore;
and Tokyo, Japan, the company has corporate offices throughout North
America, Asia and Europe. The programmable logic device market has
been led by Xilinx since the late 1990s. Over the years, Xilinx has fueled
an aggressive expansion to India, Asia and Europe regions Xilinx
representatives have described as high-growth areas for the business.
Xilinxs sales rose from $560 million in 1996 to almost $2 billion by 2007.
The relatively new President and CEO Moshe Gavrielov an EDA and
ASIC industry veteran appointed in early 2008 aims to bolster the
companys revenue substantially during his tenure by providing more
complete solutions that align FPGAs with software, IP cores, boards and
kits to address focused target applications. The company aims to use this
approach to capture greater market share from application-specific
integrated circuits (ASICs) and application-specific standard products
(ASSPs).
The companys products have been recognized by EE Times, EDN and
others for innovation and market impact. The company has expanded its
product portfolio substantially since its founding, now selling a broad
range of FPGAs, complex programmable logic devices (CPLD), design
tools, intellectual property and reference designs. Xilinx also has a global
services and training program. The organizations most popular product
lines (see Current Family Lines) are the Spartan, Vertex and Easy Path
series, each including configurations and models optimized for different
applications.

Technology:
Xilinx designs, develops and markets programmable logic products
including integrated circuits (ICs), software design tools, predefined
system functions delivered as intellectual property (IP) cores, design
services, customer training, field engineering and technical support. Xilinx
sells both FPGAs and CPLDs programmable logic devices for electronic
equipment manufacturers in end markets such as communications,
industrial, consumer, automotive and data processing.

Current Family Lines :


Xilinx has two main FPGA families: the high-performance Vertex series
and the high-volume Spartan series, with a cheaper Easy Path option for
ramping to volume production. It also manufactures two CPLD lines, the
Cool Runner and the 9500 series. Each model series has been released in
multiple generations since its launch.

Spartan Family:
The Spartan series targets applications with a low-power footprint,
extreme cost sensitivity and high-volume such as displays, set-top boxes,
wireless routers and other applications. The Spartan-6 family is built on a
45-nanometer (nm), 9-metal layer, dual-oxide process technology. The
Spartan-6 was marketed in 2009 as a low-cost solution for automotive,
wireless communications, flat-panel display and video surveillance
applications. The Spartan-3A consumes more than 70-90 percent less
power in suspend mode and 40-50 percent less for static power compared
to standard devices. Also, the integration of dedicated DSP circuitry in the
Spartan series has inherent power advantages of approximately 25
percent over competing low-power FPGAs.

RESULT: XILINX software has been carefully studied.




AIM :To implement 2s complementor for 8 bit binary number using
behavioral.

THEORY:
A two's-complement system or two's-complement arithmetic is a
system in which negative numbers are represented by the two's
complement of the absolute value; this system is the most common
method of representing signed integers on computers. In such a system,
a number is negated (converted from positive to negative or vice versa)
by computing its two's complement. An N-bit two's-complement numeral
system can represent e
very integer in the range 2
N-1
to +2
N-1
-1.

Procedure:




VHDL PROGRAM:
library IEEE;
entity comple is
Port ( a : in STD_LOGIC_vector(7 down to 0);
b : out STD_LOGIC_vector(7 down to 0));
end comple;
architecture Behavioral of comple is
begin
process(a)
variable z: STD_LOGIC_vector(7 downto 0);
variable y: STD_LOGIC_vector(7 downto 0);
variable x: STD_LOGIC_vector(7 downto 0);
begin
z:="11111111";
y:="00000001";
x:=a xor z;
b<=x + y;
end process;
end Behavioral;

RESULT: The 2s complementor for 8 bit binary number has been
successfully designed and implemented on XILINX CPLD KIT.

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