Pradyumna Paliwal

IDD B. Tech. (Electronics & Communication

Engineering) and M. Tech. (Wireless Communication)
UG(V Year I Semester)
Registration No: IDD/ECW/10213012/2015
Email: pradyumn.paliwal@gmail.com
Indian Institute of Technology Roorkee
Area(s) of Interest: Communication Networks and Signal Processing,Image Processing,Machine
learning
Educational Qualifications Year Board/Institution CGPA* / %
IDD 4th Year 2014
Indian Institute of Technology,
Roorkee
9.314
Twelfth 2010
Ojaswini Excellence H.S.
School,Damoh[M.P.]
89.2
Tenth 2008
St.John's
sr.sec.school,Damoh[M.P.]
88.8
*on a scale of 10
INTERNSHIP INFORMATION
RWTH Aachen,Germany
SoC Bus Integration and Interfacing with a Host RISC Processor of Advanced CGRA (20 May
to 19 July 2013)
Mastered High Level Processor Designing with Synopsis Processor Designer in the LISA language.
Used Multi-Processor System-level Design tool in order to integrate the Coarse-grained
reconfigurable (CGRA) architecture into a SoC platform. The complete SoC was set up as a virtual
platform using mixed System-C,C++ and LISA components with the interconnects modeled in TLM
2.0 leading to a successful integration of all the necessary components.
PROJECTS
IIT Roorkee
Automatic Handwritten Signature Verification (June 2014 - Present)
In this Project I am implementing a signature verification system using image processing and pattern
recognition techniques. Aim is to build a signature based bio metric recognition system that provides
a reliable personal recognition scheme to either confirm or determine the identity of an individual.
IIT Roorkee
Highly Parallel Architecture for Variable Block Size Integer Motion Estimation (August 2013
-October 2013)
Designed a parallel architecture suitable for fast Block matching in images. Designed an efficient
parallel algorithm for Block matching motion estimation which is a very compute-intensive task and
takes a long time on sequential architectures and mapped it on the developed parallel architecture.
IIT Roorkee
Implementation of a basic 32-bit Multi-Cycle RISC processor in VHDL (Feb 2012-April 2012)
Implemented a 32-bit Multi-Cycle RISC processor with self-developed instruction set in VHDL.
IIT Roorkee
Design and simulation of a dual band power amplifier for mobile communication (May 2012 -
July 2012)
Designed a switch-less dual-band power-amplifier that uses dual-resonance input and load matching
passive networks for impedance transformation and harmonic termination.
SKILLS AND ACHIEVEMENTS
Computer Languages C, C++, Python, SystemC, VHDL, LISA
Software Packages MATLAB, GNU Octave, Synopsis Processor Designer
Academic Achievements Honda Young Engineer and Scientist Award 2012, US$ 3000 award
given by the Honda Foundation to 14 students from 8 affiliated IITs
for outstanding overall performance
IIT Roorkee Heritage Foundation Annual Excellence award 2012,
for extraordinary academic and extracurricular activities
German Academic Exchange Service (DAAD) scholarship 2013, for
carrying out research internship at RWTH Aachen University,
Germany
All India Rank 1495 in IIT-JEE 2010
Additional Courses Taken Computer Systems and Programming, Data Structures, Discrete
Mathematical Structures , Operations Research, Banking and Bank
Finance.
Languages Known English (SRW) , Hindi (SRW)
EXTRA CURRICULARS
Shrishti (IIT Roorkee) (2013)
Won 1st prize in FPGA Based Projects Annual exhibition of Electronics Section, Hobbies Club
Shrishti (IIT Roorkee) (2012)
Won 3rd prize in Image and Signal Processing Based Projects Annual exhibition of Electronics
Section, Hobbies Club
Shrishti (IIT Roorkee) (2012)
Coordinated Hands free gaming workshop
Cognizance (2012)
Participated in Ideaz Communication during Cognizance 2012
Texas Instruments India University Program (2012-2013)
Project shortlisted for Phase 1 of TI Analog Design Contest 2012-2013
PERSONAL DETAILS
Father's Name: Vipin Paliwal
Date of Birth: June 9, 1992
Gender: Male
Contact No: 8126587561
Category: General
Permanent Address: Paliwal complex,Near
state bank,Killai naka, Damoh - 470661
Current Address: BF-16, Govind Bhawan, IIT
Roorkee-247667
REFERENCES
Dr.M.V.Kartikeyan
Head of Department,Department of Electronics
and Computer Engineering
IIT Roorkee
kartkfec@iitr.ernet.in
+91-1332-285727
Dr. Anupam Chattopadhyay
Junior Professor,UMIC Research Centre
RWTH Aachen University
chattopadhyay@umic.rwth-aachen.de
+49-241/8020739