Documente Academic
Documente Profesional
Documente Cultură
DRM064
Rev. 0
09/2004
freescale.com
Revision History
Date
Revision
Level
09/2004
Description
Initial release
Page
Number(s)
N/A
Freescale Semiconductor
Contents
Chapter 1
Introduction
1.1
1.2
1.2.1
1.2.2
1.2.3
1.3
Application Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The UPS Topologies and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Passive Standby UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line-Interactive UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Line UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC9S12E128 Advantages and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
15
16
17
Chapter 2
System Description
2.1
2.2
System Concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
System Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 3
UPS Control
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
Control Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Battery Charger Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Factor Correction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
dc/dc Step-Up Converter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inverter Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PI and PID Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase-Locked Loop (PLL) Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
27
28
30
32
33
Chapter 4
Hardware Design
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.3
4.3.1
4.4
4.4.1
4.4.2
4.5
System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Battery Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Battery Charger Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flyback Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design of Flyback Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage and Current Sensing, Current Limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Line Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Battery Charger Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auxiliary Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auxiliary SMPS Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
dc/dc Step-Up Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
dc/dc Converter Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
dc/dc Converter Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Factor Correction and Output Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
36
36
37
39
39
41
41
41
42
45
47
47
50
61
Contents
4.5.1
4.5.2
4.5.3
4.5.4
61
64
68
71
Chapter 5
Software Design
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.2.10
5.2.11
5.2.12
5.2.13
5.2.14
5.2.15
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.4
5.4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Variables and Defined Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process PLL Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process RMS Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process Mains Line Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process Ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process Sine Wave Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process Button Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process LED Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process Application State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process PFC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process Sine Wave Reference (PFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process dc Bus Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process dc/dc Step-Up Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process Inverter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process Battery Charge Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Software Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization of Peripherals and Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Periodic Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Event Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Time Execution and MCU Load Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Constant Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PI and PID Controller Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
73
73
73
76
76
76
76
76
76
76
76
77
78
78
78
78
78
78
78
80
83
83
85
85
Chapter 6
Tests and Measurements
6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
Test Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overall Efficiency at Linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overall Efficiency at Non-linear Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Frequency Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage THD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Factor Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Response on Step Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
87
88
88
89
90
91
92
92
95
Freescale Semiconductor
Chapter 7
System Set-Up and Operation
7.1
7.1.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.3.1
7.3.2
7.3.3
Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Setting of Mains Line System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Software Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Application Software Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Application PC Master Software Control Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Application Build. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Programming the MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Application Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
On-line Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Battery Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Remote Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Appendix A. Schematics
A.1
A.2
A.3
A.4
A.5
A.6
105
115
117
119
123
124
Appendix B. References
Appendix C. Glossary
Contents
Freescale Semiconductor
Figures
1-1
1-2
1-3
2-1
2-2
2-3
2-4
2-5
2-6
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
5-1
14
15
16
19
20
20
21
21
22
26
27
28
28
29
30
31
31
32
34
35
36
38
40
41
42
44
47
48
49
51
53
54
55
56
58
59
61
62
63
69
70
74
Figures
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
Freescale Semiconductor
Tables
2-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
5-1
5-2
5-3
6-1
A-1
A-2
A-3
11
Tables
Freescale Semiconductor
Chapter 1
Introduction
1.1 Application Outline
This reference design describes the design of a single phase on-line uninterruptable power supply (UPS).
UPSs are used to protect sensitive electrical equipment such as computers, workstations, servers, and
other power-sensitive systems.
This reference design focuses on the digital control of key parts of the UPS system. It includes control of
a power factor correction (PFC), a dc/dc step-up converter, a battery charger, and an output inverter. The
dc/dc converter and the output inverter are fully digitally controlled. The PFC and the battery charger are
implemented by a mixed approach, where an MCU controls the signals for PFC current and battery
current demands. The digital control is based on Freescale Semiconductors MC9S12E128
microcontroller, which is intended for UPS applications.
The reference design incorporates both hardware and software parts of the system including hardware
schematics.
NOTE
Although specific tools, suppliers, and methods are mentioned in this
document, Freescale Semiconductor does not recommend or endorse any
particular methodology, tool, or vendor.
13
Introduction
LINE FILTER
BATTERY
CHARGER
AC
=
DC
=
DC
SWITCH
AC
INVERTER
Normal operation
Backup operation
BATTERY
Freescale Semiconductor
BYPASS
AVR
LINE FILTER
BATTERY
CHARGER
AC
=
DC
=
DC
AC
SWITCH
INVERTER
+
Normal operation
Backup operation
BATTERY
15
Introduction
BYPASS
RECTIFIER
PFC
IN
DC
=
BATTERY
CHARGER
OUT
AC
AC
DC
=
=
DC
INVERTER
=
DC
DC-DC
CONVERTER
Normal operation
Backup operation
BATTERY
Freescale Semiconductor
17
Introduction
Freescale Semiconductor
Chapter 2
System Description
2.1 System Concept
The system concept of the UPS is shown in Figure 2-1. Input consists of a rectifier (D1, D5) and a power
factor correction (L1, D2, Q2). The power factor correction is controlled by a mixed approach. The dc-bus
voltage control loop of PFC is controlled by the MCU. The output of the voltage controller defines the
amplitude of the input current. Based on the required amplitude, the MCU generates a current reference
signal. The current reference signal inputs to an external logic, which performs current controller working
in hysteresis mode.
DC-AC
PFC
L1
D1
D2
KBU8J
IN
Q1
Q2
D3
C1
IN
C2
+
Q3
D4
GND
OUT
D5
Filter
OUT
DC-DC Converter
D6
D7
L2
D8
L3
Q4
T1
GND
Q5
Charger
(Flyback
Converter)
BT1
GND
D9
GND
19
System Description
The battery BT1 supplies a load during the backup mode. There are two 12-V batteries connected in
serial. The battery voltage level 24-V is converted to 390-V by the dc/dc step-up converter (Q4, Q5,
D6-D9, L2, L3, and T1) using a push-pull topology fully controlled by the MCU.
The last part of a UPS is a battery charger. The battery charger maintains a fully charged battery. It uses
a flyback topology controlled by a mixed approach. The flyback converter is controlled by a dedicated
circuit and the required output voltage and current limit are set by the MCU. A dedicated circuit is used
due to the lower cost compared to direct MCU control. Where a different battery charger topology is used,
there is still enough MCU power to provide digital control.
Freescale Semiconductor
System Concept
Figure 2-4 shows the user interface PCB. It includes two buttons (ON/OFF, BYPASS), four status LEDs
(on-line, on-battery, bypass, and error), and six LEDs indicating output power or remaining battery
capacity. There are also two serial RS232 ports, which can used for communication with the PC. The user
interface provides an extension of the serial ports, which are implemented on the MC9S12E128 controller
board.
21
System Description
Figure 2-5 shows a controller board for the MC9S12E128. The MC9S12E128 controller board is designed
as a versatile development card for developing real-time software and hardware products to support a
new generation of applications in UPS, servo and motor control, and many others.
The power of the 16-bit MC9S12E128, combined with Hall-effect/quadrature encoder interface, circuitry
for automatic current profiling, over-current logic and over-voltage logic, and two isolated RS232
interfaces, makes the MC9S12E128 controller board ideal for developing and implementing many motor
controlling algorithms, UPS, SMPS, as well as for learning the architecture and instruction set of the
MC9S12E128 processor.
For more detailed information on the MC9S12E128 controller board, see [33].
An overall view of the assembled UPS is shown in Figure 2-6.
Freescale Semiconductor
System Specification
Parameters
Single Phase On-Line UPS using MC9S12E128
The UPS should be a regenerative 1-phase online type UPS with an automatic bypass
feature when self check fails or is overloaded. The UPS is controlled manually from a front
panel switch and from PC application software.
On-line: If the input power is available, the UPS supplies a load and eliminates all possible
defects on the line (online double conversion)
Battery: If the input power is not available, the UPS supplies a load from batteries. The
backup time is given by battery capacity.
Functional Modes
Bypass: The UPS directly connects its output and input, so the load is directly connected to
the input line. The transition to this mode is set manually or automatically during overload or
fault
Fault: If any fault is detected, the UPS signals fault, and if it is possible, the bypass is
activated.
45 to 65 Hz Operating Frequency Range
120 V (at 25% of load) 280 V Operating Voltage Range for nominal mains 230 V
Input
Output
Battery
Communication
Battery 2*12 V
Battery 7.2 Ah
2x RS232 port for communication with host PC with opto-isolation implemented on
MC9S12E128 Controller Board
4 LED indicators (on-line, battery, bypass, fault)
Visual Interface
Control Interface
Audible warning
Overload
low battery
lasts 5 minute
Implementation
23
System Description
Freescale Semiconductor
Chapter 3
UPS Control
3.1 Control Techniques
Generally, a UPS consists of several different converters. So the control techniques differ with the
converter topologies used. The presented implementation of on-line UPS includes following topologies:
Battery charger: flyback converter (mixed control)
PFC: boost converter (mixed control)
dc/dc step up converter: push-pull converter (full digital control)
Output inverter: half bridge inverter (full digital control)
25
UPS Control
MC9S12E128
Output Voltage
PU7
Charging Current Limit
PWM10
yes
IBAT = Imax
no
Bulk mode
Set HV level
yes
Absorption mode
Set HV level
Float mode
Set LV level
Battery Voltage
AN03
AN02
Battery current
Freescale Semiconductor
Control Techniques
DA0
UREQ +
PI Controller
SIN REFERENCE
SINUS
GENERATION
IOC04
Zero Cross
PLL LOCK
FAULT1
FAULT0
F
I
L
T
E
R
Top DC Overvoltage
Bottom Overvoltage
AN07
AN08
27
UPS Control
Sine
Reference
Hysteresis
Levels
Input current
PWM 4
PWM 3
Freescale Semiconductor
Control Techniques
The control algorithm is depicted in Figure 3-5. Both dc bus voltages pass the digital filter, and their sum
is compared with the required value of the dc bus voltage. Based on the error, the PI controller sets the
desired duty cycle of the switching transistors.
During mains line operation, the required value of the dc bus is set to 720 V (2 x 360 V). Because the dc
bus is kept by the PFC at 780 V (2 x 390 V), the dc/dc converter is automatically switched off. In case of
mains failure, the dc bus voltage will start to fall. As soon as the voltage reaches the value 720 V, the
dc/dc converter is activated. At 720 V, there is still 20 V reserve in amplitude to generate a maximum
output voltage of 240 V RMS. As soon as the operation from batteries is recognized, the required value
of the dc bus voltage is increased back to 780 V.
The PI controller maintains the constant voltage on the dc bus independent of the load until the mains is
restored or the battery is fully discharged. If the battery is discharged, the UPS output is deactivated and
UPS stays in STANDBY ON BATTERY mode. After 1 minute, the UPS is switched off.
The PI controller constants were experimentally tuned in the same way as the PFC. The constants are
P = 39 and TI = 0.0033 s. The control loop is calculated every 1 ms.
MC9S12E128
PMF3
Output Transistors
UREQ
PMF4
+
-
PI Controller
FAULT1
FAULT0
+
+
F
I
L
T
E
R
Top DC Overvoltage
Bottom DC Overvoltage
AN07
AN08
29
UPS Control
+DCBUS
-DCBUS
Freescale Semiconductor
Control Techniques
31
UPS Control
(EQ 3-1)
(EQ 3-2)
(EQ 3-3)
1
u ( s ) = K e ( s ) + -------- e ( s ) + sT D e ( s )
sT I
(EQ 3-4)
To improve the response of the PID controller to noisy signals, the derivative portion is often replaced by
a derivative portion with filter:
sT D
sTD ------------------sT
1 + --------DN
(EQ 3-5)
For implementation of algorithms on MCU the equations EQ 3-3 and EQ 3-4 have to be expressed in
discrete time domain like:
u ( kh ) = P ( kh ) + I ( kh ) + D ( kh )
(EQ 3-6)
Freescale Semiconductor
Control Techniques
where
P ( kh ) = K e ( kh )
(EQ 3-7)
Kh
I ( kh ) = I ( kh h ) + ------- e ( kh )
TI
(EQ 3-8)
TD
KT D N
D ( kh ) = --------------------- D ( kh h ) --------------------- e ( kh h )
T D + Nh
T D + Nh
(EQ 3-9)
e ( kh ) = w ( kh ) m ( kh )
(EQ 3-10)
and
e(kh)
w(kh)
m(kh)
u(k)
P(kh)
I(kh)
D(kh)
TI
T, h
Sampling time
Controller gain
Time
Laplace variable
Filter constant
33
UPS Control
The PLL algorithm measures a period from last two zero crossing signals. Because calculation of the
phase increment to the sine wave table requires a division instruction EQ 3-11, the phase over one-half
period is calculated instead:
T
Phase Increment = 32767 ----------------Period
(EQ 3-11)
where
T
32767
Period
If phase increment just corresponds to the measured period we should get a phase of 180. If there is
some difference, the phase increment must be adjusted (see Figure 3-10). Based on the sign of the phase
difference, the phase increment is incremented or decremented by the value which is equal to the phase
difference multiplied by the PLL constant.
If the phase difference falls below some limit for last 20 periods, the PLL is locked to the line frequency
and a frequency locked status bit is set.
Actual Period
Zerocrossing
Signal
Actual
Phase
180
0
Actual Phase
Increment
Phase
Difference
Freescale Semiconductor
Chapter 4
Hardware Design
4.1 System Configuration
The single phase on-line UPS reference design is 750 VA UPS representing an on-line topology. The
UPS comprises four PCBs (power stage, user interface, input filter, and controller board). The power
stage together with the MC9S12E128 controller board is shown in Figure 1-2
35
Hardware Design
J101
PSH02_02P
J100
J104
J103
1
2
J102
+VBAT
-5V_TOP
GND_TOP
+15V_TOP
-5V_BOT
GND_BOT
+15V_BOT
+VBAT
GND_PFC
+15V_PFC
+5V_A
+5V_D
+15V
3
4
+5V_REF
1
2
GNDA
GND
/POWER_EN
POWER_EN
F101
Battery Charger
J105
L
N
F102
+5V_A
+5V_A
GNDA
GND
6.3A/fast
GNDA
/POWER_ON
GND
F100
+VBAT
-VBAT
+15V
+5V_D
+5V_A
+15V_TOP
-5V_TOP
-5V_BOT
GND_BOT
+15V_PFC
GNDA
VBAT
IBAT
J106
GND_TOP
+15V_BOT
GND
HV_BAT_LEVEL
IBAT_CONTROL
2A/fast
+VBAT
-VBAT
GND_PFC
+5V_REF
-5V_TOP
GND_TOP
+15V_TOP
-5V_BOT
GND_BOT
+15V_BOT
GND_PFC
+15V_PFC
+5V_A
+5V_D
+15V
L1
L2
N
PE
PE MH100
GNDA
GND
+5V_REF
PFC+Inverter
PE CONNECTION
PWM_TOP
PWM_BOT
J107
OUT1
OUT2
N_OUT
DCB_POS
DCB_NEG
RLY_IN
RLY_BYPASS
RLY_OUT1
RLY_OUT2
FAULT0
FAULT1
AD2
AD3
J108
FAN_PWM
V_DCB_TOP
V_DCB_BOT
V_IN
I_IN
V_OUT_TOP
V_OUT_BOT
I_OUT
TEMP
+5V_D
+5V_A
+15V
PWM10
PWM12
TIM14
TIM15
TIM16
TIM17
DIV1
DIV2
UNI-3 PFC_EN
PFC_ZC
GND
GNDA
GND
+5V_D
+5V_A
+15V
DA0
DA1
GNDA
J109
FAN+
FAN-
J110
1
2
AD1
AD4
UNI-3_PWM2
AD5
UNI-3_PWM3
AD6
UNI-3_PWM4
UNI-3 PHAIS UNI-3_PWM5
UNI-3 PHCIS
UNI-3 DCBI UNI-3 PFC_EN
UNI-3 DCBV UNI-3 SERIAL
PSH02_02P
J111
1
2
PSH02_02P
UNI-3 BEMFZCA
UNI-3 BEMFZCC
UNI-3 BEMFZCB
UNI-3 PFC_ZC
DA0
DA1
Fault1
Fault0
DC-DC Step Up
GND
GNDA
GND
GNDA
+VBAT
-VBAT
+VBAT
-VBAT
DCB_POS
DCB_NEG
PWM4
PWM5
Freescale Semiconductor
Battery Charger
80 to 280 V / 50 to 60 Hz
Output voltage
High voltage level
Low voltage level
29.4 V
27.4 V
Max. value
Absorption - float threshold
1.8 A
0.36 A
Output current
NOTE
The output values are set to the values recommended by the battery
manufacturer. The current limits can be set to any value by SW.
37
C302
220uF/450V
D302
B250R
D303
P6KE200
C301
+
4.7nF
T300
1
R302
1M
R306
1M
R303
24k
D304
D305
BYV26C
+VBAT
47uH
LINE_OK
R301
68k
1N4148
TR02/MC145
29.4V @ Q4 ON
27.4V @ Q4 OFF
L300
13
TP300
Vbat
D301
BYW29E-200
R304
39k
C303
220uF/50V
100nF
C304
R305
1k8
220uF/50V
100u/50
+
R307
620
C306
C305
R309
2k4
5.05V @ 39V
VBAT
GND_TR
CONTROL
L301
47uH
TOP249Y
R300
0.1
ISO300
SFH615A-2
GND_CH
1
3
C316
100n
R315
7.5k
IBAT1
R329
1K
R313
27R
5 3
sense
U300
R312
200
D300
1N4148
S
-VBAT
GND
IBAT2
GNDA
R314
HV_BAT_LEVEL
100
+
C307
47uF/10V
C315
100n
Q301
MMBF0201NLT1
sense
R311
33k
R310
5K6
R308
3K6
R331
100
IBAT2
MC33502
U301B
7
3
2
+
-
100k
U301A
MC33502
220n
Q300
BC847
U302
TL431ACD
GND
C314
N/P
R323
1k
GND_CH
R326
3k9
IBAT
R324
1k
IBAT_CONTROL
LINE_OK
R327
560
C311
C310
470nF
GND
4.875V @ 2.34A
GND
R318
100K
R325
33K
GND_CH
C300
R320
R322
220
D309
5V1
100nF
C308
R319
1k6
R321
1k6
+5V_A
C309
470nF
IBAT1
R317
33K
R316
220
C312
D307
10nF/100V
BAV103
470nF
R328
C313
D308
BAV103
100nF/100V
GND
/POWER_ON
68K
D
R330
10k
GND
GND_TR
G
Q302 S
MMBF0201NLT1
GND
Battery Charger
80 to 280 V / 50 to 60 Hz
29.4 V
1.8 A
Switching frequency
66 kHz
The calculated parameters of the flyback transformer are specified in Table 4-3. The measured values on
the manufactured sample are listed in Table 4-4. To decrease leakage inductance, the interleaved
winding layout is used for the primary winding. The complete transformer winding layout is shown in
Figure 4-4.
39
Hardware Design
L4
L3
L2
L1
14
Core
L3
1pcs
1pcs
1pcs
2pcs
L1
(EPCOS components)
L4
L2
328 mH + 3 0 20%
31H + 30 20%
<3.5 H
Primary dc resistance
<0.1
Secondary dc resistance
<0.001
2.5k V ac
L [H]
@1kHz, 1V
L [H]
@100kHz, 1V
ESR [Ohm]
@100kHz, 1V
DCR [Ohm]
L [H] @100kHz, 1V
pin # 9 and 13 shorted
1-6
331.2
330.5
2.142
0.095
2.88
5-7
5.2
5.22
0.061
0.018
9-13
29.8
29.74
0.194
0.0005
Freescale Semiconductor
Battery Charger
41
Hardware Design
As the name of algorithm suggests, charging consists of three stages. The charging starts with the current
limit 0.25 of battery capacity. The battery charger works in current mode until the battery voltage reaches
the high level voltage (2.45 V/cell). This stage is called bulk charging. As soon as the battery voltage
reaches the high level, the current starts to fall, and the absorption stage begins. Once the battery current
falls under 0.05 of battery capacity, the battery charge voltage is set to the low level (2.28 V/cell). The last
stage is called the float stage.
NOTE
The voltage levels and current thresholds come from the battery
manufacturer. The values may also vary with the temperature if
temperature measurement is implemented.
U202
LM2575-5
R212
33k
TP204
+5V_D
+5V_D
L202
470uH
+VBAT
D
R213
C215
220uF/10V
C216
22uF/50V
D211
KA3528LSGT
100
GND
GND
U200
LM2575-15
GND
TP200
+15V
+15V
L203
680uH
D213
1N5819
12
R214
2.4k
R215
20K
GND
GND
C218
22uF/50V
Q200 S
MMBF0201NLT1
GND
POWER_EN
R200
510
D210
1N5819
/POWER_EN
R216
1.8K
D214
KA3528LSGT
C217
220uF/10V
GND
+15V
10uH
+
C219
22u/20V
GNDA
C221
100nF
U203
MC78L05ACP
VIN
VO
GND
L205
GND
GND
TP207
+5V_A
+5V_A
GND
GND
TP208
Vref
L200
+5V_REF
10uH
C200
100nF
GND
GNDA
+
C220
22u/20V
GNDA
Freescale Semiconductor
Supply voltages for the microcontroller and other digital circuits (+5V_D) are generated by U202. U200 is
used to stabilize +15V for the flyback converter, relays, dc/dc MOSFETs drivers, and cooling fans and it
is used as a down-converter for U203 in order to lower the power loss dissipated by U203. The IC supplies
5 V for op amps, comparators, and the heatsink temperature sensor. The output voltage is further filtered
and used as a reference for the signal and control circuits. In order to switch-on and switch-off all the
control and signal circuits, U200 and U202 are controllable by POWER_EN and /POWER_EN signals.
POWER_EN signal is driven by the microcontroller to control the switch-off process. /POWER_EN signal
is grounded when the ON button is depressed. All the power supplies are put into an operational state,
the micro starts to execute the program, and the POWER_EN signal is then put into the active state to
hold the supplies operational even when the button is released.
Figure 4-7 shows the isolated flyback converter schematic that provides the inverter and PFC drivers with
a power supply. MOSFET Q201 is driven by UC3843 in a classic current-mode configuration without the
feedback loop. The supply is designed to deliver constant power to the output while access power is
dissipated in zener diodes D202-D203, D206-D207, and D209 in case of drivers-in-standby. Respective
zener diodes are used specifically to split the secondary voltage to 5-V and 15-V levels.
43
C201
T1
R201
TP201
+15V_TOP
220
D201
100pF
12
+15V_TOP
LL4448
+15V
11
C204
L201
47nF
330u
R202
R203
15k
1
2
3
4
R206
8.2k
+ C206
330uF
U201
COMP
VFB
ISENSE
RT/CT
VREF
VCC
OUT
GND
R207
GND
GND
GND
GND
Q201
NTF3055
1k
C212
100pF
GND
GND_TOP
D203
BZV55/5V1
+
C203
100uF/10V
8z.
7
6z.
C208
100pF
R205
D205
TP202
+15V_BOT
220
+15V_BOT
LL4448
TR01/MC145
100pF
C213
-5V_BOT
LL4448
R211
TP203
+15V_PFC
220
D208
C214
220uF/25V
GND_PFC
TP211
GND_BOT
TP212
GND_BOT
D207
-5V_BOT
BZV55/5V1
+ C210
100uF/10V
100pF
D206
BZV55/15V
+ C207
220uF/25V
R210
1.8
GND
TP210
-5V_TOP
-5V_TOP
C205
6
R204
220
R209
C209
100nF
D1
33
C211
100pF
GND
MMBD914LT1
8
7
6
5
UC3843
R208
8.2k
GND
D204
15k
5z.
TP209
GND_TOP
D202
BZV55/15V
+ C202
220uF/25V
8z.
+15V_PFC
TP213
D209
GND_PFC
BZV55/15V
GND_PFC
(EQ 4-1)
t ON I P
Q = i dt = ---------------2
(EQ 4-2)
Because the voltage is equal, the equality of these charges also provides equal energies. When we
compare both equations, we get
P IN
t ON I 1P
-------- T = ------------------V IN
2
(EQ 4-3)
(EQ 4-4)
The peak secondary current for a 20-V output is calculated using EQ 4-6 (all the output power is
considered), and the secondary winding inductance L2 is then given by EQ 4-7.
V IN
15
L 1 = --------- dt = ------------- 1.5 = 38H
di
0.586
(EQ 4-5)
P OUT T
1.6 3.3
I 1P = 2 ------------- ---------- = 2 ------- ----------- = 293mA
20 1.8
V OU T t O FF
(EQ 4-6)
V OU T
20
L 2 = ------------- dt = ------------- 1.8 = 123H
di
0.293
(EQ 4-7)
45
Hardware Design
Lets choose a RM8 core made from N97 ferrite material, with Ae = 64mm 2 and AL = 3300 nH. Respective
winding turns are as follows:
N1 =
L
------P- =
AL
38
--------------- = 3.4 4t
3300n
(EQ 4-8)
N2 =
L
------S- =
AL
123
--------------- = 6.1 6t
3300n
(EQ 4-9)
(EQ 4-10)
For supplying the PFC driver, 15-V supply voltage is necessary and the turns ratio between both
secondaries is used to calculate the number of turns for the PFC driver.
15
15
N 4 = ------ N 2 = ------ 6 = 4.5t
20
20
(EQ 4-11)
Rounding the number up or down would cause large unbalanced secondary voltages. Secondary turns
are then scaled to obtain appropriate secondary-to-secondary ratio. Afterwards, primary turns are also
altered. In this case, N2 = 8t gives exact value of N 4 = 6t as follows:
15
15
N 4 = ------ N 2 = ------ 8 = 6t
20
20
(EQ 4-12)
(EQ 4-13)
To maintain a discontinued conduction mode, the switching frequency has to be also altered to the value
of 200 kHz. And the maximum flux has to be checked - simulation shows flux of amplitude 160 mT.
Figure 4-8 shows the layout of the windings on the transformer bobbin.
Freescale Semiconductor
L4
L3
L2
L1
Core
Coil former
Clamp
RM8 N97
12
L3
L2
L1
L4
B65811-J-R97
B65812-C1512-T1
B65812-A2203
1set
1pcs
2pcs
(EPCOS components)
Figure 4-8. Flyback Power Transformer Layout of Windings
Value
24 V
21 V
30 V
+390 V -390 V
+350 V -350 V
580 W
0.74 A
27 A
Switching frequency
50 kHz
47
L501
+Bat
MUR180
1
2
FFPF05U120STU
D500
680u/50V
1
D504
D505
10
L503
330u
MC33152D
NC
OutA
2 InA
R505
R506
47uF
C510
C508
1n
GND_BAT
100n
C500
GND_BAT
GND_BAT
Q501 Q500
NTP45N06 NTP45N06
D
D
G
S
Q502 Q503
NTP45N06 NTP45N06
D
D
G
U501
8 NC
G1
R500
VCC
MC33152D
NC
7 OutA
InA
5 OutB
InB
TP502
PWM_5
10
S
1
R507
GND
GND
GND_BAT
GND_BAT
GND_BAT
GND_BAT
GND_BAT
PWM5
R509
10k
10
10
3
1
2
R508
10k
OutB
4 InB
L500
330u
C507
1n
GND_BAT
10
PWM4
R503
100R/1W
GND_BAT
VCC
T500
TR03/MC145
9
100n
C511
DCB_POS
+15V
GND_BAT
+OUT
650u/1A
C506
22n/400V
18
4
6
100R/1W
R504
2
D503 L502
FFPF05U120STU
47uF
C509
1
GND
13
15
FFPF05U120STU
+15V
U500
1 NC
MUR180
GND_BAT
TP501
PWM_4
FFPF05U120STU
D502
R502
1k/5W
680u/50V
680u/50V
R501
1k/5W
DCB_NEG
C501
22n/400V
-VBAT
-OUT
680u/50V
1
+VBAT
680u/50V 680u/50V
650u/1A
D501
1
The converter performance and features are analyzed by simulation with the model shown in Figure 4-10.
DC Bus
mur2100e/ON
L16
1
C5
D1
10p
L7
4700 2
R3
10u
10p
C4
R20
20n
D7
L10
20n
9.98m
K_Linear
COUPLING = 1
1
2
30.8u
L3
L1
L15
26.7n
2
30.8u
20n
V2
M3
20
R11 NTP45N06
L8
R4
10u
R7
20m
R15
L12
20n
0.5
R16
20n
R17
4700
C3
100
R10 M1
R23
L11
2n
2u
V1
R1
5m R14
Implementation = 1
2
2
23.2
L18
2n
2u
Inverter Model
C2
1n
1n
NTP45N06
M2
C10
10p
R19
1000
4700
D3
C6
10p
10p
mur2100e/ON
NTP45N06 NTP45N06
20
R12
L17
2
560u
mur2100e/ON
R9
0.3
Current Sensing
R13
20
V3
K K2
D1N4149
D12
K_Linear
COUPLING = 1
0
1
L20
1.6m
L19
80u
80m
2
R25
R27
D6
3
C11
5p
R26
1k
220
D1N4149
D9
R24
22
D1N4149
C12
10n
D10
D1N4149
D11
D1N4149
R6
2
50m
L14
20n
mur2100e/ON
D4
Implementation = 2
20
V5
22n
D8
1
R2
5m
M4
390
C8
2k
100
C1
50m
V4
R28
524meg
9.98m
26.7n
L21
22n
390
L6
L4
R5
C7
2k
1000
mur2100e/ON
R22
15n
1
1
C9
10p
R21
L2
L13
4700 2
L5
K K1
0.3
D2
R18
L9
0.5
R8
2
560u
R29
524meg
Hardware Design
The inverter is supplied by a set of a low-ESR capacitors, C502-C505 and C512-C513, to lower the
battery bus ripple current and hence the EMI signature of the converter input. Inverter MOSFETs
Q500-Q503 are driven by MC33152 drivers. MOSFETs drain voltage ringing is damped by RC cells
R504-C507 and R503-C508. Because of the voltage source character of the inverter, the rectifier has to
be a current type, which is why smoothing chokes L501 and L502 are used. Over voltage spikes across
the rectifier diodes, due to the diodes reverse-recovery and transformer leakage, are clamped by RCD
snubbers consisting of a R501- C501- D501 for the positive side, and R502 - C506 - D503 for the negative
side.
(EQ 4-14)
where
ui
induced voltage
number of turns
u i dt = N S B
(EQ 4-15)
where
Freescale Semiconductor
Initially, the magnetic charge has to be calculated. Since the induced voltage during an active part of the
converter operational cycle is constant and it equals the input voltage, the magnetic charge in the core is
given by EQ 4-16.
u i dt = V IN T
(EQ 4-16)
where
VIN
input voltage
u i dt = 24 0.45 20 10 = 216 Vs
(EQ 4-17)
Simulation results can also be used to obtain the magnetic charge. Figure 4-11 shows simulated
magnetizing voltage and magnetic charge. Magnetic charge is obtained by the time integral of the
magnetizing voltage. Peak-to-peak reading of the magnetic charge is 218 V.
Rearranging EQ 4-15, the number of primary turns can be calculated:
u dt
6
i
216 10
- = 3.12 t
--------------N1 =
= ---------------------------------S B 173 106 0.4
40V
100u
20V
0V
-100u
-20V
-200u
-40V
(EQ 4-18)
>>
-300u
15us
1
20us
V(L1:1,L1:2)
2
25us
S(V(L1:1,L1:2))
30us
35us
40us
45us
Time
51
Hardware Design
Lets choose 3 turns. However, the flux density travel B has to be checked:
u dt
6
i
216 10
- = 416 mT
B = -------------- = ----------------------------S N 1 173 106 3
(EQ 4-19)
From EPCOS Siferit N97 specification (FAL0625-W @60C), the core power loss is 10 W, indicating a
good core utilization. However, forced convection should be considered. The negative loss temperature
coefficient of the N97 material is advantageous since it contributes to a temperature stability of the core
(FAL0624-N).
Now, the number of turns of the secondaries can be calculated. For primary to secondary ratio and a
forward type of converter, equation EQ 4-20 is valid:
V OU T
p = ---------------------------------V IN MA X
(EQ 4-20)
For efficiency = 0.93 and maximum duty (MAX) = 0.98, EQ 4-20 yields
V OUT
350
p = ----------------------------------- = ------------------------------------ = 18.47
V IN MAX 21 0.93 0.97
(EQ 4-21)
Primary to secondary ratio is rounded to 18, and the secondary winding number of turns yields
N 2 = p N 1 = 18 3 = 54t
(EQ 4-22)
Once the winding turns are determined, the cross sectional area of a winding can be calculated. For the
ETD44 core, winding current density can be selected in the range 5-10A/mm 2. Let J = 8A/mm2. Primary
cross-sectional area is given by EQ 4-23
I
2
19.1
S 1 = ----1 = ---------- = 2.39 mm
J
8
(EQ 4-23)
where
1
nominal primary winding current obtained by integrating the square of the simulated
winding current (Figure 4-12).
Freescale Semiconductor
60A
915m
40A
910m
20A
905m
0A
900m
-20A
>>
895m
2.2965ms
2.3000ms
1
-I(R1)
2
2.3040ms
2.3080ms
S(I(R1)*I(R1))
2.3120ms
2.3160ms
2.3200ms
2.3240ms
2.3280ms
Time
(EQ 4-24)
where
2
nominal secondary winding current obtained by integrating the square of the simulated
winding current (Figure 4-13).
53
Hardware Design
1.5A
1.300m
1.0A
1.296m
0.5A
1.292m
-0.0A
1.288m
-0.5A
1.284m
-1.0A
1.280m
-1.5A
>>
1.276m
2.2965ms 2.3000ms
1
-I(R3)
2
2.3040ms
2.3080ms
S(I(R3)*I(R3))
2.3120ms
2.3160ms
2.3200ms
2.3240ms
2.3280ms
Time
(EQ 4-25)
In this case the best solution for the primary is the use of a copper foil. An ETD44 bobbin has a width of
30 mm. Because of the necessary creepage, the foil width is set to 25 mm. Based on the result of
EQ 4-23, the foil thickness yields 100 m and has excellent skin performance when compared with skin
depth at the current switching frequency.
From the result of EQ 4-24, the secondary winding wire diameter yields 0.338 mm. The nearest wire
diameter in production is 0.315mm. A wire with a larger diameter is not helpful any more because of the
increased ac resistance due to the skin effect.
The primary winding of the push-pull converter transformer uses a center-tapped windings as well as the
secondary windings. As the power transformer is a part of the push-pull converter, there are some
restrictions required, especially with respect to the leakage inductance. With inverter transistor turn-off,
the drain voltage in push-pull is not clamped by the circuit topology itself. For ideal case (zero leakage),
the drain voltage is clamped through the transformer coupling when the rectifier diodes are re-opened.
Freescale Semiconductor
60V
40V
20V
0V
9.458us
9.600us
V(M1:d)
V(M2:d)
9.800us
V(M3:g)
10.000us
V(M2:g)
10.200us
10.400us
10.600us
10.800us
Time
55
Hardware Design
L6
L5
L4
L3
L2
L1
18
Core
ETD44/22/15 N97 B66365-G-X197 2pcs
Coil former
B66366-B1018-T1 1pcs
Yoke
B66366-A2000
2pcs
10
L6
L2
L1
L4
(EPCOS components)
L5
L3
2.5mH+30-20%
Magnetizing inductance referred to the secondary
Magnetizing inductance referred to the primary
30H+30-20%
Total leakage inductance referred to the secondary
<20uH
Primary DC resistance
<1mOhm
Secondary DC resistance
<0.6Ohm
Test Voltage secondary-to-secondary and primary-to-secondary
2kV AC
Test Voltage primary-to-primary
150V AC
4.4.2.2 Inverter MOSFETs
As mentioned above, MOSFETs voltage rating is given by voltage spikes that can possibly occur during
MOSFET switch-off. Of course it depends on the input voltage, load conditions, and transformer
properties. For push-pull a number of twice the input voltage is usually sufficient. The current rating of the
MOSFETs (chip size) is always a compromise because a small chip has large RDS(ON) that causes high
conduction losses. On the other hand, a large chip has low RDS(ON), but the chip capacitances are higher,
and, in the case of hard-switched topologies, the energy stored in the capacitances is not recovered in
the switching process, but instead, energy is dissipated in the chip. This is especially the case in
applications where the supply voltage is greater than 200 V.
Single Phase On-Line UPS Using MC9S12E128
56
Freescale Semiconductor
The primary factor for chip selection are the effective drain current and the switching frequency. Then a
suitable device is selected. Power loss components are calculated and compared with the designed
maximum power loss per package.
Simulation results (Figure 4-12) show a value of 19.1 A (transistor and primary winding currents are the
same). Dynamically, a current level as high as 50 to 60 A is observed when a load transient occurs and
the regulator attempts to hold the output voltage level. Of course the transistor has to withstand such
conditions for a number of milliseconds.
A couple of ON Semis twin NTP45N06 could be a solution. RDS(ON) for the transistor is 26 m. If a single
NTP45N06 switches the current with an effective value of 19.1 A, conduction losses are as high as 9.5 W.
To lower the conduction losses and to ensure the transistor switching robustness in dynamic conditions,
lets consider the twin NTP45N06 which decrease overall conduction losses to the half (power loss per
package decreases to a quarter - 2.4 W). However, the switching and the capacitance losses have to be
considered, due to the increased overall chip area, and hence the overall chip capacitance.
Switching losses are given by EQ 4-26 (ref. [2]).
I SW
P SW = V D S ( Q G D + Q GS2 ) f SW -------IG
(EQ 4-26)
3 30
- = 0.72 W
P SW = 24 ( 3nC + 15nC ) 50 10 -----0.9
(EQ 4-27)
where
VDS
QGD
QGS2
fSW
switching frequency
ISW
IG
Note that VDS can reach a level close to 60V as depending on the particular duty cycle, input voltage, and
output load conditions. The same is true for ISW parameter, and the loss value can be impacted.
CAUTION
If the output load conditions or large transformer leakage cause over
voltage spikes at the drain and the maximum drain voltage is reached, the
voltage is clamped by MOSFET internal avalanche process (see
Figure 4-14 fourth wave oscillation on green waveform). If the energy of
the spikes is high enough, chip temperature will exceed the maximum limit
and the semiconductor structure is destroyed. Please always observe the
drain-to-source voltage when testing the prototype. If this is the case,
increase the MOSFET voltage class or redesign the power transformer in
order to decrease the leakage.
57
Hardware Design
Turn-on capacitance losses PCAP for the NTP45N06 are given by EQ 4-28.
1
2
P CAP = f SW W CAP = f SW --- C OSS ( EFF ) V D S
2
(EQ 4-28)
1
3
12
2
P CAP = 50 10 --- 380 10 60 = 34 mW
2
(EQ 4-29)
where
fSW
switching frequency
WCAP
COSS(EFF) =
The sum of the switching and the capacitance losses is less than 0.8W per transistor at nominal
conditions, resulting in 1.6 W for the single NTP45N06 solution and 3.2W for the twin solution. When all
the loss contributions are compared, prevalence of the conduction losses is clear. The twin NTP45N06
solution results in an overall loss of 3.2W per package (the conduction component is 2.4 W, the switching
component 0.8W). Therefore, the twin solution doesnt contribute significantly to lower a converter
efficiency. Power loss 3.2 W per package means moderate package utilization for TO220, with a good
power loss margin.
The power losses can also be calculated by simulation of the model. Figure 4-16 shows the MOSFET
instantaneous power and energy obtained by instantaneous power integration. The average power is
then calculated by the definition of the power - the energy loss referred to the switching period.
400W
8.04m
200W
8.00m
0W
7.96m
>>
-200W
7.92m
2.208ms
1
W(M3)
2.212ms
2
S(W(M3))
2.216ms
2.220ms
2.224ms
2.228ms
2.232ms
Time
Freescale Semiconductor
The use of a single transistor with a higher rated drain current is also possible, however, the copper lead
utilization is rather high even though manufacturers define the value around 75 A as a limit for TO220
package leads.
0.5KV
1.5A
1.0A
0V
0.5A
-0.5KV
0A
>>
-1.0KV
-0.5A
2.3075ms 2.3100ms
1
V(D1:1,D1:2)
2.3150ms
I(D1)
2.3200ms
2.3250ms
2.3300ms
Time
59
Hardware Design
(EQ 4-30)
0.98 10 10
L = [ ( 24 1.6 ) 18 390 ] ----------------------------------- = 583 H
0.3 0.74
(EQ 4-31)
where
VL
current ripple
VIN
VLOSS
VOUT
MAX
ri
IOUT
Filter choke performance is analyzed by simulation, and the results (Figure 4-18) verified a good design
procedure. Choke PCV2-564-02 from Coilcraft, with 560 H inductance and 2 A saturation current, is
chosen.
Freescale Semiconductor
800mA
1.0KV
400mA
0.5KV
0A
0V
-400mA
-0.5KV
-800mA
>>
-1.0KV
1.900ms
1
1.905ms
1.910ms
1.915ms
I(L16)
I(L17)
2
V(R3:2,R4:2)
1.920ms
1.925ms
1.930ms
1.935ms
1.940ms
Time
Value
Unit
80
V[r.m.s.]
270
V[r.m.s.]
390
525
2.3
A[r.m.s]
Switching frequency
30 to 60
kHz
61
I_IN1
I_IN2
Hardware Design
CT1
1:100
D604
DCB_POS
L505
L1
2.5mH
RHRP8120
D606
KBPC606
C603
C602
+
MKP10/22nF/630VDC
Q606
IRG4IBC20W
330uF/450V
GATE_PFC
GND_PFC
N
GND
C607
MKP10/22nF/630VDC
C608
330uF/450V
D608
DCB_NEG
RHRP8120
NOTE
Selecting whether the low hysteresis limit is taken from DA0 signal or from
the configurable voltage divider has to be done by resoldering the zero
resistors R666 and R667. If R666 is populated, the DA0 signal is selected.
If R667 is populated, the configurable divider is selected. By default R666
is populated and R667 is not.
Single Phase On-Line UPS Using MC9S12E128
62
Freescale Semiconductor
+5V_A
+5V_A
R657
33
100n
GNDA
3
4
R658
10k
U606A
V+
V-
R660
R659
10k
10k
R664
1.6k
GNDA
GNDA
C630
100n
R667
0
I_IN
C631
100n
V+
V-
GND
Q609 S
MMBF0201NLT1
LM339M
U606C
V+
V-
R669
10k
14
R670
10k
TP611
GND
PFC_CTRL
LM339M
PWM_PFC
+5V_D
12
100
U606B
R668
R666
DA0
100
12
R665
12
C629
100n
C628
100n
R661
470
R662
470
2
LM339M
100
+5V_D
R663
DA1
+5V_D
C627
GNDA
GNDA
GNDA
R671
4.7k
D
G
UNI-3 PFC_EN
Q610 S
MMBF0201NLT1
60%
All On 55%
R673
3.3k
75%
D
DIV1
GNDA
85%
R675
9.1k
GND
D
DIV2
Q611 S
MMBF0201NLT1
R674
10k
G
Q612 S
MMBF0201NLT1
GNDA
U601
GNDA
PWM_PFC
GND
+15V_PFC
5
HCPL3150
D609
C609
100nF
BAT42
R606
GATE_PFC
10
R607
100
D628
15V
GND_PFC
GND_PFC
Hardware Design
Pout max
- =
2 ---------------------V in min
525
2 ------------------------ = 4.2A
184 0.95
(EQ 4-32)
If we know the input current maximum value we can calculate a current ripple. We chose the current ripple
to be 15% of the input peak current. For the given peak current value it is:
I = I in max 0.15 = 0.645A
(EQ 4-33)
When the PFC switch is turned on, the following equation has to be met:
I
L 1 -------- = V in
T on
(EQ 4-34)
where
L1
Ton
Vin
(EQ 4-35)
When the PFC switch is turned off, the following equation has to be met:
I
L 1 --------- = V in V out
T off
(EQ 4-36)
where
Toff
Vout
output voltage
Freescale Semiconductor
(EQ 4-37)
(EQ 4-38)
Frequency is an inverse value of the period. The switching frequency of the PFC is then given by the
formula:
2
V out V i n V in
1
f sw = --- = -----------------------------------T
I L 1 V out
(EQ 4-39)
Switching losses of the IGBT transistor are proportional to the switching frequency. To maintain switching
losses within acceptable limits we have to design the input inductor L1 with respect to a maximum
switching frequency. From EQ 4-39, we can calculate the level of input voltage (Vin) when the switching
frequency reaches its maximum value. We get the maximum switching frequency at
V out
V in = --------2
(EQ 4-40)
If we substitute EQ 4-40 for EQ 4-39 we can solve the equation and find the value of the required input
inductance value for the given ripple current (I), output voltage (Vout) and maximum switching frequency
(fmax):
V out
L 1 = -------------------------4 I f max
(EQ 4-41)
(EQ 4-42)
To limit the maximum frequency at 60 kHz at ripple current 0.645 A, we choose the input PFC inductance
L1 = 2.5 mH.
65
Hardware Design
:
Value
Unit
2500
113
390
FREQUENCY
60
kHz
TEMPERATURE
55
TOROID
FULL WINDOW
CORE SHAPE
WINDING TYPE
We ran the calculation and got a list of suitable cores, that met our selection criteria. From the list we
selected core: T175-8/90. The software calculates all important data (number of turns, wire diameter,
losses, Rdc, Al, dimensions, etc.). For the selected core, the parameters are as follows:
Table 4-9. Design Parameters for Core P/N: T175-8/90
Parameter
Value
Unit
Al
48
nH
TURNS
287
WIRE
1.00
mm
FILL
38.9
Rdc
0.4971
Core Loss
0.28
Cu Loss
6.21
Temp. Rise
41.8
The core T175-8/90 meets all of our criteria, is an acceptable size, with moderate losses and good
linearity.
Freescale Semiconductor
The dc-bus capacitor is a storage of energy for output power factor circuit and feeds an output inverter.
The dc-bus voltage should be set above the peak at maximum r.m.s. input voltage. For input RMS voltage
Vin = 270 V, the peak voltage is Vin peak max = 381 V. To achieve good regulation of the dc-bus voltage,
the dc-bus voltage should be at least 10% above the peak at nominal r.m.s. input voltage, i.e. for
Vin nom = 230 V RMS: Vdc-bus min = 1.1x1.41x230 = 356 V. Having Vin peak max and Vdc-bus min, we can
determine the dc-bus nominal voltage. We chose Vdc-bus nom = 390 V.
The dc-bus capacitor voltage should at least be rated at 450 V dc.
If ac input is lost, it is desired that the dc-bus capacitor is large enough to hold up the dc-bus voltage at
value Vdc-bus hup, allowing the output inverter voltage to remain within specifications for a time T hup.
The maximum nominal output voltage is Vout nom = 230 V RMS. The dc-bus voltage has to be higher than
the output voltage peak value Vout peak = 325 V. The hold-up time we define as a half-period of the output
ac voltage frequency Thup = 10ms. The minimum dc-bus capacitor value can calculated:
I av T hup
C 0 = ----------------------------------------------------V dc busnom V outpeak
(EQ 4-43)
where
Iav is the average capacitor current during the drop from Vdc-bus nom to Vout peak.
The Iav current can be calculated according to the formula:
2P out
I a v = ------------------------------------------------------------- ( V dc busnom + V outpeak )
(EQ 4-44)
where
Pout is the inverter output power
is the inverter efficiency
We can enumerate equation EQ 4-44 and obtain:
2 525
I a v = ---------------------------------------- = 1.728A
0.85 ( 390 + 325 )
(EQ 4-45)
The minimum output capacitor value can be calculated if we enumerate formula EQ 4-43:
3
6
1.728 10 10
C 0 = --------------------------------------- = 266 10 F
390 325
(EQ 4-46)
(EQ 4-47)
Pout
525
I l oad = ------------------------------------------ = ------------------------------- = 0.792A
2 V dc busnom
2 390 0.85
(EQ 4-48)
67
Hardware Design
Value
Unit
BC Components (Vishay)
Catalogue Number
Rated Capacitance
330
Rated Voltage
450
V d.c.
ESR @ 100 Hz
300
2.19
Value
Unit
2x340
V[d.c.]
2x430
V[d.c.]
80 - 270
V [r.m.s.]
750
VA
3.3
A[r.m.s]
Switching frequency
20
kHz
1. Nominal output apparent power for nominal output voltage 230 V r.m.s.
Freescale Semiconductor
RE1
MZPA001
5 o
OUT1
o 4
3 o
+15V
RE2
MZPA001
D602
5 o
o 4
L2
3 o
+15V
RLY_OUT1
Q602 S
MMBF0201NLT1
GND
RE3
MZPA001
D603
D
R603
100
BAT42
RLY_BYPASS
BAT42
R602
5 o
OUT2
o 4
100
3 o
Q603 S
MMBF0201NLT1
GND
+15V
DCB_POS
D605
D
BAT42
R604
RLY_OUT2
C602
+
330uF/450V
GATE_TOP
Q604 S
MMBF0201NLT1
GND
Q605
HGTG10N120BND
V_OUT
L506
GND_TOP
5mH
2
6.8uF/400V
L507
TL34P
C604
1
3
3
4
C605
1
2
CT2
GND
I_OUT2
CS2106
I_OUT1
Q608
+
GATE_BOT
C608
330uF/450V
100
HGTG10N120BND
GND_BOT
DCB_NEG
PE
4.7nF/Y1
C606
4.7nF/Y1
N_OUT
Hardware Design
The power IGBTs Q605 and Q608 switch in a complementary manner (if Q605 is on, Q608 is off, and vice
versa). Using the power IGBTs, the dc-bus voltage is pulse-width modulated at 20kHz switching
frequency to obtain an output voltage with a low frequency a.c. component (50/60 Hz). The junction of
C602 and C608 is a zero-volts reference for the generated output waveform. The junction of the
capacitors is galvanically connected to the mains N-terminal and is labelled as system ground.
Switching pulses to gates Q605 and Q608 are generated by the dual IGBT gate opto-drive HCPL-315J
(U615). The opto-drive provides the circuitry with galvanic isolation between the MCU and each of the
IGBTs. Its topology is shown in the Figure 4-22. The IGBT gates are floating during the inverter operation
in a voltage range +/- 430 V dc. Each channel of the dual opto-drive IC is supplied from a galvanically
isolated voltage supply of +15V dc.
GATE_TOP
+15V_TOP
D611
D610
BAT42
PWM_TOP
C610
100nF
R608
BAT42
330
33
D625
5V
R610
100
D613
1
2
3
BAT42
PWM_BOT
D624
15V
R609
R611
6
7
8
330
U615
N/C
VCC1
ANODE1
VO1
CATHODE1 VEE1
16
15
14
ANODE2
VCC2
CATHODE2 VO2
N/C
VEE2
11
10
9
C632
100nF
GND_TOP
-5V_TOP
GATE_BOT
+15V_BOT
HCPL-315J
GND
GND_TOP
D612
C611
100nF
BAT42
D626
15V
R612
33
D627
5V
R613
100
C633
100nF
GND_BOT
GND_BOT
-5V_BOT
NOTE
Please note that during operation, the voltage on the power IGBTs is a sum
of the voltages on the dc-bus capacitors, i.e., it can reach up to
2 x 430 V = 960 V! The IGBTs must be rated for a collector-emitter voltage
of 1200 V.
Freescale Semiconductor
Value
6.8 F
Capacitance tolerance
20%
300V
630V
Rated temperature
105C
Safety class
71
Hardware Design
Value
Unit
5000
Maximum current
4.6
340
400
Frequency
20
kHz
Temperature
55
Core shape
Toroid
Full window
Winding type
NOTE
Note that we swapped the input and output peak voltage values in the
design parameters. In a real inverter, the dc voltage is the input parameter
and the ac voltage is the output parameter. To make an analogy with PFC,
we have to swap these parameters in the input table.
We ran the calculation and got a list of suitable cores that met our selection criteria. From the list we
selected core: T200-30B. The software calculates all important data (number of turns, wire diameter,
losses, Rdc, Al, dimensions, etc.). For the selected core, the parameters are as follows:
Table 4-14. Design Parameters for Core P/N: T175-8/90
Parameter
Value
Unit
Al
51
nH
Turns
388
Wire
1.00
MM.
Fill
38.5
Rdc
0.8868
Ohms
Core loss
1.46
Cu loss
9.38
Temperature rise
46.4
The core T200-30B meets all of our criteria, is an acceptable size, with moderate losses and low price.
Freescale Semiconductor
Chapter 5
Software Design
5.1 Introduction
This section describes the design of the software blocks for the UPS. The software is described in terms
of:
Data flow
Main software flowchart
State diagram
For more information on the control technique used, see Chapter 3 UPS Control.
73
counter_actual
Button
Processing
v_out_rms
PLL
Algorithm
phase_out
phase_pfc
phase_pfc_inc
amplitude_correction
phase_out_inc
Mains Line
Detection
RMS
Correction
v_dcb_req
buttonStatus
v_out_freq_detect
amplitude_ref
v_dcb[]
Application State
Machine
DC Bus
Scaling
Sine Wave
Reference
appState
Ramp
v_sin_ref
v_dcb[]
v_dcb_req_rmp
v_out
v_dcdc_req
Inverter
Control
PFC Control
LED
Processing
PWM_to_DCB_scale
V_bat
I_bat
Ramp
PWMB_duty_cycle
i_n_ref
Sine Wave
Reference
v_dcdc_req_rmp
v_dcdc_sum
DC/DC Step Up
Control
pfc_ref_h
PWMC_duty_cycle
Battery Charge
Control
BatState
Data Flow
Type
<Range>; [Scale]
Description
amp_ControllerPar
Structure
amplitude_correction
U16
amplitude_ref
U16
appState
enum
BatState
enum
counter_actual
U16
dcdc_duty
U16
i_bat
S16
i_out
S16
<-32768, 32767>;
[-13 A, 13 A]
i_out_rms
S16
<-32768, 32767>;
[-13 A, 13 A]
pfc_ref_h
U8
<0, 152>; [0 A, 5 A]
phase_diff
S16
<-32768, 32767>;
[-180, 180]
phase_measured
S16
<-32768, 32767>;
[-180, 180]
calculated phase
phase_out
S16
<-32768, 32767>;
[-180, 180]
phase_out_inc
U16
<33554, 58720>;
[40 Hz, 70 Hz]
phase_pfc
S16
<-32768, 32767>;
[-180, 180]
PWMB_duty_cycle
U16
PWMC_duty_cycle
U16
temperature
U16
v_bat
U16
<0, 1023>; [0 V, 39 V]
battery voltage
v_dcb[]
U16
dc bus voltage
v_dcdcControllerPar
Structure
v_in
U16
v_out
S16
<-19968, 19968>;
[-400 V, 400 V]
v_out_freq_detect
U16
<33554, 58720>;
[40 Hz, 70 Hz]
v_out_rms
U16
<-19968, 19968>;
[-400 V, 400 V]
v_pfcControlerPar
Structure
v_sine_ref
S16
<-19968, 19968>;
[-400 V, 400 V]
Type: S8 = signed 8-bit, U8 = unsigned 8-bit, S16 = signed 16-bit, U16 = unsigned 16-bit.
75
Software Design
Freescale Semiconductor
Data Flow
Run on line
Run on bypass
Error
UPS off
After RESET, the state machine enters into the Standby on battery state if the mains line is available.
Then if the user pushes the ON/OFF button, the state machine continues on to the Run on line state.
During mains line failure, the state machine goes to the Run on battery state. The state machine stays
there until the batteries are discharged, the user switches the UPS off, or the main line is restored. If the
batteries are discharged the state machine goes to the Standby on battery state. If the state machine
stays in this state one minute, the UPS is switched off (UPS state) to avoid total discharge of the batteries.
In the case of some fault, the state machine goes into the Error state.
If the state machine goes from one to another state, a respective transition function is called.
CPU RESET
INIT
STANDBY
BATTERY
STANDBY
ONLINE
RUN ON LINE
RUN
ON BATTERY
ERROR
RUN BYPASS
UPS OFF
77
Software Design
Freescale Semiconductor
Pulse-width modulator
Voltage regulator
Subsequently, the communication with the PC is initialized, and the program variables are set to default
values.
Then the program enters the never-ending loop providing the application state machine (see main
function listing below).
void main ()
{
InitPeripherals();
PCMaster_Config();
EnableInterrupts; /* enable interrupts to make this routine
interruptible
(defined int PCMaster-S12.h) */
PCMasterInit();
// init PCMaster functions
InitVariables();
while(1)
{
appStateFcn[appState]();
FanControl();
}
}
The structure of the background loop can also be seen in Figure 5-3.
RESET
Background loop
END
of Background loop
79
Software Design
Read samples
of slow ATD Conversion
Lost detection
of Line Zero Crossing
END
of Interrupt Service Routine
Freescale Semiconductor
While the fast ATD conversion is running the following tasks are performed:
Detection of missing zero crossing on the input line
Detection of input voltage polarity
RMS value calculation and output power calculation (multiplication and addition)
Generation of rectified sine waveform for the PFC
Generation of sine wave reference for the output inverter
The execution time for these tasks is shorter than the conversion time in a fast ATD conversion.
END
of Interrupt Service Routine
81
Software Design
TIM 0 ch 4 IC Interrupt
(Line Zero Crossing)
END
of Interrupt Service Routine
TIM 0 ch 5 OC Interrupt
(1 ms)
RMS correction
END
of Interrupt Service Routine
Freescale Semiconductor
TIM 0 ch 6 OC Interrupt
(50 ms)
Software timers
Battery charging
END
of Interrupt Service Routine
83
Software Design
Trace
PMF Reload Interrupt
Trace
ATD Complete Interrupt
Trace
1 ms Interrupt
Trace
50 ms
Execution
Time
50 s
15.8 s
50 s
14.2 s
8.3 ms or 10 ms
7.8 s
1 ms
50 s
1 ms
35.8 s
Name
Size in Bytes
FLASH
10087
RAM
2502
Stack
512
Freescale Semiconductor
(EQ 5-1)
To keep the maximal precision of calculation, the SCALE should be set in order to push the GAIN into the
upper half of the variable range.
Example:
Lets convert a constant 25 in U16 representation. The upper half of the U16 range is from 32768 to
65536. The get this constant to optimal range we set the SCALE to 5. Then the GAIN = 25 .
2(16-5) = 51200.
NOTE
Note that the SCALE is shared for all constants in the PI/PID controller. So
in case of a highly different order in the constants, a compromise has to be
made.
The controller implementation is explained in 3.1.5 PI and PID Controller. From EQ 3-7 results, the
proportional constant is equal to the gain of the system.
The integral constant of the controller can be expressed as:
Kh
------TI
(EQ 5-2)
where
TI
Sampling time
Controller gain
TD
kd1 = -------------------T D + Nh
KT D N
kd2 = -------------------T D + Nh
(EQ 5-3)
(EQ 5-4)
85
Software Design
where
h
Sampling time
TD
Filter constant
NOTE
The proportional constant of the output inverter controller is called q1 in the
software.
Example:
Lets have constants for the PFC controller. The PFC uses the PI controller, where the controller gain
K(P) = 100 and Integral time constant TI = 0.0016 s. The controller is calculated every 1 ms.
3
100 1 10
From EQ 5-2 we can calculate integral constant as: ------------------------------ = 6.25 .
0.0016
Since the scale is common for both constants, we choose SCALE = 8. Then we get a proportional gain
100 . 2(16-8) = 25600 and an integral gain 6.25 . 2(16-8) = 1600. In the source code we can see:
#define PFC_P_GAIN_BASE
#define PFC_I_GAIN_BASE
#define PFC_SCALE
25600
1600
8
Freescale Semiconductor
Chapter 6
Tests and Measurements
6.1 Test Equipment
All tests were done using the following equipment:
2x multimeter 34401A, Hewlett Packard
Scope TDS3014B, Tektronix
3-phase precision power meter LMG 310, Zimmer Electronic Systems
D1
D3
Rs
2.8
D2
C1
937 uF
P1
160
D4
87
Freescale Semiconductor
89
Freescale Semiconductor
Test Results
91
Freescale Semiconductor
Test Results
93
Freescale Semiconductor
Test Results
6.3.7 Summary
All measured parameters are summarized in Table 6-1
Table 6-1. Summary of Measured Parameters
Load
Parameter
Efficiency
Linear
Non-linear
91%
90%
0.4%
1%
5%
0.99
< 0.01%
95
Freescale Semiconductor
Chapter 7
System Set-Up and Operation
WARNING
This application operates in an environment that includes dangerous
voltages. The application includes batteries and dangerous voltage
may appear even if the application is not connected to the mains line.
An isolating transformer should be used during debugging. If an
isolating transformer is not used, power stage grounds and
oscilloscope grounds will be at different potentials, unless the
oscilloscope is floating. Note that probe grounds, such as in the case
of a floating oscilloscope, are subject to dangerous voltages. Take
note of the following points and recommendations
97
5.
If the mains line is available, the UPS will go into standby on-line mode. In this mode, the MCU
works and the batteries are charged, but the output is still switched off.
In the case of remote operation, run the FreeMaster software on the PC and load the project file,
UPS.pmp.
The UPS is ready for operation.
Freescale Semiconductor
MAINS LINE
SWITCH
OUTPUT
SECTION 2
OUTPUT
SECTION 1
MAIN LINE
INPUT
External Battery
Connector
Serial Ports
99
Freescale Semiconductor
Software Setup
101
Freescale Semiconductor
Application Control
ON/OFF
Button
Status
LEDs
LED Bargraph
Bypass
Button
103
Freescale Semiconductor
Application Control
Appendix A. Schematics
A.1 Schematics of Power Stage
105
J101
PSH02_02P
J100
J104
J103
1
2
J102
+VBAT
D
-5V_TOP
GND_TOP
+15V_TOP
-5V_BOT
GND_BOT
+15V_BOT
+VBAT
GND_PFC
+15V_PFC
+5V_A
+5V_D
+15V
/POWER_EN
POWER_EN
3
4
GNDA
GND
F101
1
2
+5V_REF
Battery Charger
J105
L
N
F102
+5V_A
+5V_A
GNDA
GND
6.3A/fast
GNDA
/POWER_ON
GND
F100
+VBAT
-VBAT
+15V
+5V_D
+5V_A
+15V_TOP
-5V_TOP
-5V_BOT
GND_BOT
+15V_PFC
GNDA
VBAT
IBAT
J106
GND_TOP
+15V_BOT
GND
HV_BAT_LEVEL
IBAT_CONTROL
2A/fast
+VBAT
-VBAT
GND_PFC
+5V_REF
-5V_TOP
GND_TOP
+15V_TOP
-5V_BOT
GND_BOT
+15V_BOT
GND_PFC
+15V_PFC
PE MH100
+5V_A
+5V_D
+15V
L1
L2
N
PE
GNDA
GND
+5V_REF
PFC+Inverter
PE CONNECTION
PWM_TOP
PWM_BOT
J108
FAN_PWM
OUT1
OUT2
N_OUT
DCB_POS
DCB_NEG
AD2
AD3
FAULT0
FAULT1
RLY_IN
RLY_BYPASS
RLY_OUT1
RLY_OUT2
V_DCB_TOP
V_DCB_BOT
V_IN
I_IN
V_OUT_TOP
V_OUT_BOT
I_OUT
TEMP
+5V_D
+5V_A
+15V
PWM10
PWM12
TIM14
TIM15
TIM16
TIM17
DIV1
DIV2
UNI-3 PFC_EN
PFC_ZC
GNDA
GND
+5V_D
+5V_A
+15V
DA0
DA1
GND
J107
GNDA
J109
FAN+
FAN-
J110
1
2
AD1
AD4
UNI-3_PWM2
AD5
UNI-3_PWM3
AD6
UNI-3_PWM4
UNI-3 PHAIS UNI-3_PWM5
UNI-3 PHCIS
UNI-3 DCBI UNI-3 PFC_EN
UNI-3 DCBV UNI-3 SERIAL
PSH02_02P
J111
1
2
PSH02_02P
UNI-3 BEMFZCA
UNI-3 BEMFZCC
UNI-3 BEMFZCB
UNI-3 PFC_ZC
DA0
DA1
DC-DC Step Up
Fault1
Fault0
GNDA
GND
GND
GNDA
+VBAT
-VBAT
+VBAT
-VBAT
DCB_POS
DCB_NEG
PWM4
PWM5
Pavel Grasblum
Author:
Size
Schematic Name: 00165_01
A3 Design File Name:
Rev
01
C201
T1
R201
TP201
+15V_TOP
220
D201
100pF
12
+15V_TOP
LL4448
8z.
1
+15V
11
C204
L201
47nF
330u
R202
R203
510R
1
2
3
4
R206
16K
+ C206
330uF/35V
COMP
VFB
ISENSE
RT/CT
MMBD914LT1
8
7
6
5
VREF
VCC
OUT
GND
R207
GND
GND
GND
GND
GND
R205
100pF
D205
TP202
+15V_BOT
220
+15V_BOT
LL4448
TR01/MC145
C208
C213
-5V_BOT
R211
TP203
+15V_PFC
220
D208
LL4448
+
GND_PFC
U202
LM2575-5
TP204
+5V_D
+5V_D
L202
470uH
R213
100
+5V_D
+15V
+15V
GND
GND
GND
GND
+15V_TOP
GND_TOP
GND_TOP
-5V_TOP
+5V_REF
+5V_D
+15V_TOP
GND
+15V_BOT
GND
-5V_TOP
+15V_BOT
GND_BOT
GND_BOT
U200
LM2575-ADJ
TP200
+15V
1
GND
GNDA
680uH
R216
1.8K
C217
220uF/35V
D214
KA3528LSGT
2
GND
L205
220uH
+
C219
22u/20V
GNDA
C221
100nF
U203
MC78L05ACP
VIN
VO
+15V
GND
GND
GND
GNDA
GND
TP207
+5V_A
+5V_A
GND
C200
100nF
GND
TP208
Vref
L200
+5V_REF
220uH
+15V_PFC
+15V_PFC
GND_PFC
12
C218
22uF/50V
1u
R214
2.4k
R215
20K
D213
MBRA140
-5V_BOT
L204
GNDA
-5V_BOT
L203
GND
+15V
POWER_EN
GND
+5V_REF
+5V_A
D211
KA3528LSGT
+5V_A
C215
220uF/35V
C216
22uF/50V
TP206
GND
R200
510
D210
MBRA140
/POWER_EN
Q200
BC846
GND_PFC
R212
33k
+15V_PFC
TP213
D209
GND_PFC
BZV55/15V
C214
100uF/16V
+
C220
22u/20V
GNDA
GND
GNDA
GROUND CONNECTION
TP211
GND_BOT
TP212
GND_BOT
D207
-5V_BOT
BZV55/5V1
+ C210
100uF/16V
100pF
+VBAT
D206
BZV55/15V
+ C207
100uF/16V
R210
1.8
GND
TP210
-5V_TOP
-5V_TOP
C205
6z.
100pF
C212
100pF
GND
C203
100uF/16V
1k
100nF
C211
100pF
Q201
NTF3055
GND_TOP
D203
BZV55/5V1
7
R204
220
D1
R209
C209
5z.
D
G
33
UC3843
R208
N/P
GND
D204
15k
U201
8z.
TP209
GND_TOP
D202
BZV55/15V
+ C202
100uF/16V
GND_PFC
C302
220uF/450V
D302
B250R
D303
P6KE200
C301
+
4.7nF
T300
L300
13
R302
1M
D305
BYV26C
R306
1M
+VBAT
R303
24k
D304
1N4148
TR02/MC145
C303
220uF/50V
100nF
220uF/50V
100u/50
+
+
C304
R305
1k8
+
R309
2k4
GND_TR
2
L
ISO300
SFH615A-2
GND_CH
1
R329
1K
R313
27R
5 3
IBAT1
VBAT
R310
5K6
C315
100n
Q301
MMBF0201NLT1
GND
IBAT2
GNDA
C307
47uF/10V
5.05V @ 39V
-VBAT
R314
HV_BAT_LEVEL
100
C316
100n
R315
7.5k
R307
620
47uH
CONTROL
TOP249Y
R300
0.1
L301
sense
sense
U300
R312
200
D300
1N4148
R304
39k
C306
C305
D
R311
33k
29.4V @ Q4 ON
27.4V @ Q4 OFF
47uH
LINE_OK
R301
68k
TP300
Vbat
D301
BYW29E-200
R308
3K6
R331
100
5
R321
1k6
C300
GND_CH
R318
100k
U301A
MC33502
100K
220n
Q300
BC847
U302
TL431ACD
GND
C314
N/P
R323
1k
GND_CH
R325
33K
470nF
GND
R324
1k
IBAT_CONTROL
C311
C310
4.875V @ 2.34A
GND
R320
R322
220
D309
5V1
100nF
C308
IBAT2
MC33502
U301B
IBAT1
+5V_A
C309
470nF
R319
1k6
R317
33K
R316
220
470nF
GND
IBAT
GND
+5V_A
+5V_A
LINE_OK
GND
R327
560
GND
C312
D307
10nF/100V
BAV103
100nF/100V
GNDA
GND_TR
/POWER_ON
68K
C313
D308
BAV103
GNDA
R328
D
R330
10k
G
Q302 S
MMBF0201NLT1
GND
Author:
Pavel Grasblum
Size
Schematic Name: Battery Charger
A3 Design File Name:
Modify Date:
Thursday, August 19, 2004
Copyright Motorola
2003
5
Rev
01
Sheet
4
10
of
POPI Status: Motorola General Business
1
GND
J401
GND
D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GNDA
UNI-3_PWM2
UNI-3_PWM3
UNI-3_PWM4
UNI-3_PWM5
GND
+5V_D
GNDA
+15V
UNI-3 DCBV
UNI-3 PHAIS
UNI-3 PHCIS
GNDA
+5V_A
+5V_A
+5V_D
+5V_D
+15V
+15V
UNI-3 PFC_ZC
UNI-3 BEMFZCB
GNDA
J402
GND
2
4
6
8
10
1
3
5
7
9
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND
+5V_D
GNDA
UNI-3 DCBI
GNDA
UNI-3 SERIAL
UNI-3 PFC_EN
UNI-3 BEMFZCA
UNI-3 BEMFZCC
C
UNI-3
Fault0
Fault1
J400
+5V
FAULTS HEADER
AD1
AD3
AD5
DA1
GNDA
2
4
6
8
10
12
14
1
3
5
7
9
11
13
AD2
AD4
AD6
DA0
+5V_A
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
1
3
5
7
9
11
13
15
17
19
21
23
25
PWM10
PWM12
TIM14
TIM15
TIM16
TIM17
+5V
Title
Author:
Pavel Grasblum
Size
Schematic Name: Control Board Interface
A
Design File Name:
Rev
01
of
5
10
Modify Date:
Sheet
Wednesday, October 01, 2003
Copyright Motorola
POPI Status: Motorola General Business
2003
5
L501
+Bat
MUR180
FFPF05U120STU
D500
680u/50V
1
D504
D505
10
L503
330u
OutA
GND_BAT
8
7
R505
10
5
L500
330u
R506
47uF
C510
C508
1n
GND_BAT
GND_BAT
Q501 Q500
NTP45N06 NTP45N06
D
D
G
S
Q502 Q503
NTP45N06 NTP45N06
D
D
G
G1
S
R500
U501
8 NC
MC33152D
VCC
NC
7 OutA
InA
5 OutB
InB
TP502
PWM_5
10
S
1
R507
GND_BAT
GND_BAT
GND_BAT
GND_BAT
TP503
GND_BAT
TP500 TP504
GND GNDA
GND_BAT
GND
GND
GND
GNDA
GNDA
GND
GND_BAT
PWM5
R509
10k
10
GND
GNDA
100n
C500
GND_BAT
10
R508
10k
OutB
4 InB
PWM4
R503
100R/1W
C507
1n
2 InA
T500
TR03/MC145
9
1
GND_BAT
MC33152D
VCC
NC
DCB_POS
+15V
GND_BAT
100n
C511
+OUT
650u/1A
C506
22n/400V
18
4
6
100R/1W
R504
2
D503 L502
FFPF05U120STU
47uF
C509
1
GND
13
15
FFPF05U120STU
+15V
TP501
PWM_4
MUR180
GND_BAT
U500
1 NC
FFPF05U120STU
D502
R502
1k/5W
680u/50V
680u/50V
R501
1k/5W
DCB_NEG
C501
22n/400V
-VBAT
-OUT
680u/50V
1
+VBAT
680u/50V 680u/50V
650u/1A
D501
1
+5V_REF
TP610
I_OUT1
R614
I_IN
130R
I_IN
R679
180
C612
10n
D619
MBR0540
U604B
MC33502D
R617
100k
D617
BZV55/5V1
2
3
R600
10
I_OUT
MC33502D
U604A
100n
GNDA
+ C614
22uF
GNDA
V_INP
C613
GNDA
TP600
I_OUT
D618
MBR0540
R678
180
GNDA
DCB_POS
+5V_A
GNDA
+5V_REF
D600
1N4007
+5V_REF
C616
100n
R619
300k
R620
11k
R618
330k
TP601
-DCB_DIV
GNDA
V_DCB_BOT_DIV
R625
300k
R622
470k
C
R631
130k
V_DCB_TOP_DIV
V_IN
R636
33K
TP603
+DCB_DIV
R632
TP602
R621
V_OUT_NEG
11k
R630
300k
V_DCB_TOP
V_OUT_BOT
R672
11K
GNDA
GNDA
GNDA
R634
300k
C620
33n
0R
D620
BZV55/3V6
R627
330k
C617
33n
R624
V_DCB_BOT
R629
300k
1K
R633
11k
+ C619
10uF/10V
R623
1K
R626
330k
R628
330k
TP604
V_IN
R616
180
I_IN2
D616
BZV55/5V1
GNDA
I_IN1
D615
MBR0540
R615
100k
D614
MBR0540
I_OUT2
R635
300k
V_OUT
R637
GNDA
GNDA
680k
DCB_NEG
GNDA
R638
300k
+5V_D
GNDA
+5V_D
R641
V_DCB_TOP_DIV
R642
10k
10k
C600
V_INP
R647
R648
330k
330k
330k
D622
BAT42
D623
BAT42
C621
15n
10
11
U606D
V+
V-
13
TP606
PFC_ZC
V_OUT_TOP
1K
D621
BAT42
C622
33n
GNDA
R651
680k
GND
1K
C625
33n
R680
33
C634
R653
100n
10K
+15V
+5V_D
C623
100n
TP609
REF_NEG
R655
10k
GNDA
GNDA
+5V_D
+15V
+5V_REF
+5V_REF
TEMP
+Vout
R652
+5V_A
+5V_D
2 1
+5V_A
+5V_A
TP608
TEMP
Q600
LM35CA
GNDA
GNDA
GNDA
+5V_REF
GNDA
R645
1
R649
11k
TP607
REF_POS
10K
+Vs
TP605
V_OUT_POS
GNDA
R650
C624
100n
R643
330k
+5V_REF
GNDA
FAULT1
PFC_ZC
LM339M
+5V_A
7
U605B
LM393D
100n
12
R646
R644
10k
R639
300k
R640
10k
GNDA
1
GND
R654
10k
GND
GNDA
FAULT0
U605A
LM393D
GNDA
A
GNDA
V_DCB_BOT_DIV
R656
10k
C626
100n
GNDA
Title
Pavel Grasblum
Author:
Size
Schematic Name:
A3 Design File Name:
GNDA
5
Rev
01
Analog_Sensing
Modify Date:
Monday, March 08, 2004
2003
Copyright Motorola
Sheet
7
10
of
Motorola General Business
POPI Status:
1
U601
PWM_PFC
GND
+15V_PFC
+15V_TOP
D609
C609
100nF
R606
MBR0540
R607
GATE_PFC
10
D628
15V
100
GND_TOP
GND_TOP
-5V_TOP
GND_PFC
HCPL3150
+15V_TOP
-5V_TOP
+15V_BOT
+15V_BOT
GND_PFC
GND_BOT
GATE_TOP
+15V_TOP
D611
C
D610
BAT42
PWM_TOP
C610
100nF
R608
330
R609
MBR0540
R610
33
1
2
3
BAT42
R611
6
7
8
330
U615
N/C
VCC1
ANODE1
VO1
CATHODE1 VEE1
16
15
14
ANODE2
VCC2
CATHODE2 VO2
N/C
VEE2
11
10
9
-5V_BOT
-5V_BOT
+15V_PFC
D625
5V
100
D613
PWM_BOT
D624
15V
GND_BOT
GND_PFC
GND_PFC
GND_TOP
C632
100nF
+15V_PFC
GND_TOP
GND
GND
-5V_TOP
GATE_BOT
+15V_BOT
HCPL-315J
D612
C611
100nF
GND
D626
15V
R612
MBR0540
R613
33
D627
5V
100
C633
100nF
GND_BOT
GND_BOT
-5V_BOT
Title
Author:
Pavel Grasblum
Size Schematic Name:
IGBT_Drives
Design File Name:
Modify Date: Monday, March 08, 2004
Sheet
of
8
10
Copyright Motorola
POPI Status: Motorola General Business
2003
A4
Rev
01
RE1
MZPA001
5 o
MBRS130
+15V
D601
L504
D
D
R601
FAN_PWM
D1
+ C601
10u/15V
3 o
FAN-
+15V
RE2
MZPA001
330u
D602
5 o
G
68
OUT1
o 4
FAN+
o 4
Q601
NTF3055
L2
GND
BAT42
3 o
+15V
R602
RLY_OUT1
Q602
BC846
4K7
GND
I_IN1
RE3
MZPA001
D603
I_IN2
BAT42
RLY_BYPASS
CT1
1:100
L505
+15V
3 o
GND
D604
2.5mH
+15V
BAT42
7
o
C602
+
C603
Q606
IRG4IBC20W
MKP10/22nF/630VDC
330uF/450V
GND
HGTG10N120BND
V_OUT
L506
GND_TOP
6mH
GATE_PFC
R605
Q607
BC846
4K7
GND_PFC
C605
3.3uF/400V
1
2
GND
N
RLY_IN
4K7
Q605
GATE_TOP
Q604
BC846
GND
L507
TL34P
C604
1
3
PE
4.7nF/Y1
C606
4.7nF/Y1
N_OUT
3
4
RE4
MZPA002
R604
RLY_OUT2
D607
BAT42
2
D605
RHRP8120
D606
KBPC606
DCB_POS
OUT2
o 4
Q603
BC846
4K7
V_INP
L1
DCB_POS
5 o
R603
CT2
GND
I_OUT2
I_OUT1
Q608
C607
+
MKP10/22nF/630VDC
CS2106
GATE_BOT
C608
330uF/450V
HGTG10N120BND
GND_BOT
D608
+15V
+15V
RHRP8120
GND
DCB_NEG
DCB_NEG
GND
Title
Pavel Grasblum
Author:
Size
Schematic Name:
A3 Design File Name:
Rev
01
Inverter
Modify Date:
Monday, March 08, 2004
2003
Copyright Motorola
9
10
Sheet
of
Motorola General Business
POPI Status:
1
+5V_A
+5V_A
R657
33
100n
GNDA
3
R663
100
DA1
R658
10k
U606A
V+
V-
R660
R659
10k
10k
R665
N/P
12
R664
1.6k
GNDA
GNDA
V+
V-
GND
Q609 S
MMBF0201NLT1
12
R667
0
I_IN
U606B
N/P
C630
N/P
R668
100
LM339M
R666
DA0
C628
100n
R661
470
R662
470
2
LM339M
C629
10n
+5V_D
+5V_D
C627
C631
10n
U606C
V+
V-
R669
10k
14
R670
10k
TP611
PFC_CTRL
LM339M
GND
PWM_PFC
12
+5V_D
GNDA
GNDA
MMBF0201NLT1
60%
3.3K
MMBF0201NLT1
75%
10k
85%
9.1k
GNDA
R671
4.7k
D
G
UNI-3 PFC_EN
Q610 S
MMBF0201NLT1
R673
N/P
R674
N/P
R675
N/P
GND
All On 55%
G
DIV1
Q611
N/P
D
G
DIV2
Q612
N/P
S
GNDA
S
GNDA
GNDA
Title
Author:
Ivan Feno
Size Schematic Name:
PFC_Control
Design File Name:
Modify Date: Monday, March 08, 2004
Sheet
of
10
10
Copyright Motorola
POPI Status: Motorola General Business
2003
A4
Rev
01
Application Control
115
+5V_D
LED_FAULT
SW1
R1
1300
R2
10k
D1
L53LID
BT_BYPASS
J1
LED_LEV5
LED_LEV3
LED_LEV1
BT_BYPASS
LED_BAT
LED_FAULT
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
1
3
5
7
9
11
13
15
17
19
21
23
25
GND
BEEP
LED_LEV6
LED_LEV4
LED_LEV2
Switch/P-0SYB
+5V_D
BT_ON/OFF
LED_BYPASS
LED_ON
J3
1
3
5
7
9
R4
10k
SW2
+5V_D
5
9
4
8
3
7
2
6
1
2
4
6
8
10
BT_ON/OFF
HEADER 5X2
HEADER 13x2
LED_ON
J2
R3
1300
D2
L53LGD
GND
LED_BAT
CON/CANNON9
R5
270
D3
L53ND
GND
2
1
Switch/P-0SEB
R6
LED_LEV1
R9
LED_LEV3
R10
LED_LEV4
R11
LED_LEV5
LED_LEV6
R12
GND
LED_BYPASS
J4
PSH02_02W
1300
R8
LED_LEV2
J6
1300
R7
1300
1300
1
3
5
7
9
1300
5
9
4
8
3
7
2
6
1
2
4
6
8
10
1300
HEADER 5X2
D4
L53LYD
J5
GND
BEEP
BZ1
CON/CANNON9
1300
D5
L53LID
D6
L53LGD
D7
L53LGD
D8
L53LGD
D9
L53LGD
SA003
D10
L53LID
GND
+5V_D
+5V_D
GND
GND
GND
GND
GND
GND
GND
GND
Title
Author:
Pavel Grasblum
Size Schematic Name: 00165B01
A4 Design File Name:
Rev
01
Application Control
117
R103
330k
SIOV-S20K275
4.7nF/Y1
J100
J101
C100
C100B
100nF/X1 1uF/X1
4
2
TL34P
L100
3
1
C101
R100
C102
R101
L_OUT
J104
N_OUT
MH1
PE
R102
SIOV-S20K275
100nF/X1
J103
SG-190
C103
4.7nF/Y1
PE
J102
GROUND CONNECTION
B
MH2
GROUND CONNECTION
Title
Author:
Pavel Grasblum
Size
Schematic Name: 00165C01
A
Design File Name:
Rev
01
2
2
of
Modify Date:
Sheet
Monday, September 15, 2003
Copyright Motorola
POPI Status: Motorola General Business
2003
2
Application Control
Qty
Description
Manufacturer
Part number
CT1
CT2
current transformer
COILCRAFT
any available
any available
any available
C204
any available
C206
any available
C215, C217
any available
C216, C218
22-F/50-V 5 x 11 mm
any available
C219, C220
any available
C300
any available
C301
4.7-nF polyester
Vishay
MKT1820
C302
220-F/450-V electrolytic
EPCOS
B43504
C304, C305
220-F/50-V electrolytic
Rubycon
ZL series
C306
100-/50-V electrolytic
Jamicon
C307
47-F/10-V electrolytic
Jamicon
any available
C312
10-nF/100-V ceramic
any available
C313
100-nF/100-V ceramic
any available
no populated
11
any available
C500, C511
any available
C501, C506
22n/400-V metallized
WIMA
MKP10
680/50-V
Rubycon
ZL series
C507, C508
1n/100-V
WIMA
MKS 2
C509, C510
any available
C601
any available
TRONIC
3044202
CS2106
C602, C608
330-F/450-V electrolytic
EPCOS
B43504
C603, C607
22-nF/630-Vdc
WIMA
MKP10
C604, C606
4.7-nF/Y1
any available
C605
3.3-F/400-V
WIMA
C609
any available
any available
C614
any available
MKP10
119
Qty
Description
Manufacturer
Part number
any available
C619
any available
C621
any available
D201,D205,D208, D304
Fairchild
LL4448
D202,D206,D209
Philips
BZV55/15V
D203,D207,D616,D617
Philips
BZV55/5V1
D204
ON Semiconductor
MMBD914LT1
D210,D213
schottky diode
ON Semiconductor
MBRA140
D211,D214
Kingbright
KA3528SGT
D300
high-speed diode
Philips
1N4148
D301
Vishay
BYW29E-200
bridge rectifier
Diotec
Semiconductor
B250R
D302
D303
Vishay
P6KE200
D305
Vishay
BYV26C
D307,D308
Philips
BAV103
D309
Philips
BZV55/5V1
D500,D502,D504,D505
Fairchild
FFPF05U120STU
D501,D503
ON Semiconductor
MUR180
D600
diode
Philips
1N4007
D601
schottky diode
ON Semiconductor
MBRS130
D602,D603,D605,D607,D611,D613,D62
9
1,D622,D623
schottky diode
Philips
BAT42
D604,D608
hyperfast diode
Fairchild
RHRP8120
bridge rectifier
Diotec
Semiconductor
KBPC606
D609,D610,D612,D614,D615,D618,D61
7
9
schottky diode
ON Semiconductor
MBR0540
D620
Philips
BZV55/3V6
D624,D626,D628
zener diode 15 V
Philips
BZV55/15V
BZV55/5V1
D606
D625,D627
Philips
F100
fast fuse 2 A
any available
F101
car fuse 40 A
any available
F102
any available
ISO300
optocupler
Vishay
SFH615A-2
PSH02_02P
J100,J102,J103,J104,J105,J106,J107,J
9
108,J109
FASTON
J101,J110,J111
connector
EZK (distributor)
J400
header 7 x 2
any available
J401
connector
EZK (distributor)
J402
header 5 x 2
any available
J403
header 13 x 2
any available
L200,L205
FASTRON
PFL_20X2
Freescale Semiconductor
Application Control
Qty
Description
Manufacturer
Part number
L201,L500,L503,L504
FASTRON
L202
470 H
FASTRON
09P/F-471k
L203
680 H
FASTRON
09P/F-681k
L204
FASTRON
L300,L301
radial inductor 47 H
Coilcraft
PCV-1-473-03
L501, L502
560 / 1 A
Coilcraft
PCV-2-564-02
L505
2.5 mH
custom design
see 4.5.2.1
L506
5 mH
custom design
see 4.5.4.2
L507
toroid choke
Tesla Blatna
TL34P
ON Semiconductor
BC846
Q201, Q601
ON Semiconductor
NTF3055
Q300
ON Semiconductor
BC847
ON Semiconductor
MMBF0201NLT1
ON Semiconductor
NTP45N06
LM35CA
Q600
temperature sensor
National
Semiconductor
Q605, Q608
IGBT
Fairchild
HGTG10N120BND
Q606
IGBT
International
Rectifier
IRG4IBC20W
Q611, Q612
no populated
relay
CARLO GAVAZZI
MZPA001
RE4
relay
CARLO GAVAZZI
MZPA002
R200, R203
any available
any available
R202
any available
R206
any available
33 SMD 0805
any available
1k SMD 0805
any available
R210
any available
any available
any available
R214
any available
R215
any available
R216
any available
R300
Isabellenhtte
Heusler GmbH KG
R301
68k, 2W
any available
R302, R306
1M size 0207
any available
R303
any available
R304
any available
R305
any available
R307
any available
R308
any available
PMA-C - R100 - 1
121
Qty
Description
Manufacturer
R309
R310
any available
R311, R636
any available
Part number
any available
R312
any available
R313
any available
R315
any available
any available
R319, R321
any available
R326
any available
R327
any available
R328
any available
15
any available
10 SMD 1206
any available
R501, R502
1-k/5-W
any available
R503, R504
100R/1W
any available
R600
10 SMD 0805
any available
R601
68 SMD 0805
any available
any available
any available
R608, R611
any available
R609, R612
33 SMD 1206
any available
R614
130RSMD 0805
any available
any available
any available
any available
any available
R622
any available
R624, R667
0R SMD 0805
any available
R631
any available
R637, R651
any available
R650, R653
any available
R661, R662
any available
R664
any available
R671
any available
T1
transformer
customer design
see 4.3.1
T300
transformer
customer design
see 4.2.4
T500
transformer
customer design
see 4.4.2.1
U200
switching regulator
ON Semiconductor
LM2575-ADJ
U201
switching regulator
ON Semiconductor
UC3843
U202
switching regulator
ON Semiconductor
LM2575-5
Freescale Semiconductor
Application Control
Qty
Description
Manufacturer
Part number
U203
linear regulator
ON Semiconductor
MC78L05ACP
U300
switching regulator
Power Integrations
TOP249Y
U301, U604
operational amplifier
ON Semiconductor
MC33502
U302
voltage reference
Fairchild
TL431ACD
U500,U501
MOSFET driver
ON Semiconductor
MC33152D
U601
opto driver
Agilent
HCPL3150
U605
dual comparators
ON Semiconductor
LM393D
U606
quad comparators
ON Semiconductor
LM339M
U615
opto driver
Agilent
HCPL-315J
Qty
Description
buzzer
Manufacturer
EZK (distributor)
Part number
BZ1
SA003
D1, D10
Kingbright
L53LID
D2,D5,D6,D7,D8,D9
Kingbright
L53LGD
D3
Kingbright
L53ND
D4
Kingbright
L53LYD
J1
header 13 x 2
any available
J2,J5
any available
J3,J6
header 5 x 2
any available
J4
connector
any available
any available
R2, R4
any available
R5
any available
SW1
Switch
MEC
switch 15501
extender 16250
cap 1D06
SW2
Switch
MEC
switch 15501
extender 16250
cap 1D02
123
Qty
1
Description
1F / X1
Manufacturer
EPCOS
Part number
B81133
C100, C101
100-nF / X1
EPCOS
B81133
C102, C103
4.7-nF / Y1
MURATA
DE2E3KH472MA3B
J100,J101,J102,J103,J104
faston 6.3 mm
any available
L100
toroid choke
Tesla Blatna
TL34P
R100
Rhopoint
Components
SG-190
R101, R102
EPCOS
SIOV-S20K275
R103
330k, 0.6 W
any available
Freescale Semiconductor
Application Control
Appendix B. References
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
Feno, I.: Analysis and Synthesis of the IGBT switching techniques and verification in Partial Series
Resonant Converter. Ph.D. Dissertation, University of Zilina, Faculty of Electrical Engineering,
August 2003.
A More Realistic Characterization Of Power MOSFET Output Capacitance Coss. Application Note
AN-1001, International Rectifier.
Billings, K.: Switchmode Power Supply Handbook, second edition. McGraw-Hill, 1999.
Pressman, A. I.: Switching Power Supply Design, second edition, McGraw-Hill, 1998.
International Standard IEC62040-1-1, Uninterruptable power systems (UPS) - Part 1-2: General
and safety requirements for UPS used in operator access areas.
International Standard IEC62040-1-2, Uninterruptable power systems (UPS) - Part 1-2: General
and safety requirements for UPS used in restricted access locations.
International Standard IEC62040-2, Uninterruptable power systems (UPS) - Part 2:
Electromagnetic compatibility (EMC) requirements.
International Standard IEC62040-3, Uninterruptable power systems (UPS) - Part 3: Method of
specifying the performance and test requirements.
YUASA NP valve regulated lead acid battery manual. Yuasa Battery GMBH, 1999.
TOP242-250 Up to 290 W Extended power, design flexible, EcoSmart, integrated off-line switcher
family, data sheet. Power Integrations, August 2003
AN-18, TOPSwitch Flyback Transformer Construction Guide. Power Integrations, 1996.
AN-16, TOPSwitch Flyback Design Methodology. Power Integrations, 1996.
MC9S12E-Family Device User Guide, data sheet. Motorola, 2003.
HCS12 CPU V2.0 Reference Manual, Reference Manual. Motorola, 2003.
HCS12 10-Bit, 16-Channel Analog to Digital Converter (ATD) Block Guide. Reference Manual.
Motorola, 2003.
HCS12 Background Debug Module Block Guide. Reference Manual. Motorola, 2003.
HCS12 Clocks and Reset Generator (CRG) Block Guide. Reference Manual. Motorola, 2003.
Digital-to-Analog Converter: 8-Bit, 1-Channel. Reference Manual. Motorola, 2003.
Debug Module. Reference Manual. Motorola, 2003.
Port Integration Module: 9S12E128. Reference Manual. Motorola, 2003.
HCS12 128K FLASH Block Guide. Reference Manual. Motorola, 2003.
HCS12 Inter-Integrated Circuit (IIC) Block Guide. Reference Manual. Motorola, 2003.
Interrupt (INT) Module V1 Block User Guide. Reference Manual. Motorola, 2003.
Multiplexed External Bus Interface (MEBI) Module V3 Block User Guide. Reference Manual.
Motorola, 2003.
Module Mapping Control (MMC) V4 Block User Guide. Reference Manual. Motorola, 2003.
HCS12 Oscillator Block Guide. Reference Manual. Motorola, 2003.
Pulse Modulator with Fault Protection: 15-Bit, 6-Channel. Reference Manual. Motorola, 2003.
HCS12 8-Bit, 6-Channel Pulse Width Modulator (PWM) Block Guide. Reference Manual. Motorola,
2003.
HCS12 Serial Communications Interface (SCI) Block Guide. Reference Manual. Motorola, 2003.
HCS12 Serial Peripheral Interface (SPI) Block Guide. Reference Manual. Motorola, 2003.
Timer: 16-Bit, 4-Channel. Reference Manual. Motorola, 2003.
Voltage Regulator 3V3 Block User Guide V2. Reference Manual. Motorola, 2003.
MC9S12E128 Controller Board, Design Reference Manual, Motorola 2004
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor
125
Freescale Semiconductor
Application Control
Appendix C. Glossary
ac
alternating current
ac/dc converter
ATD
analog-to-digital converter
A/D
analog-to-digital
AVR
CW
DAC
digital-to-analog converter
dc
direct current
dc/ac converter
dc/dc converter
converter that converts one level of direct voltage to another level of direct voltage
DT
dead time; a short time that must be inserted between turning off one transistor in the
inverter half-bridge and turning on the complementary transistor, to allow for the
limited switching speed of the transistors.
duty cycle
the ratio of the time the signal is on to the time it is off. Duty cycle is usually quoted
as a percentage.
EMC
EMI
IC
integrated circuit
IDE
IGBT
input/output (I/O)
input/output interfaces between a computer system and the external world. A CPU
reads an input to sense the level of an external signal and writes to an output to
change the level on an external signal.
interrupt
logic 1
logic 0
HCS12
MCU
127
MW
Metrowerks Corporation
PC
personal computer
PCB
PCM
PFC
PI Controller
proportional-integral controller
PID Controller
proportional-integral-derivative controller
PLL
PMP
PVAL
PWM
RESET
RMS
SCI
SMPS
software
SPI
SWI
software interrupt; an instruction that causes an interrupt and its associated vector
fetch
THD
timer
UPS
Freescale Semiconductor
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which may be provided in Freescale Semiconductor data sheets and/or specifications can and do
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DRM064
Rev. 0, 09/2004