USB3 Verification Requirement Specification 0.2

USB3SS Verification Requrirement
Specification Template
SKELETON COMPANY CONFIDENTIAL
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B PTZ/N/A [Nithin Maiya]

USB3SS Verification Specification (Requirement/Plan)

USB3 SS - 7600
Revision History

Table 1: Revision history
Date Revision Author Approver(s) Changes
12/09/2014 0.1 Sachin Kumar
Jain
Nithin Maiya
Kumar
Initial version
12/09/2014 0.2 Sachin Kumar
Jain
Removed FS and LS

Table 2: Reference Documents
Document Name Document Number Version
USB3_r1.0_06_06_2011.pdf Revision
r1.0_06_06_2011
DWC_usb3_databook.pdf
USB_30_PIPE_10_Final_042309.pdf

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Table of Contents
1 Introduction 5
1.1 Glossary 5
1 USB3 SUBSYSTEM 7
2 USB3 SS Verification Environment 8
2.1 DATA TRANSFER AND SCOREBOARDING 9
2.1.1 IN DATA TRANSFER 9
2.1.2 OUT DATA TRANSFER 9
2 Alpha Maturity Scenarios/tests 12
2.1 Register Read write Test 16
2.1.1 USB30_SS DWC Controller Register read/write test 16
2.2 Data Transfer Tests 16
2.2.1 USB30_SS_BULK_IN_Test (BYPASS Enumeration) 16
2.2.2 USB30_SS_BULK_OUT_Test (BYPASS Enumeration) 17
2.2.3 USB30_SS_DATA_TRANS_TEST (With Enumeration) 17
2.2.4 USB20_HS_DATA_TRANS_TEST 17
3 BETA Maturity Scenarios/tests 18
3.1 USB30_Functional_LP_Test 18
3.1.1 USB30_U0_U1_U0_Test DSP (host) initiated 18
3.1.2 USB30_U0_U1_U0_Test USP (device) initiated 18
3.1.3 USB30_U0_U2_U0_Test DSP (host) initiated 19
3.1.4 USB30_U0_U2_U0_Test USP (device) initiated 19
3.1.5 USB30_U0_U3_U0_Test DSP (Host) initiated 20
3.1.6 USB30_U0_U3_U0_Test USP (Device) initiated 20
3.1.7 USB30_U0_U3_U0_Test DSP (Device) initiated - Hibernation 21
3.1.8 USB30_U1_U2_HRESUME 22

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3.1.9 USB30_U1_U2_DRESUME 22
3.1.10 USB20_HS_L2SUSPEND_REMTWKUP 22
3.1.11 USB20_HS_L2SUSPEND_RESET 22
3.1.12 USB20_HS_L2SUSPEND_RESUME 22
3.1.13 USB20_HS_L1SUSPEND_REMTWKUP 22
3.1.14 USB20_HS_L1SUSPEND_RESET 23
3.1.15 USB20_HS_L1SUSPEND_RESUME 23
3.1.16 USB20_HS_L2SUSPEND_REMTWKUP_HIB 23
3.1.17 USB20_HS_L2SUSPEND_RESET_HIB 23
3.1.18 USB20_HS_L2SUSPEND_RESUME_HIB 23
4 Final Maturity Scenarios/tests 24
4.1 USB3 Warm Reset Test 24
4.2 USB3 DSP Disconnect Testcase 24
4.3 USB3 USP Disconnect Testcase 25
4.4 USB3 Hot Reset Test 26
4.5 USB3 U0_to_Recovery_to_U0 Test 26
5 Software Sequence Details 28
5.1.1.1 Test Steps: 30
5.1.1.2 Device Mode Sequence 31
5.1.1.3 Device Mode Initialization 31
5.1.1.4 EP_CONFIG - Start Configuration & SET EP CONFIGURATION 31
5.1.1.5 SET EP TRANSFER RESOURCE CONFIGURATION 32
5.1.1.6 Program the BULK_OUT TRANSFER 32

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6 Low Power Scenario/Tests (MVSIM/QUESTANLP) 33
7 GLS Scenarios/tests 34

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1 Introduction
The aim of the Subsystem verification is to focus on the integration tests and inter-operability tests. Further,
the subsystem goes into SoC and SoC verification is performed to assess that the IP is correctly integrated at
the top level and formerly developed tests shall be instrumental in achieving the objective. The verification
plan is a specification document dedicated to:
Identify the IP or subsystem interfaces
Identify the IP or subsystem features
Specify how the features are stimulated (coverage model)
Specify how the features are checked (Self-checking capabilities)
Identify the scenarios (tests) to stimulate the IP or subsystem
Estimate the expected coverage provided by the scenarios
1.1 Glossary
AHB Advanced High-performance Bus
AMBA Advanced Microcontroller Bus Architecture
APB Advanced Peripheral Bus
AXI Advanced eXtensible Interface
BFM Bus-Functional Model
DMA Direct Memory Access
eDMA Embedded DMA
DW Design Ware (all Synopsys IP are called as DW)
EP End Point
GPIO General Purpose Input Output
MPHY MIPI Alliance MPHY (Physical layer)
RRAP Remote Register Access Protocol
USB3 SuperSpeed Inter-chip
SoC System on Chip
SOMA Specification of Modeling Architecture
TLM Transaction Level Modeling
VAL Verification Abstraction Layer

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VRI Virtual Register Interface
VIP Verification IP
UVC Universal Verification Component

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1 USB3 SUBSYSTEM
In this USB3 subsystem, USB3.0 device controller, USB2.0 device controller are
implemented.USB3.0 IP as a bus master will directly access external system DRAM
through the bus interconnection. In this subsystem, the USB3.0 (super-speed) PHY and
USB2.0 (HS) PHY are included. This sub-system has the following features:
Compliant with USB 2.0 specification (revision 2.0), and USB3.0 specification (rev. 1.0).
Can have SS(5-Gbps), HS (480-Mbps), and operation modes.
Support HS USB OTG PHY with ULPI interface and SS USB PHY with PIPE3 Interface.
Support all kinds of transfer types: Control, Bulk, Isochronous, and interrupt.
Transfer descriptor used for data transfer between this modules with system memory.
Descriptor caching/data pre-fetching for high performance requirement
The block doesnt support USB2/USB3 working at the same time.
Below is the functional diagram of the USB3SUBSYS

Figure 1 : USB3 Subsystem Block Diagram
Super Speed USB
Device Controller
USB2.0 PHY
USB3.0 PHY
UTMI+
PIPE3

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2 USB3 SS Verification Environment

Figure 2 : USB3 Subsystem Block Diagram

Figure 2: USB3SS Verification Environment Block Diagram

USB3 Device Controller

USB3.0 PHY USB2.0 PHY

32bit AHB
Slave I/F
64 bit AXI
Master I/F
AHB
MASTER
EVC
AXI SLAVE
EVC

USB 3.0 HOST PIPE USB 2.0 HOST UTMI+

PHY EVC PHY EVC

USB 3.0 HOST Controller EVC

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2.1 DATA TRANSFER AND SCOREBOARDING
2.1.1 IN DATA TRANSFER
USB3 Device Transmits data transfer from memory to VIP USB3 Host
Memory -> TX buffer -> PHY -> VIP Host

A VIP emulates the USB3 Host which requests and receives the data from USB3 DEVICE IP.
SV test shall verify that interrupt is generated at end of transfer and that event buffer is
updated to report correct event notification, which depends on what events were enabled for
notification.
Note: Scoreboard mechanism is implemented in the SV-UVM Environment. SV triggers the
Callback functions to recover the data received by host (VIP). SV Env has reference data
available in the AXI Slave memory. Scoreboard compares consecutive packets of the
reference data with the actual data. If either interrupt is not generated for correct event or
there is data/type mismatch, error will be reported to indicate failure of the test.

AXI IP VIP
MEM
VAL
3
2 1
4

Figure 3: USB3 SS Data IN Transfer Block Diagram
2.1.2 OUT DATA TRANSFER
USB3 Device receives data transfer from VIP Host to external memory, following the path:

VIP Host -> PHY -> Rx buffer -> Memory

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AXI IP
VIP
MEM
VAL
2
3
1
4

Figure 4: USB3SS Data OUT Transfer Block Diagram

A VIP emulates the USB3 Host which transmits data to the USB3 DEVICE SS. SV test shall verify
that interrupt is generated at end of transfer and that event buffer is updated to report correct event
notification, which depend on what events were enabled for notification.

Note: Scoreboard mechanism is implemented in the software. SV has reference data available in
AXI Slave Memory. Scoreboard compares consecutive packets of the reference data with the
actual data. If either interrupt is not generated for correct event or there is data/type mismatch, error
will be reported to indicate failure of the test

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2 Functional Requirements
Functionality support for all layers (Protocol, Link and Physical).

Support to run Protocol layer transfers at Packet-level (Transaction Packet, Data Packet, Link
Management Packet, and Isochronous Timestamp Packet).

Support to run link layer commands (LCRDx, LGOOD, etc.) and link layer Header Packets.

Full enumeration process handling capability (GET_DESCRIPTOR, SET_CONFIGURATION,
SET_ADDRESS, etc.) through control transfers

Support of all kind of Endpoints (Control transfers, Bulk transactions, Interrupt transactions, and
Isochronous
Transactions)

Complete support of Burst Transactions and Flow Control Conditions

Complete support for Bulk Stream protocol state machines for both host and device (ISPSM/IMDSM
and OSPSM/OMDSM)

Support of Link Training and Status State Machine (LTSSM)

Support for Cyclic Redundancy Check (CRC) error in Data Packet Payload (CRC-32), Header
packets (CRC-16), and Link commands (CRC-5)

Support for Link error detection/injection and recovery

Support for Framing Error in Header Packet, DPP and Link Command

Support for injection and detection of Header sequence number error.

Flexibility for injecting other types of Link Errors (like, Header Packet Error, ACK Tx Header
Sequence Number Error etc.)

Support Link Recovery and Header Packet Retransmission

o Supports Link Power Management
o Support for running LGO_Ux link command
o U1/U2/U3 state transitions
o Support for LFPS signaling for Ux State Exit to U0.
o Low power state transition can be initiated by any end

Low power state exit transition can be initiated by any end

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Supports data scrambling/descrambling, 8b/10b encoding/decoding, and electrical/logical idle.

All types of Training Sequence Ordered Sets (for example, TSEQ, TS1, TS2, etc.) supported

Supports loopback mode and lane polarity inversion

Support for Low Frequency Periodic Signaling (LFPS)
o Configurable delays to control timing in transfers at different layers
o Configurable timers to control LTSSM transitions
o Configurable Initial LTSSM state
o Configurable number of TSEQ Ordered Sets in LTSSM
o Configurable number of Polling.LFPS in LTSSM
o Configurable support for skipping

Polling.LFPS and TSEQ ordered sets.

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3 Functional Coverage Bins
Item Remarks
Upon Data packet end, samples packet fields
The coverage group name is: cover_in/out_data_pkt

pkt_kind
Packet KindProtocol Layer (TL)
packet or Link Layer(DLL) packet
data_pkt_len Packet Length
payload_len Packet Payload Length
sop SOP of Packet
eop EOP of Packet
pkt_err

Packet Error Type if any
cross pkt_kind, pkt_err

Item Remarks

LTSSM state transition (Passive upstream port)
The coverage group name is: Cover_ltssm_state

state_name

Current state of the agent
next_state_name Next state of the agent
succeeded_condition
Exit condition of the state
transition

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directed_mode

Mode of the agent, Directed etc.
loopback_mode Loopback mode of agent
cross state_name, next
_state_name, succeeded_condition

state_transition_kind

Transition from state to state

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4 Alpha Maturity Scenarios/tests
4.1 Register Read write Test

This test performs all the read only, write only and read-write tests on the registers of USB3. These checks
are performed in a C test, which is generated from IPXACT xml. These tests are automatically generated by
the spirit2regtest tool.
4.1.1 USB30_SS DWC Controller Register read/write test
XML of DWC USB3 controller is used.
The test will verify the AXI slave interface, implicitly verifying the XML of the Synopsys IP,will verify the
PIPEW register wrt to the XML released

1. DWC_REG
2. PIPE_MIPHY_REG
3. USB2_REG

Register Access for the DWC Module

1). Check the reset value of all the registers.
2). Check all the registers for read write accesses.
4.2 Data Transfer Tests
4.2.1 USB30_SS_BULK_IN_Test (BYPASS Enumeration)
This scenario performs the bulkin test.
USB3 Device DUT enters into U0 LTSSM state after initialization. These data packets are prepared in the
memory first and then send to the VIP. With the help of VRI, comparison is done in software. This scenario
will perform basic IN data transfers in the super speed mode.
Test steps:
1) Disable Scrambling and set scaledown mode to reduce link-training time for simulation
2) CPU enables the USB3 feature through programming
3) Setup The Device TRBs and bypass the control transfer (SetAddress request).
4) Endpoints are configured and resources are allocated accordingly.
5) CPU stores the data into the system memory.
6) Initialize the device registers. Predetermined device address is programmed in core.
7) CPU waits for the connect-done event.

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8) Endpoint start transfer command fetches the data TRB. It decodes TRB and then fetches data
from the system memory to internal buffer of core.
9) Program the Denali host model via VRI to start bulk transfer
10) CPU waits to complete the bulk transfer event.
11) CPU uses the VRI function call to implement the scoreboard mechanism
12) Based on packet comparison, test case Pass/Fail.
4.2.2 USB30_SS_BULK_OUT_Test (BYPASS Enumeration)
This scenario performs the bulkout test.
USB3 Device DUT enters into U0 LTSSM state after initialization. CPU triggers the VIP via VRI to send the
data. With the help of VRI, comparison is done in software. This scenario will perform basic OUT data
transfers in the super speed mode.
Test steps:
3) Setup The Device TRBs and bypass the control transfer.
7) CPU passes data to the VIP through VRI function call.
8) CPU triggers the VIP to start the bulk transfer through VRI
9) Endpoint start transfer command fetches the data TRB.
4.2.3 USB30_SS_DATA_TRANS_TEST (With Enumeration)
1) Verify the USB 3.0 data path of the XHCI Controller with the PIP3 PHY along with USB 3.0 I/F
2) Will include initial USB enumeration sequence in SS mode
3) Will include 1 data transfer in OUT and IN direction
4) DUT in Device mode only"
The Interrupter Target changed to 1 from the default 0, Hence all the EP related interrupt would trigger on
INT_1 line
4.2.4 USB20_HS_DATA_TRANS_TEST

1) Verify the USB 2.0 data path of the XHCI Controller with the ULPI PHY along with USB 2.0 I/F
2) Will include initial USB enumeration sequence in HS mode
3) Will include 1 data transfer in OUT and IN direction
4) DUT in Device mode only

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5 BETA Maturity Scenarios/tests
5.1 USB30_Functional_LP_Test
These tests check the functional low power feature of the USB3 SS.
5.1.1 USB30_U0_U1_U0_Test DSP (host) initiated
It exercises the LTSSM state transition U0 to U1 (entry to U1) and U1 to U0 (exit from U1).
Test steps:
7) Device enters into U0 LTSSM State.
8) Host initiated U1 Exit after U1 Entry (LTSSM Transition U0 > U1 > Recovery > U0)

5.1.2 USB30_U0_U1_U0_Test USP (device) initiated
It exercises the LTSSM state transition U0 to U1 (entry to U1) and U1 to U0 (exit from U1).

Test steps:

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8) Device initiated U1 Exit after U1 Entry (LTSSM Transition U0 > U1 > Recovery > U0)

5.1.3 USB30_U0_U2_U0_Test DSP (host) initiated
It exercises the LTSSM state transition U0 > U2 > U0

Test steps:
5.1.4 USB30_U0_U2_U0_Test USP (device) initiated
It exercises the LTSSM state transition U0 > U2 > U0
Test steps:

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5.1.5 USB30_U0_U3_U0_Test DSP (Host) initiated
It exercises U3 LTSSM state. The transition sequence is U0->U3->U0

Test steps:

5.1.6 USB30_U0_U3_U0_Test USP (Device) initiated
It exercises U3 LTSSM state and hibernation mode is also checked. The transition sequence is U0-
>U3->U0

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Test steps:
5.1.7 USB30_U0_U3_U0_Test DSP (Device) initiated - Hibernation
It exercises U3 LTSSM state and hibernation mode is also checked. The transition sequence is U0-
>U3->U0
Please refer section 8.2 and 8.3 of USB3 Subsystem for 7600 (Document) and for detailed
programming sequence.
Test steps:
8) Store MPHY attributes into the System memory
9) U3 Entry (LTSSM Transition U0 > U3)
10) Wait for hibernate entry event
11) Store the non-sticky registers into the System memory
12) Host initated U3 exit
13) Assert reset to controller (Vcc_reset_n) (LTSSM Transition U3 > SS.Disabled > U3)
14) Restore the non-sticky registers from system memory

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15) Assert reset to MPHY, restore the MPHY registers.
16) Enter into Recovery LTSSM state and wait till U0 entry
5.1.8 USB30_U1_U2_HRESUME
1) DUT is Configured in SS Device Mode
2) Verifying the transitions from U0 to U1 to U2 to U0 States due to host Resume
3) Bulk Data Transfer in the U0 State before and after the transition.
5.1.9 USB30_U1_U2_DRESUME
1) DUT is Configured in SS Device Mode
2) Verifying the transitions from U0 to U1 to U2 to U0 States due to Device Resume
3) Bulk Data Transfer in the U0 State before and after the transition.
5.1.10 USB20_HS_L2SUSPEND_REMTWKUP
1) DUT is Configured in USB2.0 HS Dev Mode
2) Verifying the L2 Suspend Remote Wakeup scenario.
3) Bulk Data Transfer before suspend and after the remote wakeup.
5.1.11 USB20_HS_L2SUSPEND_RESET
2) Verifying the L2 Suspend Reset Wakeup scenario.
3) Bulk Data Transfer before suspend and after the Reset wkup
5.1.12 USB20_HS_L2SUSPEND_RESUME
2) Verifying the L2 Suspend Resume Wakeup scenario.
3) Bulk Data Transfer before suspend and after the Resume wkup
5.1.13 USB20_HS_L1SUSPEND_REMTWKUP
1) DUT is Configured in HS Dev Mode
3) Bulk Data Transfer before suspend and after the remote wakeup

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5.1.14 USB20_HS_L1SUSPEND_RESET
1) DUT is configured in HS Dev Mode
3) Bulk Data Transfer before suspend and after the Reset wkup.
5.1.15 USB20_HS_L1SUSPEND_RESUME
1) DUT is configured in HS Dev Mode
3) Bulk Data Transfer before suspend and after the Resume wkup
5.1.16 USB20_HS_L2SUSPEND_REMTWKUP_HIB
3) Bulk Data Transfer before suspend and after the remote wakeup
5.1.17 USB20_HS_L2SUSPEND_RESET_HIB
3) Bulk Data Transfer before suspend and after the Reset wkup.
5.1.18 USB20_HS_L2SUSPEND_RESUME_HIB
3) Bulk Data Transfer before suspend and after the Resume wkup.

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6 Final Maturity Scenarios/tests
6.1 USB3 Warm Reset Test
Warm reset is the inband reset mechanism which can be initiated from host (Refer USB3 specification 3.6.2)
Test steps:
3) RRAP commands are exchanged in the RxDetect LTSSM state
9) CPU triggers Host VIP model to issue warm reset
10) Host Issues warm reset
11) Device MPHY detects the line-reset
12) Device controller resets the local MPHY and enters into RxDetect Reset LTSSM state.
13) Host and device exchange the RRAP sequence
14) LTSSM transition from RxDetect > Polling > U0

6.2 USB3 DSP Disconnect Test case
DSP Disconnect test (Refer 5.6.2 of USB3 specification for detailed explanation)
Test steps:

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9) CPU triggers Host VIP model to issue DSP Disconnect
10) Host Issues line-reset
11) Device MPHY detects the line-reset
13) Host and device exchange the RRAP sequence for DSP Disconnect
14) Device controller resets the local MPHY and ready to reconnect.

6.3 USB3 USP Disconnect Testcase
USP Disconnect test (Refer 5.6.1 of USB3 specification for detailed explanation)
Test steps:

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9) Device MPHY Issues line-reset
10) Host MPHY detects the line-reset
12) Device is ready to reconnect.

6.4 USB3 Hot Reset Test
-TBD-

6.5 USB3 U0_to_Recovery_to_U0 Test
Recovery is LTSSM state, if entered, retraining on the port required.
Test steps:
8) Entry into U0 LTSSM State
9) Link request to enter into Recovery LTSSM state (LTSSM U0 > Recovery)
10) Retrain and entry into U0 LTSSM state (LTSSM Recovery > U0)

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16) Based on packet comparison, test case Pass/Fail

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7 Error Scenerios/Negative Test
7.1 Data Packet Error
1) CRC 32 error
2) Sequence number error
3) Data packet length error
4) Actual data payload error
7.2 Header Packet Error
1) CRC 5 error
2) CRC 16 error
3) Header packet framing symbol error
4) Header packet sequence number error
5) Data packet start framing symbol error
6) Data packet end framing symbol error
7) Data packet abort framing symbol error
7.3 Link Command Packet Error
1) CRC5 error
2) Link command framing
3) Symbol error
4) Different link command error
5) Link command sequence number error
7.4 Training Sequence Error
1) Corruption of training sequence symbols
2) Corruption of K code

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7.5 Physical layer error
1) Disparity error
2) 8b10b Error

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8 Software Sequence Details
8.1.1.1 Test Steps:
1) Perform the Bulk Transfer as mentioned in 2.4.6.1 or 2.4.6.2 or 2.4.7.1 respectively for FS, HS
& SS mode
2) Enable the Phy Suspend Enable bits (SUSPENDUSB20, ENBLSLPM) in the GUSB2PHYCFG
register and GUSB3PIPECTL (SUSPENDENABLE) bit
3) Write 0 into the USBCMD.Run_Stop bit.
4) Write into the Denali to Put the controller into the Desired low power state (L1/L2/U1/U2/U3) by
writing into PORTSC.PLS bits and PORTSC.LWS bit 1 3.
5) Check the Entry into the desired state by checking the register bits DSTS.Link_State
6) Check the Entry into the desired state by checking the register bits PORTSC.PLS
7) If Hibernation is enable, follow the hibernation entry steps as mentioned in the Synopsys
DesignWare core DataBook 12.2.3.2
8) Exit the hibernation state as per the Synopsys DesignWare core DataBook 12.2.3.4 or 12.2.2.3
depending upon the suspend exit event (Resume/ Remotewkup/ Reset)
For Reset : Initiate USB_RESET from VRI before step 6
For Resume : Initiate Resume from VRI before step 6
For Remote Wkup : Initiate the Remote Wkup event from the DUT after step 6, by writing
RECOVERY into the DCTL.LNKSTATE_CHNG_REQ register
9) Check the Entry into the U0 state (DSTS.LINK_STATE)
10) Perform the bulk transfer as mentioned in step 1
11) If Hibernation is enable, follow the hibernation entry steps as mentioned in the Synopsys
DesignWare core DataBook 12.2.2.1
12) Exit the hibernation state as per the Synopsys DesignWare core DataBook 12.2.2.2 or 12.2.2.3
depending upon the suspend exit event (Resume/ Remotewkup/ Reset)
For Reset : Set the PORTSC.PORT_RESET bit after step 7
For Resume : Set the PORTSC.PLS bit to U0 state and PORTSC.LWS bit 1, after step 7
For Remote Wkup : Initiate the Remote Wkup event from the VRI before step 7
13) Check the Entry into the U0 state (PORTSC.PLS)
14) Perform the bulk transfer as mentioned in step 1

Doc no.
3/002 02-10/LXE 108 820 Uen
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B 2014-08-01
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8.1.1.2 Device Mode Sequence
1) Allocate the memory for the the different data structures
2) Program the Scaledown register bits in GCTL to 2'b11
3) Write '1' to the GCTL.disscramble
4) Write 0x8 to the GUSB2PHYCFG_0_USBTRDTIM (Synopsys Fix)
5) Write 1 to the GCTL.PRTCAPDIR bit, to program the controller in device mode.
6) Program the Device Speed in the DCFG Register.

8.1.1.3 Device Mode Initialization
Write the Data to be transmitted to the DUT_DATA_ADDR Space (for the Bulk IN transactions)
Setup the Device TRB in the TR_ADDR Space for the BULKIN Transfer, as per Section 8.1.1 DWC Specs.
Setup the Device TRB in the TR_ADDR Space for the BULKOUT Transfer, as per Section 8.1.1 DWC Specs.
Device Tx Desc and CMD Registers Programming seq :
Program the GTXFIFOSZ Register.
Program the GEVNTADR Register with the Event_Ring Addr Pointer.
Program the GEVNTSZ Register with the Event Ring Size.
Program the DCFG.NUMP bit for the Interruptor Number for non-ep specific interrupt.
Program the DCFG.DEVADDR for the Device Address.
Program the DCTL.RunStop Register bit, to issue the Run Command.
Set the DEVTEN.CONNECTDONEEVTEN bit, to enable the Connect Event Done Interrupt.

8.1.1.4 EP_CONFIG - Start Configuration & SET EP CONFIGURATION
Program the Configuration Parameters (Param 0, 1 & 2) for the EP, as per Section 7.3.2.5.1 DWC Specs.
Program the DEPCMD Configuration Parameters to Start the New Configuration.
Wait for the DEPCMD.CMDACT (Command Active) bit to go LOW.
Program the DEPCMDPAR_0/1/2 Registers for the Configuration parameters selected for the EP0 (OUT).
Program the DEPCMD Configuration Parameters to SET_EP_CONFIGURATION.
Wait for the DEPCMD.CMDACT (Command Active) bit to go LOW.
Repeat the steps 4, 5,6 for EP0 (IN)
Repeat the steps 4, 5,6 for EP1 (BULK OUT)
Repeat the steps 4, 5,6 for EP1 (BULK IN)

Doc no.
3/002 02-10/LXE 108 820 Uen
Rev
B 2014-08-01
Reference

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ESSRJJN
Checked


8.1.1.5 SET EP TRANSFER RESOURCE CONFIGURATION
Repeat the Steps mentioned in the point e(6, 7, 8, 9) with DEPCMDPAR_0/1/2 as 0/0/1 for the DEPCMD as
EP_TRANSFER_RESOUCE_CONFIG
Wait for the DEV CONNECT Interrupt (Connect Event Interrupt).
Set the DEV_ADDR in the DCFG Register.
Program the BULK_IN_TRANSFER
a. Issue START TRANSFER COMMAND for the EP1-BULK_IN Physical EP, (similiar to steps e(4, 5, 6) with
DEPCMD as START_TRANSFER
DEPCMDPAR_2/1/0 = 0/TRB_ADDR_HI/TRB_ADDR_LO
Issue the Start BULK_IN Transfer for EP1 from the Denali Host using VRI.
Wait for the Transfer Complete Interrupt (Bulk_IN).
Read the Data Received at Denali via VRI.
Check and compare the Data Received at Denali and transmitted by DUT.
8.1.1.6 Program the BULK_OUT TRANSFER
Issue START TRANSFER COMMAND for the EP1-BULK_OUT Physical EP, (similiar to steps e(4, 5, 6) with
DEPCMD as START_TRANSFER
DEPCMDPAR_2/1/0 = 0/TRB_ADDR_HI/TRB_ADDR_LO
Issue the Start BULK_OUT Transfer for EP1 from the Denali Host using VRI.
Wait for the Transfer Complete Interrupt.
Check & Compare the data received.

Doc no.
3/002 02-10/LXE 108 820 Uen
Rev
B 2014-08-01
Reference

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9 Low Power Scenario/Tests (MVSIM/QUESTANLP)

Doc no.
3/002 02-10/LXE 108 820 Uen
Rev
B 2014-08-01
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10 GLS Scenarios/tests

USB3 Verification Requirement Specification 0.2

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