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Multistage Interconnection Netwoks a Review
1
Neha Saini,
2
Shilpa Gupta,
3
Bindu Thakral
1,2
Dept. of ECE, Punjab College of Engineering & Technology, Lalru Mandi, Punjab, India
3
Dept. of ECE, Ansal University, Gurgaon, Haryana, India
Abstract
Multistage Interconnection Networks (MINs) are basic class of
switch-based network architectures, which are used for constructing
scalable parallel computers or for connecting networks. Multistage
Interconnection Networks (MINs) are networks providing fast and
effcient communication. Reliability of MINs is used to measure
systems ability to transform information from input to output.
In section I we reviewed the introduction of MIN networks. In
section II classifcation of MINs is discussed. In section III we
surveyd the reliability of MINs. In section IV conclusion and
future scope of the paper.
Keywords
MIN, Fast and Effcient Communication, Switch-Based Network
Architecture
I. Introduction
Parallel processing is an effcient form of information processing
which emphasizes the exploitation of concurrent events in
computing process by means of cost effectiveness. The highest
level of parallel processing is conducted among multiple jobs
through multiprocessor system. Research and development
of multiprocessor system are aimed at improving throughput,
reliability, fault tolerance and cost. Interconnections are based
on different methods
Bus system which is based on time shared basis 1.
Crossbar switch network which is very expensive and not 2.
scalable
Multidimensional meshes which costly system and needs 3.
more number of hops
Multistage Interconnect Networks (MIN) 4.
processor can connect to multiple memory modules
simultaneously
medium cost effective
More dynamic and static networks available
The basic function of Interconnect Network is to transfer
information from the input nodes of the network to the output
nodes by establishing route through itself in an effcient manner.
Effective procedures for performance analysis are important for
determining the application of MINs. These techniques may be
accurate and effcient but specifc fault tolerance methods used and
improved permutation capabilities are important to performance
enhancement.
II. Multistage Interconnection Networks
Multistage Interconnection Network (MIN) is a good choice
as an Interconnection Network [5,13]. The basic function of
an interconnection network is to transfer information from the
input nodes of the network to the output nodes by setting up
communication paths for routing through the network, in an
effcient manner. The topological and functional properties
of interconnection networks, used for processor-processor or
processor-memory interconnection, have been the subject of
research over the years.
Interconnect Networks (IN) on the basis of network topology can
be classifed into four major categories. These are:
1. Static(Direct) IN: One-to-one Connection between source and
destination [41].
Ring
Star
Meshes
Fully connected Ring
Bus
2. Dynamic(Indirect) IN: Route is to be decided through active
switching elements[41].
Cross-bar
Multistage Interconnection Networks(MIN)
3. Hybrid IN: Both topologies are included in a single
network[41].
Hyper-cube
Hyper-meshes
Multistage Interconnection networks are the major class of indirect
networks, being recognized as cost-effective means to provide
high bandwidth communication in multiprocessor systems.
Regular: If the number of SEs is same in each stage, then the MIN
is specifed as regular MIN.
Irregular: If the number of SEs is not same in each stage, then the
MIN is specifed as Irregular MIN.
As discussed there are two types of IN: Static and Dynamic.
Static networks have the advantage of being simple to built and
expand, requiring a simple routing algorithm. Bust such a network
fails even in the presence of a single fault, without overheads
[41]. Many static networks have been proposed, examples include
the Omega Network and the Baseline Network [1,2]. A dynamic
network allows the interconnection pattern among the network
nodes to be varied dynamically, being accomplished by some
form of switching. Examples of dynamic networks include ASEN,
ABN etc., and many bus-based networks [3,4]. The routing path
is fxed in a static MIN, while in a dynamic MIN , it is adaptable
according to faults / traffc present.
To design multistage interconnection networks (MINs),
incorporating small crossbar switches organized in stages, are
used. A large number of network designs based on Clos [18] and
Benes[15] networks have been proposed and used in the last three
decades. Clos Network was frst outlined by Charles Clos in 1953.
The frst stage of the network consists of r switches, each of size
(n x m); middle stage has m switches of size (r x r) each; and the
last stage is the mirror image of the frst. Thus, the network has
N = r.n input terminals and output terminals.
Most of the MINs proposed in the literature are usually constructed
using 2x2 crossbar switches and have n = log2N stages, every stage
consisting of N/2 SEs. Total number of switches in the network is
N/2 (log2N) for NxN network, as compared to O(N2) for a crossbar
network. Omega Network [11] maintains a uniform connection
pattern between stages. Every input terminal has a unique path to
every output terminal, and exhibits the property of self-routing,
i.e. routing is performed in a distributed manner using destination
address as the routing tag. If the stages of Omega Network are
traversed backward, inverse path from destination to source is
accomplished between stages, to get the inverse Omega Network
which is also a useful MIN in parallel processing environment
as it suffciently supports the communication patterns in several
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parallel algorithms such as Fast Fourier Transforms (FFTs) and
matrix operations [11].
Applications of regular topologies include such usage where latency
provided by all paths is the same. Cube Network is an example
of a regular MIN wherein which the SEs are interconnected as
the corners of a m-dimensional cube [6]. Irregular topologies
provide paths of varying lengths, thus reducing the average
latency considerably. The irregular Double Tree (DOT) Network,
originally proposed by Levitt [7], has many paths of diverse length
between any input / output[8].
Examples of static MINs include the Shuffe Exchange Network
[10], the Delta Network [12], Generalized Shuffe Exchange
Network [16], Data Manipulator Network [5], Indirect Binary
n-cube Network [15]. Topological equivalence of several of these
networks has been established [9]. These networks can also be
constructed by using larger sized SEs with corresponding reduction
in the number of stages, and hence in the latency offered by the
network.
Delta Networks, introduced by Patel [12] have the property of
digit controlled routing, which means that a path can be setup
through the network in a distributed manner by using individual
bits of the destination address.
A further generalization of Delta Networks, called Generalized
Shuffe-Exchange Network [GSN] was introduced by Bhuyan
and Agarwal [16].
Pease proposed a MIN, called Indirect Binary n-cube, where
interconnection patterns are modeled after the links to
n-dimensional hypercube [15]. Each set of inter-stage links
correspond to a dimension of the hypercube.
Another well studies class of MINs is the Data Manipulator. In
this network, each stage has N SEs and switching elements are
controlled centrally. A detailed discussion of these networks may
be found in Siegal [21]. The Augmented Data Manipulator (ADM)
has the same topology as that of Data Manipulator except that the
SEs are now controlled individually. The Inverse Augmented Data
Manipulator IADM Network. The data manipulator networks is
not unique path network, the path between any source destination
pair is specifed by constructing a routing tag.
Dynamic MINs have the ability to dynamically reroute the data
through a fault free path if the regular path is faulty or busy. These
networks are also known as rearrangeable networks. The Benes
rearrangeable binary network is an example of such a network.
Recently, one-sided cross point switching network has been studies
by Verma and Chalasani [20].
III. Reliability
A large volume of literature exists on the subject of fault-
tolerance in interconnection networks. Even though a number of
multipath MINs have been designed that provide faulttolerance,
the challenge in accepting new Fault-Tolerant designs is the
enhancement of performance and reliability. Various methods
investigated and used for fault-tolerance include introduction
of redundancy in a known topology, and exploiting inherent
redundancy of the topology. Most of these networks described
in the literature are derived from unique path networks [14]. Faults
in the computer system often result in degraded performance that
declines dramatically with the increase in network size. Several
performance enhancements have been employed, such as use of
parallel links and multiple sub-networks.
A. Redundancy at the Network Level
Fault-Tolerant Networks are designed to provide multiple copies
of the same unique path network.
INDRA network incorporates union of R parallel copies of a basic
unique path network with an initial distribution stage.
Another example of a fault-tolerant statically reroutable regular
MIN is the Modular Network (MN) [23]. Redundant paths are
created by adding modules so that links can be made available
by providing connections though these modules in the event of a
fault in the regular path.
B. Redundant Stages in the Network
Adding redundant copies of networks is an expensive solution,
but all classes of permutations can be routed even in the presence
of multiple switch failures. When full access is the ultimate
criteria of fault-tolerance, then extra switching stage provides a
costly, though highly reliable solution to failures. Examples of
such networks include Extra Stage Cube (ESC) , Extra-Stage
Omega [25].
The Extra Stage Cube is constructed from Generalized Cube
Network by adding an extra stage at the front of the network.
Multiplexers and demultilexers are attached at input and output
stage. Fault-tolerance is improved but at the cost of increase in
path length and complexity of the network.
By adding a redundant switching stage at the input of the Omega
Network, Extra Stage Omega Network is obtained. This MIN
provides high fault-tolerance but at the expense of additional cost,
as well as higher latency as the path length from any source to
any destination is increased.
Augmented Shuffe-Exchange Network (ASEN), a multipath MIN,
features links among switches belonging to the same stage.
A comparison of multi-pass approach reveals some interesting
tradeoffs in introducing fault-tolerance into the MIN. The extra-
stage approach, where an additional switching stage is provided
in the MIN to create multiple paths, is a traditional approach.the
comparision of two types of MIN with their extra stages.
IV. Conclusion and Future Scope
In this section, the concept of fault tolerance of MIN has been
studied with their structural characteristics. To increase the fault-
tolerant capability of network the redundant paths are to be added
to the network. But this is not true every time i.e. with the increase
in the stages multiple paths increase but with more number of
extra stages the reliability of network decreases.
Review of the studied papers conclude that reliability of regular
MIN networks are found.In future further research work can be
done to fnd out the reliability of irregular networks.
References
[1] T.Y. Feng, Survey of interconnection Networks, IEEE
Computer, Vol. 4, Dec. 1981, pp. 12-27.
[2] George B. Adams and Howard Jay Siegel A Survey of Fault-
tolerant Multistage Networks and comparison to Extra Stage
Cube, 17th Annual Hawaii International Conference on
System Sciences, 1984, pp. 268-277.
[3] George B. Adams, Dharma P. Agrawal and Howard Jay Siegel,
A Survey and Comparison of Fult-tolerent Multistage
Interconnection Networks, IEEE Computer, June 1987,
pp. 14-27.
[4] Laxmi N. Bhuyan, Qing Yang and Dharma P. Agrawal
Performance of Multiprocessor Interconnection Networks,
IEEE, Feb. 1989,pp. 25-37.
IJECT VOL. 4, ISSUE SPL - 3, APRIL - JUNE 2013 ISSN : 2230-7109 (Online) | ISSN : 2230-9543 (Print)
www. i j e c t . o r g
88
INTERNATIONAL JOURNAL OF ELECTRONICS & COMMUNICATION TECHNOLOGY
[5] R.K. Dash, N.K. Barpanda, P.K. Tripathy, C.R. Tripathy,
Network reliability optimization problem of interconnection
network under node-edge failure model, Elsevier, Journal
of Applied Soft Computing (2012), pp. 23222328.
[6] Howard Jay Siegal, Wayne G. Nation, Clyde P. Kruskal and
Leonard M. Napolitano, Jr., Using the Multistage Cube
Network Topology in Parallel Supercomputers, Proceedings
of IEEE, Vol. 77, No.12, Dec. 1979, pp. 1932 1953.
[7] N.Levitt, M.W. Green and J. Goldberg, A study Communication
Problem in the Self-Repairable Multiprocessor, Proc.
AFIPS Conference, Vol.32, 1968.
[8] C.K.C. Leung and J.B. Dennis, Design of Fault-Tolerant
Packet Communication Computer Architecture, Proc.
International Symposium on Fault Tolerant Computing,
August 1980, pp. 328-335.
[9] Dharma P. Agrawal, Graph Theoretical Analysis and Design
of Multistage Interconnection Networks, IEEE Trans. On
Computer, Vol.C-32, No.7, July 1983, pp. 637-648.
[10] H.S. Stone, Parallel Processing with the Perfect Shuffe,
IEEE Trans. On Computers, Vol. C-20, Feb. 1971, pp. 153-
161.
[11] D.H. Lawrie, Access and Alignment of Data in an Array
Processor, IEEE Trans. On Computers, Vol. C-24, Dec.
1975, pp. 1145-1155.
[12] J.H. Patel, Processor-Memory Interconnection for
Multiprocessors, Proc. of the 6th Annual Symposium on
Computer Architecture, April 1979, pp. 168-177.
[13] K. Hwang, Advanced Parallel Processing with Super
Computers, Proc. IEEE, OC-79, Oct. 1987, 127-137.
[14] Sadawarti, H.; and Bansal, P.K. Fault-tolerant Routing in
Unique-Path Multistage Interconnection Networks, In:
Proceedings of the IEEE First India Annual Conference
INDICON-2004, 20-22 December, pp. 427-430.
[15] M.C. Pease, The Indirect Binary n-Cube Multiprocessor
Array, IEEE Trans. On Computers, Vol. C-26, No.5, May
1977, pp. 458-473.
[16] L.N. Bhuyan and D.P. Agrawal, Design and Performance
of Generalized Interconnection Network, IEEE Trans.
On Computers, Vol. C-32, No. 12, Dec. 1983, pp. 1081
1090.
[17] V.E. Benes, Mathematical Theory of Connecting Networks
and Telephone Traffc, Academic Press, New York, 1965.
[18] Clos, A Study of Non-Bocking Switching Networks, Bell
System Technical Journal, Vol. 32, March 1953, pp. 406-
424.
[19] V.P. Nelson, Fault-Tolerant Computing: Fundamental
Concepts, IEEE Computer, Vol. 23, No.7, July 1990, pp.
19-25.
[20] Anujan Varma and Suresh Chalasani, Fault-Tolerant Analysis
of One Sided Cross-Point Switching Network, IEEE Trans.
On Computers, Vol.4, No.2, Feb. 1992, pp. 143-158.
[21] H.J. Siegal, Interconnection Networks for Large Scale
Parallel Processing: Theory and Case Studies, Lexington,
MA: Lexington Books, 1985.
[22] C.S. Raghavandera and A. Varma, INDRA: A Class of
Interconnection Networks with Redundant Paths, Proc.
Real-Time Systems Symposium, December 1984, pp. 153-
164.
[23] P.K. Bansal, Kuldip Singh and R.C. Joshi, Reliability and
Performance Analysis of a Modular Network, Journal of
Microelectronics and Reliability, Vol. 33, No.4, 1991, pp.
529-534.
[24] S. Wei and G. Lee, Extra Group Network: A Cost-Effective
Fault-Tolerant Multistage Interconnection Network, Proc.
15th Annual Symposium on Parallel Architecture, June 1988,
pp. 108-115.
[25] G.B. Adams III and H.J. Siegal, The Extra Cube: A
Fault-Tolerant Symposium Interconnection Network for
Supersystems,Trans. On Computers, Vol. C-31, May 1982,
pp. 443-454.
[26] Indra Gunawan, Reliability analysis of shuffe-exchange
network systems,Elsevier Journal of Reliability Engineering
and System Safety 93 (2008, pp.) 271276.
[27] Indra Gunawan, Redundant paths and reliability bounds in
gamma networks, Elsevier Journal of Applied Mathematical
Modelling 32 (2008), pp.588594.
[28] Suresh Rai ,Tighter Bounds on Full Access Probability in
Fault-Tolerant Multistage sParallel and Distributed Systems,
V. 10, No. 3, March 1999, pp. 328-335.
[29] Himanshu Agarwal, Thesis on Multistage interconnection
Networks Thapar Institute of Engg. And Technology,Patiala,
India, 2000.
[30] Sheetal, Thesis on Fault tolerant Multistage interconnection
Networks Thapar Institute of Engg. And Technology,Patiala,
India, 2008.
[31] Peter Newman,Thesis on Fast Packet Switching for
Integrated Services, Wolfson College University of
Cambridge, Dec.1988.
[32] Lauderdale, Grant Matthew,Thesis on Performance
Prediction of Packet Switched Multistage Interconnection
Network in an Execution-driven environment Rice
University, 1990.
[33] Sven-Arne Reinemo, thesis onQuality of Service in
Interconnection Networks the Faculty of Mathematics and
Natural Sciences at the University of Oslo, Sept. 2007.
[34] Neha Sharma, D. Chadha, Vinod Chandra, The augmented
data vortex switch fabric: An all-optical packet switched
interconnection network with enhanced fault tolerance, ,
Elsevier Journal of Optical Switching and Networking 4
(2007),pp. 92105.
[35] J. Sengupta, P.K. Bansal and Ajay Gupta, Permutation and
Reliability Measures of Regular and Irregular MINs, 2000
IEEE, 0-7803-6355-8/00 pp.-I-531-I-536.
[36] Ching-Wen Chen, Neng-Pin Lu, Chung-Ping Chung,3-
Disjoint gamma interconnection networks Elsevier Journal
of Systems and Software 66 (2003), pp.129134.
[37] Sharma, S.; Kahlon, K.S.; Bansal, P.K.; and Singh, K.
Irregular Class of Multistage Interconnection Networks in
Parallel Processing, Journal of Computer Science, 4 (3),
2008a, pp. 220-224.
[38] S.; Kahlon, K.S.; and Bansal, P.K., On a class of Multistage
Interconnection Networks in Parallel Processing,
International Journal of Computer Science and Network
Security, 8 (5), 2008b, pp. 287-291.
[39] Subramanyam, A.; Prasad, E.V.; and Nadamuni, R.,
Permutation Capability and Connectivity of Enhanced
Multistage Interconnection Network (E-MIN), In:
Proceedings of IEEE International Conference on Advanced
Computing and Communications ADCOM-06, 20-23
December 2006, pp. 8-11.
[40] Subramanyam, A.; Prasad, E.V.; and Reddy, C.N.,
Performance Evaluation of Single Stage and Multistage
Interconnection Networks Connectivity in Multiprocessors,
IE(I) Journal CP, 89,2008, pp. 38-45.
IJECT VOL. 4, ISSUE SPL - 3, APRIL - JUNE 2013
www. i j e c t . o r g INTERNATIONAL JOURNAL OF ELECTRONICS & COMMUNICATION TECHNOLOGY
89
ISSN : 2230-7109 (Online) | ISSN : 2230-9543 (Print)
[41] J. Sengupta, P.K. Bansal and Ajay Gupta, Permutation and
Reliability Measures of Regular and Irregular MINs, 2000
IEEE, 0-7803-6355-8/00 pp.-I-531-I-536.
[42] Ching-Wen Chen, Neng-Pin Lu, Chung-Ping Chung,3-
Disjoint gamma interconnection networks Elsevier Journal
of Systems and Software 66 (2003), pp.129134.
[43] J. Sengupta, P.K. Bansal and Ajay Gupta, Permutation and
Reliability Measures of Regular and Irregular MINs, 2000
IEEE, 0-7803-6355-8/00 pp.-I-531-I-536.
[44] Aggarwal, H.; and Bansal, P.K., Routing and Path Length
Algorithm for Cost-effective Modifed Four Tree Network,
In: Proceedings of IEEE Region 10 Conference on Computers,
Communications, Control and Power Engineering, TENCON-
02, 28-31 October(2002), pp. 293-297.
[45] Aljundi, A.C.; Dekeyser, J.L.; and Kechadi, M.T., On
the Scalability of Multistage Interconnection Networks,
In: Proceedings of IEEE International Conference on
Information and Communication Technologies: From Theory
to Applications, 19-23 April(2001), pp. 655-656.
[46] Aljundi, A.C.; Dekeyser, J.L.; and Kechadi, M.T., A
Study of an Evaluation methodology for Unbuffered
Multistage Interconnection Networks, In: proceedings of
IEEE International Symposium on Parallel and Distributed
Processing, 22-26 April(2003).
[47] Aljundia, A.C.; Dekeyser, J.L.; Kechadi, M.T.; and Scherson
I.D., A Universal Performance Factor for Multi-criteria
Evaluation of Multistage Interconnection Networks, Future
Generation Computer Systems, 22 (4), (2006), pp. 794-
804.
[48] Bataineh, S.M.; and Qanzu, G. E., Reliable Omega IN
for Large-scale Multiprocessor Systems, The Computer
Journal, 46 (5), (2003)pp. 467-475.
[49] Bataineh, S.M.; and Allosl, B.Y., Fault-tolerant Multistage
Interconnection Network, Telecommunication Systems, 17
(4), (2001),pp. 455-472.
[50] Bhatia, M.; and Youssef, A. (1998), Performance Analysis
and Fault Tolerance of Randomized Routing on Clos
Networks, Telecommunication Systems, 10 (1), pp. 157-
173.