Sunteți pe pagina 1din 4


5: Digital Signal Processing T P Chaturvedi, RCD

The world of science and engineering is full of signals. Digital Signal Processing (DSP) is the
science of using computers to understand these types of signals. DSP is widely replacing analog
systems due to its reliability, repeatability and programmability. DSP instruments use the Fast Fourier
Transform (FFT) to translate digitized time domain signals into the frequency domain for the
purpose of measurement and analysis.

Analog to Digital Converter: ADC converts a signal which is continuous in time and amplitude into
one that is discrete in time and amplitude. The ADC is specified for Input Range, Resolution,
Quantization Error, Conversion speed, Sampling Rate etc.

Input Range: The maximum analog voltage which can be applied to input of ADC for the conversion.
Resolution & Quantization: An ideal ADC
represents all analog inputs within a certain
range by a limited number of digital output
codes. The diagram shows that each digital
code represents a fraction of the total analog
input range. Since the analog signal may be
continuous, while the digital codes are
discrete, there is quantization process that
introduces a quantization error.

The analog samples are quantized and
mapped into their nearest digital value.
For example, a 4 bit ADC can represent an
analog sample as one of 16 possible values
i.e. (2
= 16). If the range of this converter is
0 and 10 volts, then its resolution is 10/(2
= 0.667 volts/bit.

The width of one step is defined as 1 LSB
(least significant bit). It is also a measure of
the resolution of the converter since it defines the number of divisions or units of the full analog range.
The resolution of an ADC is usually expressed as the number of bits and is improved by
increasing it. For example, an ADC with an n-bit resolution has 2
possible digital codes which define
step levels. However, since the first (zero) step and the last step are only one half of a full width,
the full-scale range (FSR) is divided into 2
1 step widths. 1LSB=FSR/ (2
1) for an n-bit ADC.






Quantizing Noise: Quantizing noise is introduced in
the process of converting the analog signal to digital
value. Quantizing noise is basically due to the finite
resolution of ADC. The two main variables in
quantizing are the quantization level and dynamic
For any input within the dynamic range of the
digitizer, the output will be a digital representation of
the input, to the nearest integral multiple of the
quantization level. Now this noise or error introduced
by the quantization depends on the relative intensity of
the noise in the original signal with respect to the size
of the quantization level. The Standard deviation of
the quantization noise is V/12, where V is the
magnitude of quantization level in volts.

Sampling: In order to convert an analog signal into a digital code, it must first be sampled. This
results in natural sample values which remain continuous in amplitude but discrete in time. The
sample values are exactly equal to the original signal value at the sampling instant. The amplitude of
the analog signal is measured at discrete points in time using a sample and hold circuit.

Nyquist Sampling Theorem: Nyquist Sampling Theorem states that a signal must be sampled at a
rate that is twice the highest frequency component in the signal. In other word, if the sampling rate
is 1/t (sampling interval =t), the Fourier transform of the signal must be zero at all the frequencies
greater than 1/(2t). The critical frequency, Fn=1/(2t), is called Nyquist frequency. A signal with
Fourier components from 0 to 300 Hz should sampled at a rate of at least 600 samples per second or
every 1.7 msec.
Under sampling and Alias frequency: If the
signal is under sampled there will be errors in
reconstruction of the signal back.. These errors
will manifest in two ways. The frequency
information above the nyquist frequency will
be lost and under sampled high frequency
show up as spurious low frequency called as
aliasing. If the analog signal is under sampled,
signal reconstructed will have lower aliasing
frequencies not present initially. Here we have a
100 Hz sine wave sampled at 80 Hz i.e. less than 2 * fmax and as a consequence the reconstructed
signal could also be as 20 Hz.
This effect is known as aliasing, and is
combated by first ensuring the sampling rate is
high enough and secondly through the use of an
analog low pass filter in front of the ADC. This
filter is called an anti-aliasing filter. Anti-aliasing filter
ensures that any frequency components which could
cause aliasing are suppressed.

Differential Non Linearity (DNL) is defined as maximum amount of deviation of any quantum ( or
LSB change) in entire transfer function from its ideal size of FS/2

Differential Non Linearity (DNL) is defined as maximum amount of deviation of any quantum ( or
LSB change) in entire transfer function from its ideal size of FS/2

Analog-to-digital converter:


Flash ADC: Also called the parallel A/D converter. It is
formed of a series of comparators, each one comparing the
input signal to a unique reference voltage. The comparator
outputs connect to the inputs of a priority encoder circuit,
which then produces a binary output. For N bit ADC 2
comparators are required.

Successive Approximation ADC: Successive
approximation ADC starts first setting the MSB (most
significant bit, on an eight-bit ADC it would be D7). The
comparison between Vin and the DAC output will tell the control
unit if this bit should remain set at 1 or should be set at 0, as the
op amp will tell right away the control unit if the sample value is
greater or lower than 128 (2^7). Then D6 is set to one, and from
the comparison done by the op amp, the control unit will know if
this bit should remain set or not. And so on.
The good thing about the successive approximation ADC is
its speed. At the worst case it will find the correct digital value
for the sample at n clock cycles, where n is the number of bits
used. For an eight-bit ADC, the digital value for each sample
can be found in up to eight clock cycles (compare to 255 on
the ramp counter), and for a 16-bit ADC the digital value for
each sample can be found in up to 16 clock cycles (compare
to 65,535 of counter ADC). Input 3V, 8 bit ADC

Dual-Slope ADC: The switch first connects Vin to the integrator.
With that, the integrator starts generating the sawtooth waveform,
and the switch position will remain set at Vin during a fixed number
of clock cycles. When this number of clock cycles is reached, the
analog switch moves its position to allow Vref to enter the
integrator. Since Vref is a negative voltage, the sawtooth
waveform goes towards zero, using a number of clock cycles
proportional of the Vin value. T1 is fixed, while T2 duration is
proportional to the value of Vin. Vin sets the slope angle: the higher
Vin is, the higher the angle will be.
Waveform found at the integrator output
T2=T1 x V

Input Voltage C0 C1 C2 Q0 Q1
0 to 1V Low Low Low 0 0
1V to 2V High Low Low 0 1
2V to 3V High High Low 1 0
3V to 4V High High High 1 1
Bit Analog
DAC setting Analog
ator o/p
Digital O/P
7 2.5 1000 0000 2.5 High 1000 0000
6 1.25 1100 0000 3.75 Low 1000 0000
5 0.625 1010 0000 3.125 Low 1000 0000
4 0.3125 1001 0000 2.8125 High 1001 0000
3 0.15625 1001 1000 2.96875 High 1001 1000
2 0.078125 1001 1100 3.04 Low 1001 1000
1 0.039 1001 1010 3.007 Low 1001 1000
0 0.0195 1001 1001 2.988 High 1001 1001


Weighted Resistor Digital to Analog Converter (DAC)
A switch connects an input either to a common voltage V
or to a common ground. Only switches currently
connected to the voltage source contribute current to the
non-inverting input summing node. S
= 1 if switch X
connects to V, S
= 0 if it connects to ground.
There are eight possible combinations of connections for
the three switches. The inputs are weighted in a 4:2:1
relationship, so that the sequence of values 4S3 + 2S2 +
S1 form a binary-coded decimal number representation.
The magnitude of Vo varies in units (steps) of (R
from 0 to 7. The digital input controls the switches, and the
amplifier provides the analog output.
The converter uses only one resistor per bit. Matching the resistors is critical to achieve linearity is
disadvantage. This type of converter is most often used where only a few bits, say 4 or 6, are required
and performance is not critical.

R-2R Ladder DAC
It solves problem of the weighted resistor converter since it uses
only two resistor values the matching is considerably easier to
achieve, making it easy to integrate on an IC.

A three-section R-2R ladder is connected to a switch network so
that either a fixed voltage V is applied to each section or a ground
connection is made. The current contribution through each switch
(apply superposition) is as given. Sx is a binary variable which has
the value 1 is the voltage connection is made, and the value 0 for
a ground connection.

The current from the ladder is fed to an inverting amplifier, and the output voltage Vo is
Vo = -R
1 1 1
3 2 1 )
3 2 3 4 3 8
= -R

(4 3 2 2 1) S S S



Flash Type Low conversion time (~
20 ns )

For N bit ADC 2
required, Large DNL

Conversion time <
High Resolution
Poor linearity( 1/2

Dual Slope ADC

Excellent linearity,
Good noise rejection
Slow speed