Reg.

No
V.S.B. COLLEGE OF ENGINEERING TECHNICAL CAMPUS, COIMBATORE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
INTERNAL TEST - IV
EC 6302- DIGITAL ELECTRONICS

YearSe!e"#er $ Bra%&'( II III ECE Da#e(
Fa&)*#+ Na!e( S.SUGUNA T,!e( -00!,%"
Ma. .Mar/"( 00
PART-A A%"1er ALL 2)e"#,3%" 40.25-0 Mar/"6
1. What is meant by programmable counter? Mention its application. Apr/May 2010
2. Write about modulus of a counter. May/un 2011
!. "o# a $ flip%flop is con&erted into ' flip%flop. No&/$ec 2012
(. Write do#n the classification of memories. No&/$ec 2012
). $istinguish bet#een *+R,M and **+R,M. May/un 2011
PART-B A%"1er ALL 2)e"#,3%" 478-68-6590 Mar/"6
-. .a/ $esign a ! bit ohnson counter and e0plain its operation. No&/$ec 2012 .1/
OR
-. .b/ *0plain the operation of shift and ring counters. May/un 2012 .1/
2. .a/ $esign a se3uence detector #hich detects the se3uence 01110 using
$ flip flops .one bit o&erlapping/ No&/$ec 2012 .1-/
OR
2. .b/ 4mplement the follo#ing 5oolean function #ith a +6A.
7
1
.A85.9/ : (0,1,2,4)
F
2
(A,B,C) = (0,5,6,7)
F
3
(A,B,C) = (0,3,5,7) No&/$ec 200; .1-/
1. .a/ *0plain in detail +R,M and +R,M +rogramming. No&/$ec 2010 .1-/
OR
1. .b/ *0plain the basic structure of 2)-<( static RAM #ith neat diagram. May/un 2011 .1-/
<<<<<

+repared by Appro&ed by
.=.=uguna A+/*9*/ .=.=uguna A+/*9*/
Form No. AC 08a Rev.No. 00 Effective Date: 30/06/2014
Reg.No
V.S.B. COLLEGE OF ENGINEERING TECHNICAL CAMPUS, COIMBATORE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
INTERNAL TEST-IV
EC 6302- DIGITAL ELECTRONICS

YearSe!e"#er $ Bra%&'( II III ECE Da#e(
Fa&)*#+ Na!e( S.SUGUNA T,!e( -00!,%"
Ma. .Mar/"( 00
PART-A A%"1er ALL 2)e"#,3%" 40.25-0 Mar/"6
1. $ra# the logic diagram of =tatic and 5ipolar RAM cell. No&/$ec 2012
2. Mention fe# applications of +A6 and +6A. May/un 2012
!. Whether R,M is classified as a non &olatile storage de&ice? Why? May/un 2011
(. $istinguish bet#een synchronous and asynchronous circuits. No&/$ec 200;
). What is meant by memory e0pansion? Mention its limit. Apr/May 2010
PART-B A%"1er ALL 2)e"#,3%" 478-68-6590 Mar/"6
-. .a/ What is meant by >ni&ersal =hift register? *0plain the principle of operation of ( bit >ni&ersal
=hift Register. Apr/May 2010 .01/
OR
-. .b/.i/ Write short notes on master sla&e flip flop. No&/$ec 2010 .0-/
.ii/ Write do#n the characteristic table for ? flip%flop #ith N,R gates. Apr/May 2010 .02/
2. .a/ 5riefly e0plain about
i/ =tate $iagram
ii/ =tate Reduction
iii/ =tate 'able
i&/ =tate Assignment May/un 2011 .1-/
OR
2. .b/ .i/$iscuss the classification of R,M and R,M memories. May/un 2012 .01/
2. .b/.ii/ *0plain Memory $ecoding and Memory *0pansion of digital system. May/un 2012 .01/
1. .a/ .i/ *0plain the principle of operation of 5ipolar =RAM cell. Apr/May 2010 .01/
1. .a/ .ii/ We can e0pand the #ord si@e of a RAM by combining t#o or more RAM chips. 7or instance8
#e can use t#o !201 memory chips #here the number !2 represents the number of #ords and 1
represents the number of bits per #ord8 to obtain a !201- RAM. 4n this case the number of #ords
remain the same but the length of each #ord #ill 2 bytes long. $ra# a blocA diagram to sho# ho# #e
can use t#o 1-0( memory chips to obtain a 1-01 RAM. Apr/May 2010 .01/
OR
1..b/ $esign a combinational circuit using R,M. 'he circuit accepts ! bit number and outputs a binary
number e3ual to s3uare of the input number. No&/$ec 200; .1-/
Form No. AC 08a Rev.No. 00 Effective Date: 30/06/2014
Reg.No
+repared by Appro&ed by
.=.=uguna A+/*9*/ .=.=uguna A+/*9*/
Form No. AC 08a Rev.No. 00 Effective Date: 30/06/2014