Mikro Komputer

Microkomputer
INTRODUCTION TO COMPUTER, MICROCOMPUTERS and

MICROCOMPUTER BLOC DIAGRAM

Dosen Pembimbing:
ISRAM RASYAL, ST.,MMSI,MSc

Anggota

Anjar Syaefa Ibrahim (20112943)
Abdul Ghafiqi Yamini (20112028)
Rafi Sukran (25112881)
Siti Anshila Putri (27112044)
Trina Putri Andini (27112478)

UNIVERSITAS GUNADARMA
FAKULTAS ILMU KOMPUTER DAN TEKNOLOGI INFORMASI
SISTEM KOMPUTER
2014
University of Technology
Department of Electrical & Electronic Eng.
Fourth Year-Microprocessor Eng. II

Introduction to Computer &
Microcomputers
Lecture One-Page 1 of 11
Dr. Hadeel Nasrat
INTRODUCTION TO COMPUTER AND
MICROCOMPUTERS
What is a Computer?
An electronic device that accepts input, stores large quantities of data, execute
complex instructions which direct it to perform mathematical and logical operations
and outputs the answers in a human readable form.
Computers are not very intelligent devices, but they handle instructions
flawlessly and fast. They must follow explicit directions from both the user and
computer programmer. Computers are really nothing more than a very powerful
calculator with some great accessories. Applications like word processing and games
are just a very complex math problem.
Computer Generations
From the 1950s, the computer age took off in full force. The years since then
have been divided into periods or generations based on the technology used.
1. First Generation Computers (1945-1954): Vacuum Tubes
These machines were used in business for accounting and payroll applications.
Valves were unreliable components generating a lot of heat. They had very limited
memory capacity. Magnetic drums were developed to store information and tapes
were also developed for secondary storage. They were initially programmed in
machine language (binary). A major breakthrough was the development of
assemblers and assembly language.
2. Second Generation (1955-1964): Transistors
The development of the transistor revolutionized the development of
computers. Invented at Bell Labs in 1948, transistors were much smaller, more
rugged, cheaper to make and far more reliable than valves. Core memory was
introduced and disk storage was also used. The hardware became smaller and more
reliable, a trend that stills continues. Another major feature of the second generation

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was the use of high-level programming languages such as Fortran and Cobol. These
revolutionized the development of software for computers.
3. Third Generation (1965-1974): Integrated Circuits (ICs)
ICs were again smaller, cheaper, faster and more reliable than transistors.
Speeds went from the microsecond to the nanosecond (billionth) to the picosecond
(trillionth) range. ICs were used for main memory despite the disadvantage of being
volatile. Minicomputers were developed at this time. Terminals replaced punched
cards for data entry and disk packs became popular for secondary storage. IBM
introduced the idea of a compatible family of computers, 360 family easing the
problem of upgrading to a more powerful machine. Operating systems were
developed to manage and share the computing resources and time-sharing operating
systems were developed. These greatly improved the efficiency of computers.
Computers had by now pervaded most areas of business and administration. The
number of transistors that be fabricated on a chip is referred to as the scale of
integration (SI). Early chips had SSI (small SI) of tens to a few hundreds. Later chips
were MSI (Medium SI): hundreds to a few thousands. Then came LSI chips (Large
SI) in the thousands range.
4. Fourth Generation (1975-1984): VLSI (Very Large SI)
The term fourth generation is occasionally applied to VLSI-based computer
architecture. VLSI has made it possible to fabricate an entire CPU, main memory, or
similar devices with a single IC. This has resulted in new classes of machines such as
inexpensive personal computers, and high- performance parallel processors that
contain thousands of CPUs. VLSI allowed the equivalent of tens of thousand of
transistors to be incorporated on a single chip. This led to the development of the
microprocessor a processor on a chip. Intel produced the 4004 which was followed
by the 8008,8080, 8088 and 8086 etc. Other companies developing microprocessors
included Motorolla (6800, 68000), and Zilog. Personal computers were developed
and IBM launched the IBM PC based on the 8088 and 8086 microprocessors.
Mainframe computers have grown in power. Memory chips are in the megabyte
range. VLSI chips had enough transistors to build 20 ENIACs. Secondary storage has
also evolved at fantastic rates with storage devices holding gigabytes (1024Mb = 1
Gb) of data. On the software side, more powerful operating systems are available
such as Unix. Applications software has become cheaper and easier to use.

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Dr. Hadeel Nasrat
5. Fifth Generation (1991-Present):
The race is now on building the next or fifth generation of computers,
machine that exhibit artificial intelligence (AI). Thus new generations of computers
will involve robotics and computer networks. Developments are still continuing.
Computers are becoming faster, smaller and cheaper. Storage units are increasing in
capacity. Distributed computing is becoming popular and parallel computers with
large numbers of CPUs have been built.
Generation
Technology &
Architecture
Software &
Applications
Systems
First
(1945-54)
Vacuum tubes, Relay
memories, CPU driven by
PC and accumulator; fixed
point Arithmetic
Machine & Assembly
language, Single user
Basic I/O using
programmed and
Internet mode.
ENIAC TIFRAC
IBM 701
Princeton IAS
Second
(1955-64)
Discrete Transistors, Core
Memories, Floating point,
Arithmetic I/O, processors,
Multiplexed memory
access
HLL used with
compilers, batch
processing, Monitoring,
Libraries
IBM7099
CDC 1604
Third
(1965-74)
Integrated circuits,
Microprogramming,
Pipelining, Caching,
Lookahead Processing
Multiprogramming,
Time sharing OS,
Multi-user applications
IBM 360/700
CDC 6000
TA-ASC PDP-8
Fourth
(1975-84)
LSI/VLSI and
Semiconductor memory,
Microprocessors
technology,
Multiprocessors, vector
super-computing, multi
computer
Multiprocessor OS,
languages, Compilers
VAX 9800, Cray
X-MP, IBM
3600, Pentium
Processor based
systems (PCs),
UltraSPARC etc.
Fifth
(1991-
present)
VLSI/VHSIC processors,
scalable architecture
Massively parallel
processing, Grand
challenge Applications
Cray/MPP,
TMC/CM-5, Intel
paragon, Fujitsu
VP500

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Types of Computers
Computer now comes in a variety of shapes and sizes, which could be roughly
classified according to their processing power into five sizes: super large, large,
medium, small, and tiny.
Microcomputers are the type of computers that we are most likely to notice and use in
our everyday life. In fact there are other types of computers that you may use directly
or indirectly:
Supercomputers-super large computers: supercomputers are high- capacity
machines with hundreds of thousands of processors that can perform more than
1 trillion calculations per second. These are the most expensive but fastest
computers available. "Supers," as they are called, have been used for tasks
requiring the processing of enormous volumes of data, such as doing the U.S.
census count, forecasting weather, designing aircraft, modeling molecules,
breaking codes, and simulating explosion of nuclear bombs.
Mainframe computers - large computers: The only type of computer available
until the late 1960s, mainframes are water- or air-cooled computers that vary in
size from small, to medium, to large, depending on their use. Small
mainframes are often called midsize computers; they used to be called
minicomputers. Mainframes are used by large organizations such as
banks, airlines, insurance companies, and colleges-for processing millions of
transactions. Often users access a mainframe using a terminal, which has a
display screen and a keyboard and can input and output data but cannot by
itself process data.
Workstations - medium computer: Introduced in the early 1980s,
workstations, are expensive, powerful computers usually used for complex
scientific, mathematical, and engineering calculations and for computer-aided
design and computer-aided manufacturing. Providing many capabilities
comparable to midsize mainframes, workstations are used for such tasks as
designing airplane fuselages, prescription drugs, and movie special effects.
Workstations have caught the eye of the public mainly for their graphics
capabilities, which are used to breathe three-dimensional life into movies such
as Jurassic Park and Titanic. The capabilities of low-end workstations overlap
those of high-end desktop microcomputers.
Microcomputer - small computers: Microcomputers, also called personal
computers (PC), can fit next to a desk or on a desktop, or can be carried
around. They are either stand-alone machines or are connected to a computer
network, such as a local area network. A local area network (LAN) connects,
usually by special cable, a group of desktop PCs and other devices, such as
printers, in an office or a building. Microcomputers are of several types:
Desktop PCs: are those in which the case or main housing sits on a

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desk, with keyboard in front and monitor (screen) often on top.
Tower PCs: are those Microcomputer in which the case sits as a
"tower," often on the floor beside a desk, thus freeing up desk surface
space.
Laptop computers (also called notebook computers): are lightweight
portable computers with built-in monitor, keyboard, hard-disk drive,
battery, and AC adapter that can be plugged into an electrical outlet;
they weigh anywhere from 1.8 to 9 pounds.
Personal digital assistants (PDAs) (also called handheld computers or
palmtops) combine personal organization tools-schedule planners,
address books, to-do lists. Some are able to send e-mail and faxes. Some
PDAs have touch-sensitive screens. Some also connect to desktop
computers for sending or receiving information.
Microcontrollers-tiny computers: Microcontrollers, also called
embedded computers, are the tiny, specialized microprocessors installed
in "smart" appliances and automobiles. These microcontrollers enable
PDAs microwave ovens, for example, to store data about how long to
cook your potatoes and at what temperature.
Basic Blocks of a Microcomputer
If we think of the computer as an information manipulation device the basic
components of a microcomputer are:
Input Units -- "How to tell it what to do"
Devices allow us to enter information into the computer. A keyboard and
mouse are the standard way to interact with the computer. Other devices include
mice, scanners, microphones, joysticks and game pads used primarly for games.
Output Units -- "How it shows you what it is doing"
Devices are how the manipulated information is returned to us. They
commonly include video monitors, printers, and speakers.
Memory -- "How the processor stores and uses immediate data"

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When you use a program, the computer loads a portion of the program from
the hard drive to the much faster memory (RAM). When you "save" your work or
quit the program, the data gets written back to the hard drive.
Processor Central Processing Unit
Datapath - consists of register file and ALU
Register is a storage location. Used to hold data or a memory address
during execution of an instruction
ALU receives data from main memory and/or register file, performs
computations and writes result back to main memory or registers
Control unit decodes and monitors the execution of instructions and also acts
as an arbiter while various systems compete for resources of CPU.
Fig. (1): Basic Block of a Microcomputer

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Computer Architecture
In computer engineering, computer architecture is the conceptual design and
fundamental operational structure of a computer system. It is a blueprint and
functional description of requirements (especially speeds and interconnections) and
design implementations for the various parts of a computer focusing largely on the
way by which the central processing unit (CPU) performs internally and accesses
addresses in memory.
Computer architecture comprises at least three main subcategories
Instruction set architecture, or ISA, is the abstract image of a computing
system that is seen by a machine language (or assembly language)
programmer, including the instruction set, memory address modes, processor
registers, and address and data formats.
Microarchitecture, also known as Computer organization is a lower level,
more concrete, description of the system that involves how the constituent
parts of the system are interconnected and how they interoperate in order to
implement the ISA. The size of a computer's cache for instance, is an
organizational issue that generally has nothing to do with the ISA.
System Design which includes all of the other hardware components within a
computing system such as:
system interconnects such as computer buses and switches
memory controllers and hierarchies
CPU off-load mechanisms such as direct memory access issues like
multi-processing.
Once both ISA and microarchitecture has been specified, the actual device needs to
be designed into hardware. This design process is often called implementation.
Implementation is usually not considered architectural definition, but rather hardware
design engineering.
Computer Organization deals with the advances in computer architecture right from
the Von Neumann machines to the current day super scalar architectures.
Von Neumann Architecture
The earliest computing machines had fixed programs. Some very simple
computers still use this design, either for simplicity or training purposes. For
example, a desk calculator (in principle) is a fixed program computer. It can do basic
mathematics, but it cannot be used as a word processor or to run video games. To
change the program of such a machine, you have to re-wire, re-structure, or even re-
design the machine. Indeed, the earliest computers were not so much "programmed"

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as they were "designed". "Reprogramming", when it was possible at all, was a very
manual process, starting with flow charts and paper notes, followed by detailed
engineering designs, and then the often-arduous process of implementing the physical
changes.
The idea of the stored-program computer changed all that. By creating an
instruction set architecture and detailing the computation as a series of instructions
(the program), the machine becomes much more flexible. By treating those
instructions in the same way as data, a stored-program machine can easily change the
program, and can do so under program control.
The von Neumann architecture is a computer design model that uses a
processing unit and a single separate storage structure to hold both instructions and
data as shown in Fig. (2). It is named after mathematician and early computer
scientist John von Neumann. Such a computer implements a universal Turing
machine, and the common "referential model" of specifying sequential architectures,
in contrast with parallel architectures. The term "stored-program computer" is
generally used to mean a computer of this design, although as modern computers are
usually of this type, the term has fallen into disuse. All general-purpose computers
are now based on the key concepts of the von Neumann architecture.
Fig.(2): The Von-Neumann Architecture

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Though the von Neumann model is universal in general-purpose computing, it
suffers from one obvious problem. All information (instructions and data) must flow
back and forth between the processor and memory through a single channel, and this
channel will have finite bandwidth. When this bandwidth is fully used the processor
can go no faster. This performance limiting factor is called the von Neumann
bottleneck.
Hardvard Architecture
A Harvard Architecture as shown in Fig. (3) has one memory for instructions
and a second for data. The name comes from the Harvard Mark 1, an
electromechanical computer which pre-dates the stored-program concept of von
Neumann, as does the architecture in this form. It is still used for applications which
run fixed programs, in areas such as digital signal processing, but not for general-
purpose computing. The advantage is the increased bandwidth available due to
having separate communication channels for instructions and data; the disadvantage
is that the storage is allocated to code and data in a fixed ratio.
In Harvard architecture, there is no need to make the two memories share
characteristics. In particular, the word width, timing, implementation technology, and
memory address structure can differ. Instruction memory is often wider than data
memory. In some systems, instructions can be stored in read-only memory while data
memory generally requires read-write memory. In some systems, there is much more
instruction memory than data memory so instruction addresses are much wider than
data addresses.
Fig. (3): The Hardvard architecture

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A pure Harvard architecture computer suffers from the disadvantage that
mechanisms must be provided to separately load the program to be executed into
instruction memory and any data to be operated upon into data memory.
Additionally, modern Harvard architecture machines often use a read-only
technology for the instruction memory and read/write technology for the data
memory. This allows the computer to begin execution of a pre-loaded program as
soon as power is applied. The data memory will at this time be in an unknown state,
so it is not possible to provide any kind of pre-defined data values to the program.
The solution is to provide a hardware pathway and machine language
instructions so that the contents of the instruction memory can be read as if they were
data. Initial data values can then be copied from the instruction memory into the data
memory when the program starts. If the data is not to be modified (for example, if it
is a constant value, such as pi, or a text string), it can be accessed by the running
program directly from instruction memory without taking up space in data memory
(which is often at a premium).
For instance each port may be supplied from its own local cache memory (fig.
(4)). The cache memories reduce the external bandwidth requirements sufficiently to
allow them both to be connected to the same main memory, giving the bandwidth
advantage of a Harvard architecture along with most of the flexibility of the simple
von Neumann architecture. (The flexibility may be somewhat reduced because of
cache consistency problems with self-modifying code). Note that this type of
Harvard architecture is still a von Neumann machine.
The Modified Harvard architecture is very like the Harvard architecture but
provides a pathway between the instruction memory and the CPU that allows words
from the instruction memory to be treated as read-only data. This allows constant
data, particularly text strings, to be accessed without first having to be copied into
data memory, thus preserving more data memory for read/write variables. Special
machine language instructions are provided to read data from the instruction memory.

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Fig. (4): A modified Harvard Architecture

Microprocessors Architecture
Lecture Two-Page 1 of 10
Dr. Hadeel Nasrat

2.1 Microprocessor
A microprocessor is a computer processor on a microchip. It's sometimes called
a logic chip. It is the "engine" that goes into motion when you turn your computer on.
A microprocessor is designed to perform arithmetic and logic operations that make
use of small number-holding areas called registers. Typical microprocessor operations
include adding, subtracting, comparing two numbers, and fetching numbers from one
area to another. These operations are the result of a set of instructions that are part of
the microprocessor design. When the computer is turned on, the microprocessor is
designed to get the first instruction from the basic input/output system (BIOS) that
comes with the computer as part of its memory. After that, either the BIOS, or the
operating system that BIOS loads into computer memory, or an application program
is "driving" the microprocessor, giving it instructions to perform.
2.2 Evaluation of the Microprocessors
The evolution of microprocessors has been known to follow Moore's Law
when it comes to steadily increasing performance over the years. This law suggests
that the complexity of an integrated circuit, with respect to minimum component
cost, doubles every 18 months. This dictum has generally proven true since the early
1970s. From their humble beginnings as the drivers for calculators, the continued
increase in power has led to the dominance of microprocessors over every other form
of computer; every system from the largest mainframes to the smallest handheld
computers now uses a microprocessor at its core.
Intel 4004 was a 4 bit up. Only 45 instructions P Channel Mosfet technology. 50
K instructions per second (ENIAC).
Later 8008 as an 8 bit processor then 8080 and Motorolla 6800.
8080 was 10x faster than 8008 and TTL compatible.
MITS Altair 8800 in 1974. The BASIC Interpreter was written by Bill Gates.
Assembler program was written by Digital Research Corporation.
In 1977, 8085 microprocessor. Internal clock generator, higher frequency at
reduced cost and integration. There are 200 million 8085s around the world.

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In 1978, 8086+8088 microprocessors 16 bit. Addressed 1 Mbyte of memory.
Small instruction cache (4-6 bytes) enabled prefetch of instructions.
IBM decided to use 8088 in PC.
In 1983, 80286 released, identical to 8086 except the addressing and higher clock
speed.
32 bit microprocessor: In 1986 major overhaul on 80286 architecture, 80386 DX
with 32bit data + 32 bit address (4 G bytes).
In 1989, 80486 = 80386 + 80387 co processor + 8KB cache.
In 1993, Pentium (80586). Includes 2 execution engines.
Pentium Pro included 256K Level 2 cache mechanism as well as Level 1 cache.
Also 3 execution engines which can execute at the same time and can conflict and
still execute in parallel. The address bus was expended to 36.
Pentium 2 included L2 cache on its circuit board (called slot)
Later Pentium 3 and 4 released with several architectural and technological
innovations.
2.3 Block diagram of a simple CPU
As mentioned before, the microprocessor is the CPU of the microcomputer.
Therefore, the power of the microcomputer is determined by the capabilities of the
microprocessor. Its clock frequency determines the speed of the microcomputer. The
number of data and address pins on the microprocessor chip make up the
microcomputer's word size and maximum memory size. The microcomputer's I/O and
interfacing capabilities are determined by the control pins on the microprocessor chip.
The logic inside the microprocessor chip can be divided into three main areas:
the register section, the control unit, and the Arithmetic and Logic Unit (ALU). A
microprocessor chip with the above three sections is shown in Fig. (2.1).
A typical CPU has three major components: (1) register set, (2) arithmetic logic unit
(ALU), and (3) control unit (CU). The register set differs from one computer
architecture to another. It is usually a combination of general-purpose and special-
purpose registers. General-purpose registers are used for any purpose, hence the name
general purpose. Special-purpose registers have specic functions within the CPU.
For example, the program counter (PC) is a special-purpose register that is used to
hold the address of the instruction to be executed next. Another example of special-
purpose registers is the instruction register (IR), which is used to hold the instruction
that is currently executed. The ALU provides the circuitry needed to perform the
arithmetic, logical and shift operations demanded of the instruction set. In Chapter 4,

Dr. Hadeel Nasrat
we have covered a number of arithmetic operations and circuits used to support
computation in an ALU. The control unit is the entity responsible for fetching the
instruction to be executed from the main memory and decoding and then executing it.
Figure (2.1) shows the main components of the CPU and its interactions with the
memory system and the input/output devices.
The CPU fetches instructions from memory, reads and writes data from and to
memory, and transfers data from and to input/output devices. A typical and simple
execution cycle can be summarized as follows:
1. The next instruction to be executed, whose address is obtained from the PC, is
fetched from the memory and stored in the IR.
2. The instruction is decoded.
3. Operands are fetched from the memory and stored in CPU registers, if needed.
4. The instruction is executed.
5. Results are transferred from CPU registers to the memory, if needed.
Arithmetic Unit Control Unit
CCR
ACC
ALU
CL
IR
MDR
MAR
PC
Main memory Input/Output
Microprocessor
Fig. (2.1): Central processing unit main components and interactions with the
memory and I/O.

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The execution cycle is repeated as long as there are more instructions to execute. A
check for pending interrupts is usually included in the cycle. Examples of interrupts
include I/O device request, arithmetic overow, or a page fault.
When an interrupt request is encountered, a transfer to an interrupt handling routine
takes place. Interrupt handling routines are programs that are invoked to collect the
state of the currently executing program, correct the cause of the interrupt, and restore
the state of the program. The actions of the CPU during an execution cycle are
dened by micro-orders issued by the control unit. These micro-orders are individual
control signals sent over dedicated control lines. For example, let us assume that we
want to execute an instruction that moves the contents of register X to register Y.
Let us also assume that both registers are connected to the data bus, D. The control
unit will issue a control signal to tell register X to place its contents on the data bus D.
After some delay, another control signal will be sent to tell register Y to read from
data bus D. The activation of the control signals is determined using either hardwired
control or microprogramming. These concepts are explained later.
2.4 Register Set
The number, size, and types of registers vary from one microprocessor to
another. However, the various registers in all microprocessors carry out similar
operations. The register structures of microprocessors play a major role in designing
the microprocessor architectures. Also, the register structures for a specific
microprocessor determine how convenient and easy it is to program this
microprocessor.
2.4.1. Memory Access Registers
Two registers are essential in memory write and read operations: the memory
data register (MDR) and memory address register (MAR). The MDR and MAR are
used exclusively by the CPU and are not directly accessible to programmers. In order
to perform a write operation into a specied memory location, the MDR and MAR
are used as follows:
1. The word to be stored into the memory location is frst loaded by the CPU
intoMDR.
2. The address of the location into which the word is to be stored is loaded by the
CPU into a MAR.
3. A write signal is issued by the CPU.

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Similarly, to perform a memory read operation, the MDR and MAR are used as
follows:
1. The address of the location from which the word is to be read is loaded into the
MAR.
2. A read signal is issued by the CPU.
3. The required word will be loaded by the memory into the MDR ready for use by
the CPU.
2.4.2. Instruction Fetching Registers
Two main registers are involved in fetching an instruction for execution: the
program counter (PC) and the instruction register (IR). The PC is the register that
contains the address of the next instruction to be fetched. The fetched instruction is
loaded in the IR for execution. After a successful instruction fetch, the PC is updated
to point to the next instruction to be executed. In the case of a branch operation, the
PC is updated to point to the branch target instruction after the branch is resolved, that
is, the target address is known.
2.4.3. Condition Registers
Condition registers, or ags, are used to maintain status information. Some
architectures contain a special program status word (PSW) register. The PSW
contains bits that are set by the CPU to indicate the current status of an executing
program. These indicators are typically for arithmetic operations, interrupts, memory
protection information, or processor status.
2.4.4. Special-Purpose Address Registers
1. Index Register:
The address of the operand is obtained by adding a constant to the content of a
register, called the index register. The index register holds an address displacement.
Index addressing is indicated in the instruction by including the name of the index
register in parentheses and using the symbol X to indicate the constant to be added.
2. Segment Pointers:
In order to support segmentation, the address issued by the processor should
consist of a segment number (base) and a displacement (or an offset) within the
segment. A segment register holds the address of the base of the segment.

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3. Stack Pointer:
A stack is a data organization mechanism in which the last data item stored is
the rst data item retrieved. Two specific operations can be performed on a stack.
These are the Push and the Pop operations. A specic register, called the stack pointer
(SP), is used to indicate the stack locationm that can be addressed. In the stack push
operation, the SP value is used to indicate the location (called the top of the stack).
After storing (pushing) this value, the SP is incremented (in some architectures, e.g.
X86, the SP is decremented as the stack grows low in memory).
80386 Registers
The Intel basic programming model of the 386, 486, and the Pentium consists
of three register groups. These are the general-purpose registers, the segment
registers, and the instruction pointer (program counter) and the ag register. Fig. (2.2)
shows the three sets of registers. The rst set consists of general purpose registers A,
B, C, D, SI (source index), DI (destination index), SP (stack pointer), and BP (base
pointer). The second set of registers consists of CS (code segment), SS (stack
segment), and four data segment registers DS, ES, FS, and GS. The third set of
registers consists of the instruction pointer (program counter) and the ags (status)
register. Among the status bits, the rst ve are identical to those bits introduced as
early as in the 8085 8-bit microprocessor. The next 6 11 bits are identical to those
introduced in the 8086. The ags in the bits 12 14 were introduced in the 80286
while the 16 17 bits were introduced in the 80386. The ag in bit 18 was introduced
in the 80486.
Fig. (2.2): The main register sets in 80X86 (80386 and above
extended all 16 bit registers except segment registers).

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2.5 Arithmetic Logic Unit
In computing, an arithmetic logic unit (ALU) is a digital circuit that performs
arithmetic and logical operations. The ALU is a fundamental building block of the
central processing unit of a computer, and even the simplest microprocessors contain
one for purposes such as maintaining timers. The processors found inside modern
CPUs and GPUs have inside them very powerful and very complex ALUs; a single
component may contain a number of ALUs.
An ALU must process numbers using the same format as the rest of the digital
circuit. For modern processors, that almost always is the two's complement binary
number representation. Early computers used a wide variety of number systems,
including one's complement, sign-magnitude format, and even true decimal systems,
with ten tubes per digit.
Most of the computers actions are performed by the ALU. The ALU gets data from
processor registers. This data is processed and the results of this operation are stored
into ALU output registers. Other mechanisms move data between these registers and
memory. Most ALUs can perform the following operations:
Integer arithmetic operations (addition, subtraction, and sometime
multiplication and division, though this is more expensive)
Bitwise logic operations (AND, NOT, OR, XOR)
Bit-shifting operations (shifting or rotating a word by a specified number of
bits to the left or right, with or without sign extension). Shifts can be
interpreted as multiplications by 2 and divisions by 2.
2.6 Datapath
The CPU can be divided into a data section and a control section. The data
section, which is also called the datapath, contains the registers and the ALU. The
datapath is capable of performing certain operations on data items. The control
section is basically the control unit, which issues control signals to the datapath.
Internal to the CPU, data move from one register to another and between ALU and
registers.
Internal data movements are performed via local buses, which may carry data,
instructions, and addresses. Externally, data move from registers to memory and I/O
devices, often by means of a system bus. Internal data movement among registers and

Dr. Hadeel Nasrat
between the ALU and registers may be carried out using different organizations
including one-bus, two-bus, or three-bus organizations. Dedicated datapaths may also
be used between components that transfer data between themselves more frequently.
For example, the contents of the PC are transferred to the MAR to fetch a new
instruction at the beginning of each instruction cycle. Hence, a dedicated datapath
from the PC to the MAR could be useful in speeding up this part of instruction
execution.
2.6.1. One-Bus Organization
Using one bus, the CPU registers and the ALU use a single bus to move outgoing
and incoming data. Since a bus can handle only a single data movement within one
clock cycle, two-operand operations will need two cycles to fetch the operands for the
ALU. Additional registers may also be needed to buffer data for the ALU.
This bus organization is the simplest and least expensive, but it limits the amount
of data transfer that can be done in the same clock cycle, which will slow down the
overall performance. Figure (2.3) shows a one-bus datapath consisting of a set of
general-purpose registers, a memory address register (MAR), a memory data register
(MDR), an instruction register (IR), a program counter (PC), and an ALU.
2.6.2. Two-Bus Organization
Using two buses is a faster solution than the one-bus organization. In this case,
general-purpose registers are connected to both buses. Data can be transferred from
Fig. (2.3): One-Bus Datapath.

Dr. Hadeel Nasrat
two different registers to the input point of the ALU at the same time. Therefore, a
two-operand operation can fetch both operands in the same clock cycle. An additional
buffer register may be needed to hold the output of the ALU when the two buses are
busy carrying the two operands. Figure (2.4a) shows a two-bus organization. In some
cases, one of the buses may be dedicated for moving data into registers (in-bus),
while the other is dedicated for transferring data out of the registers (out-bus). In this
case, the additional buffer register may be used, as one of the ALU inputs, to hold one
of the operands. The ALU output can be connected directly to the in-bus, which will
transfer the result into one of the registers. Figure (2.4b) shows a two-bus
organization with in-bus and out-bus.
Fig. (2.4): Two-bus organizations. (a) An Example of Two-Bus Datapath.
(b) Another Example of Two-Bus Datapath with in-bus and out-bus
.
(a)
(b)

Dr. Hadeel Nasrat
2.6.3. Three-Bus Organization
In a three-bus organization, two buses may be used as source buses while the
third is used as destination. The source buses move data out of registers (out-bus), and
the destination bus may move data into a register (in-bus). Each of the two out-buses
is connected to an ALU input point. The output of the ALU is connected directly to
the in-bus. As can be expected, the more buses we have, the more data we can move
within a single clock cycle. However, increasing the number of buses will also
increase the complexity of the hardware. Figure (2.5) shows an example of a three-
bus datapath.
Fig. (2.5): Three-Bus Datapath.

Lecture Three-Page 1 of 10
Dr. Hadeel Nasrat
3.1 CPU INSTRUCTION CYCLE
The sequence of operations performed by the CPU during its execution of
instructions is presented in Fig. (3.1). As long as there are instructions to execute, the
next instruction is fetched from main memory. The instruction is executed based on
the operation specied in the opcode eld of the instruction. At the completion of the
instruction execution, a test is made to determine whether an interrupt has occurred.
An interrupt handling routine needs to be invoked in case of an interrupt.
The basic actions during fetching an instruction, executing an instruction, or
handling an interrupt are defined by a sequence of micro-operations. A group of
control signals must be enabled in a prescribed sequence to trigger the execution of a
micro-operation. In this section, we show the micro-operations that implement
instruction fetch, execution of simple arithmetic instructions, and interrupt handling.
3.1.1 Fetch Instructions
The sequence of events in fetching an instruction can be summarized as follows:
1. The contents of the PC are loaded into the MAR.
2. The value in the PC is incremented. (This operation can be done in parallel with a
memory access).
Fig. (3.1): CPU Functions.

Dr. Hadeel Nasrat
3. As a result of a memory read operation, the instruction is loaded into the MDR.
4. The contents of the MDR are loaded into the IR.
Let us consider the one-bus datapath organization shown in Fig. (2.3). We will
see that the fetch operation can be accomplished in three steps as shown in the table
below, where t0 < t1 < t2 . Note that multiple operations separated by ; imply that
they are accomplished in parallel.
Step Micro-Operation
t
0
MAR (PC); A (PC)
t
1
MDR Mem MAR; PC (A)+4
t
2
IR (MDR)
using the three-bus datapath shown in Fig. (2.5), the following table shows the steps
needed.
t
0
MAR (PC); A (PC)+4
t
1
MDR Mem MAR;
t
2
IR (MDR)
3.1.2 Execute Simple Arithmetic Operation
Add R
1
, R
2
, R
0
: This instruction adds the contents of source registers R
1
and R
2
, and
stores the results in destination register R
0
. This addition can be executed as follows:
1. The registers R
0
, R
1
, R
2
are extracted from the IR.
2. The contents of R
1
and R
2
are passed to the ALU for addition.
3. The output of the ALU is transferred to R
0
.
Using the one-bus datapath shown in Fig. (2.3), this addition will take three steps as
shown in the following table, where t
0
< t
1
< t
2
.

Dr. Hadeel Nasrat
t
0
A (R
1
)
t
1
B (R
2
)
t
2
R
0
(A)+(B)
Using the two-bus datapath shown in Fig. (2.4a), this addition will take two steps as
0
< t
1
.
t
0
A (R
1
) + (R
2
)
t
1
R
0
(A)
Using the two-bus datapath with in-bus and out-bus shown in Fig. (2.4b), this
addition will take two steps as shown in the following table, where t0 < t1 .
t
0
A (R
1
)
t
1
R
0
(A) + (R
2
)
Using the three-bus datapath shown in Fig. (2.5), this addition will take one steps as
shown in the following table.
t
0
R
0
(R
1
) + (R
2
)

Dr. Hadeel Nasrat
Add X, R
0
: This instruction adds the contents of memory location X to register R
0
and stores the result in R
0
. This addition can be executed as follows:
1. The memory location X is extracted from IR and loaded into MAR.
2. As a result of memory read operation, the contents of X are loaded into MDR.
3. The contents of MDR are added to the contents of R
0
.
Using the one-bus datapath shown in Fig. (2.3), this addition will take five steps as
0
< t
1
< t
2
< t
3
< t
4
.
t
0
MAR X
t
1
MDR Mem[MAR]
t
2
A (R
0
)
t
3
B (MDR)
t
4
R
0
(A)+(B)
Using the two-bus datapath shown in Fig. (2.4a), this addition will take four steps as
0
< t
1
< t
2
< t
3
.
t
0
MAR X
t
1
MDR Mem[MAR]
t
2
A (R
0
) + (MDR)
t
3
R
0
(A)

Dr. Hadeel Nasrat
Using the two-bus datapath with in-bus and out-bus shown in Fig. (2.4b), this
addition will take four steps as shown in the following table, where t
0
< t
1
< t
2
< t
3
.
t
0
MAR X
t
1
MDR Mem[MAR]
t
2
A (R
0
)
t
3
R
0
(A) + (MDR)
Using the three-bus datapath shown in Fig. (2.5), this addition will take three steps as
shown below, where t
0
< t
1
< t
2
.
t
0
MAR X
t
1
MDR Mem[MAR]
t
2
R
0
(R
0
) + (MDR)
3.1.3 Interrupt Handling
After the execution of an instruction, a test is performed to check for pending
interrupts. If there is an interrupt request waiting, the following steps take place:
1. The contents of PC are loaded into MDR (to be saved).
2. The MAR is loaded with the address at which the PC contents are to be saved.
3. The PC is loaded with the address of the rst instruction of the interrupt handling
routine.
4. The contents of MDR (old value of the PC) are stored in memory.

Dr. Hadeel Nasrat
The following table shows the sequence of events, where t
1
< t
2
< t
3
.
t
1
MDR PC
t
2
MAR
PC
Address1 (where to save PC);

Address 2 (interrupt handling routine)
t
3
Mem[MAR] (MDR)
3.2 Control Unit
Even though the datapath is capable of performing all the operations of the
microprocessor, it cannot, however, do it on its own. In order for the datapath to
execute the operations automatically, the control unit is required. The control unit,
also known as the controller, controls the operations of the datapath, and therefore,
the operations of the entire microprocessor.
The control unit is the main component that directs the system operations by
sending control signals to the datapath. These signals control the ow of data within
the CPU and between the CPU and external units such as memory and I/O. Control
buses generally carry signals between the control unit and other computer
components in a clock-driven manner. The system clock produces a continuous
sequence of pulses in a specied duration and frequency. A sequence of steps (t
0
, t
1
,
t
2
, where t
0
< t
1
< t
2
< ) are used to execute a certain instruction. The op-code
eld of a fetched instruction is decoded to provide the control signal generator with
information about the instruction to be executed. Step information generated by a
logic circuit module is used with other inputs to generate control signals. The signal
generator can be specied simply by a set of Boolean equations for its output in terms
of its inputs. Fig. (3.2) shows a block diagram that describes how timing is used in
generating control signals.

Dr. Hadeel Nasrat
There are mainly two different types of control units:
1. Microprogrammed.
2. Hardwired.
In microprogrammed control, the control signals associated with operations are
stored in special memory units inaccessible by the programmer as control words. A
control word is a microinstruction that species one or more micro-operations. A
sequence of microinstructions is called a microprogram, which is stored in a ROM or
RAM called a control memory CM.
In hardwired control, xed logic circuits that correspond directly to the Boolean
expressions are used to generate the control signals. Clearly hardwired control is
faster than microprogrammed control.
Fig. (3.2): Timing of control signals.

Dr. Hadeel Nasrat
However, hardwired control could be very expensive and complicated for
complex systems. Hardwired control is more economical for small control units. It
should also be noted that microprogrammed control could adapt easily to changes in
the system design. We can easily add new instructions without changing hardware.
Hardwired control will require a redesign of the entire systems in the case of any
change.
Example 1:
Let us revisit the add operation in which we add the contents of source registers
R
1
, R
2
, and store the results in destination register R
0
.We have shown earlier that this
operation can be done in one step using the three-bus datapath shown in Fig. (2.5).
Let us try to examine the control sequence needed to accomplish this addition at step
t
0
. Suppose that the op-code eld of the current instruction was decoded to Inst-x
type. First we need to select the source registers and the destination register, then we
select Add as the ALU function to be performed. The following table shows the
needed step and the control sequence.
Step
Instruction
Type
Micro-operation
Control
t
0
Ins-x
R
0
(R
1
) + (R
2
)
Select R
1
as source 1 on out-bus1 (R
1
out-bus1)
Select R
2
as source 2 on out-bus2 (R
2
out-bus2)
Select R
0
as destination on in-bus (R
0
in-bus)
Select the ALU function Add (Add)
Fig. (3.3) shows the signals generated to execute Inst-x during time period t
0
.
The
AND gate ensures that these signals will be issued when the op-code is decoded into
Inst-x and during time period t
0
. The signals (R
1
out-bus 1), (R
2
out-bus2), (R
0
in-bus),
and (Add) will select R1 as a source on out-bus1, R
2
as a source on out-bus2, R
0
as
destination on in-bus, and select the ALUs add function, respectively.

Dr. Hadeel Nasrat
Example 2 :
Let us repeat the operation in the previous example using the one-bus datapath
shown in Fig. (2.3). We have shown earlier that this operation can be carried out in
three steps using the one-bus datapath. Suppose that the op-code eld of the current
instruction was decoded to Inst-x type. The following table shows the needed steps
and the control sequence.
Step
Instruction
Type
Micro-operation
Control
t
0
Inst-x
A (R
1
)
Select R
1
as source (R
1
out)
Select A as destination (A in)
t
1
Inst-x
A (R
2
)
Select R
2
as source (R
2
out)
Select B as destination (B in)
t
2
Inst-x
R
0
(R
1
) + (R
2
)
Select the ALU function Add (Add).
Select Ro as destination (R
0
in)
Fig. (3.3): Signals generated to execute Inst-x on three-bus datapath
during time period t
0 .

Dr. Hadeel Nasrat
Fig. (3.4) shows the signals generated to execute Inst-x during time periods t
0
, t
1
, and
t
2
. The AND gates ensure that the appropriate signals will be issued when the op-code
is decoded into Inst-x and during the appropriate time period. During t
0
, the signals
(R
1
out) and (A in) will be issued to move the contents of R
1
into A. Similarly during
t
1
, the signals (R
2
out) and (B in) will be issued to move the contents of R
2
into B.
Finally, the signals (R
0
in) and (Add) will be issued during t
2
to add the contents of A
and B and move the results into R
0
.
Fig. (3.4): Signals generated to execute Inst-x on one-bus datapath
during time period t
0
, t
1
, t
2.

The 80386 Microprocessors
Lecture Four-Page 1 of 8
Dr. Hadeel Nasrat
3.1 Introduction
The 80386 microprocessor is a full 32-bit version of the earlier 8086/80286 16-
bit microprocessors, and represents a major advancement in the architecture, a switch
from a 16-bit architecture to a 32-bit architecture. Along with this larger word size are
many improvements and additional features. The 80386 microprocessor features
multitasking, memory management, virtual memory (with or without paging),
software protection, and a large memory system. All software written for the early
8086/8088 and the 80286 are upward-compatible to the 80386 microprocessor. The
amount of memory addressable by the 80386 is increased from the 1M bytes found in
the 8086/8088 and the 16M bytes found in the 80286, to 4G bytes in the 80386.
Before the 80386 or any other microprocessor can be used in a system, the
function of each pin must be understood. Figure (3-1a) illustrates the pin-out of the
80386DX microprocessor. The 80386DX is packaged in a 132-pin PGA (pin grid
array). Two versions of the 80386 are commonly available: the 80386DX, which is
illustrated and described in this section; the other is the 80386SX, which is a reduced
bus version of the 80386. A new version of the 80386-the 80386EX-incorporates the
AT bus system, dynamic RAM controller, programmable chip selection logic, 26
address pins, 16 data pins, and 24 I/O pins. Figure (3-1b) illustrates the 80386SX
embedded PC.
The 80386DX addresses 4G bytes of memory through its 32-bit data bus and
32-bit address. The 80386SX, more like the 80286, addresses 16M bytes of memory
with its 24-bit address bus via its 16-bit data bus. The 80386SX was developed after
the 80386DX for applications that didn't require the full 32-bit bus version. The
80386SX is found in many personal computers that use the same basic motherboard
design as the 80286. At the time that the 80386SX was popular, most applications,
including Windows, required fewer than 16M bytes of memory, so the 80386SX is a
popular and a less costly version of the 80386 microprocessor.

Dr. Hadeel Nasrat
A31-A2: Address bus connections address any of the 1Gx32 memory locations found
in the 80386 memory system. Note that A0 and A1 are encoded in the bus
enable ( 0 3 BE BE ) to select any or all of the four bytes in a 32-bit wide
memory location. Also note that because the 80386SX contains a 16-bit data
bus in place of the 32-bit data bus found on the 80386DX, A1 is present on the
80386SX, and the bank selection signals are replaced with BHE and BLE.
The BHE signal enables the upper data bus half; the BLE signal enables the
lower data bus half.
Fig. (3.1): The pin-outs of the 80386DX and 80386SX microprocessors.

Dr. Hadeel Nasrat
D31-D0: Data bus connections transfer data between the microprocessor and its
memory and I/O system. Note that the 80386SX contains D15-DO.
0 3 BE BE : Bank enable signals select the access of a byte, word, or double word
of data. These signals are generated internally by the microprocessor from
address bits A1 and A0. On the 80386SX, these pins are replaced by BHE ,
BLE, and A1.
IO M/ : Memory/IO selects a memory device when a logic 1 or an I/O device when a
logic 0. During the I/O operation, the address bus contains a 16-bit I/O address
on address connections A15-A2.
R W / : Write/read indicates that the current bus cycle is a write when a logic 1 or a
read when a logic 0.
ADS : The address data strobe becomes active whenever the 80386 has issued a
valid memory or I/O address. This signal is combined with the R W / signal to
generate the separate read and write signals present in the earlier 8086-80286
microprocessor-based systems.
RESET: Reset initializes the 80386, causing it to begin executing software at
memory location FFFFFFF0H. The 80386 is reset to the real mode, and the
leftmost 12 address connections remain logic 1s (FFFH) until a far jump or far
call is executed. This allows compatibility with earlier microprocessors.
CLK2: Clock times 2 is driven by a clock signal that is twice the operating frequency
of the 80386. For example, to operate the 80386 at 16 MHz, we apply a 32
MHz clock to this pin.
READY : Ready controls the number of wait states inserted into the timing to
lengthen memory accesses. .
LOCK : Lock becomes a logic 0 whenever an instruction is prefixed with the
LOCK:prefix. This is used most often during DMA accesses.

Dr. Hadeel Nasrat
C D/ : Data/control indicates that the data bus contains data for or from memory or
I/O when a logic 1. If C D/ is a logic 0, the microprocessor is halted or
executes an interrupt acknowledge.
16 BS : Bus size 16 selects either a 32-bit data bus ( 16 BS = 1) or a 16-bit data bus
( 16 BS =0). In most cases, if an 80386DX is operated on a 16-bit data bus, we
use the 80386SX that has a 16-bit data bus.
NA: Next address causes the 80386 to output the address of the next instruction or
data in the current bus cycle. This pin is often used for pipelining the address.
HOLD: Hold requests a DMA action.
HLDA: Hold acknowledge indicates that the 80386 is currently in a hold condition.
PEREQ: The coprocessor request asks the 80386 to relinquish control and is a
direct connection to the 80387 arithmetic coprocessor.
BUSY : Busy is an input used by the WAIT or FWAIT instruction that waits for the
coprocessor to become not busy. This is also a direct connection to the 80387
from the 80386.
ERROR: Error indicates to the microprocessor that an error is detected by the
coprocessor.
INTR: An interrupt request is used by external circuitry to request an interrupt.
NMI: A non-maskable interrupt requests a non-maskable interrupt as it did on the
earlier versions of the microprocessor.
3.2 Internal Architecture of the 80386DX Microprocessor
The internal architecture of the 8086 family of microprocessors has changed a
lot as part of the evolutionary process from the original 8086 to the 80386. All
members of the 8086 family employ what is called parallel processing. That is, they
are implemented with simultaneously operating multiple processing units. Each unit

Dr. Hadeel Nasrat
has a dedicated function and they operate at the same time. The more the parallel
processing, the higher the performance of the microprocessor.
The 8086 microprocessor contains just two processing units: the bus interface
unit and execution unit. In the 80286 microprocessor, the internal architecture was
further partitioned into four independent processing elements: the bus unit, the
instruction unit, the execution unit, and the address unit. This additional parallel
processing provided an important contribution to the higher level of performance
achieved with the 80286, architecture.
The 80386DX's internal architecture: is illustrated in Fig. (3.2). Here we see
that to enhance the performance, more parallel processing elements are provided.
Notice that now there are six functional units: the execution unit, the segment unit,
the page unit, the bus unit, the prefetch unit, and the decode unit. Let us now look
more closely at each of the processing units of the 80386DX.
The bus unit is the 80386DX's interface to the outside world. By interface, we
mean the path by which it connects to external devices. The bus interface provides a
32-bit data bus, a 32-bit address bus, and the signals needed to control transfers over
the bus. In fact, 8-bit, l6-bit, and 32-bit data transfers are supported. These buses are
demultiplexed like those of the 80286. That is, the 80386DX has separate pins for its
address and data bus lines. This demultiplexing of address and data results in higher
performance and easier hardware design. Expanding the data bus width to 32 bits
further improves the performance of the 80386DX's hardware architecture as
compared to that of either the 8086 or 80286.
The bus unit is responsible for performing all external bus operations. This
processing unit contains the latches and drivers for the address bus, transceivers for
the data bus and control logic for signaling whether a memory, input/output or
interrupt-acknowledg bus cycle is being performed. Looking at Fig. (3.2), we find
that for data accesses, the address of the storage location that is to be accessed is input

Dr. Hadeel Nasrat
from the paging unit, and for code accesses the address is provided by the prefetch
unit.
The prefetch unit implements a mechanism known as an instruction stream
queue. This queue permits the 80386DX to prefetch up to 16 bytes of instruction
code. Whenever the queue is not full-that is, it has room for at least 4 more bytes and,
at the same time, the execution unit is not asking it to read or write operands from
memory-the prefetch unit supplies addresses to the bus interface unit and signals it to
look ahead in the program by fetching the next sequential instructions. Prefected
instructions are held in the FIFO queue for use by the instruction decoder. Whenever
bytes are loaded at the input end of the queue, they are automatically shifted up
through the FIFO to the empty locations near the output. With its 32-bit data bus. the
80386DX fetches 4 bytes of instruction code in a single memory cycle. Through this
prefetch mechanism, the fetch time for most instructions is hidden. If the queue in the
prefetch unit is full and the execution unit is not requesting access to operands in
memory the bus interface unit does not need to perform any bus cycle.
The execution unit includes the arithmetic/logic unit (ALU), the 80386DX's
registers, special multiply, divide, and shift hardware, and a control ROM. By
registers, we mean the 80386DX's general-purpose registers, such as EAX, EBX, and
ECX. The control ROM contains the microcode sequences that define the operation
performed by each of the 80386DX's machine code instructions. The execution unit
reads decoded instructions from the instruction queue and performs the operations
that they specify. It is the ALU that performs the arithmetic, logic, and shift
operations required by an instruction. If necessary, during the execution of an
instruction, it requests the segment and page units to generate operand addresses and
the bus interface unit to perform read or write bus cycles to access data in memory or
I/O devices. The extra hardware that is provided to perform multiply, divide, shift,
and rotate operations improves the performance of instructions that employ these

Dr. Hadeel Nasrat
functions.
The segment and page units provide the memory-management and protection
services for the 80386DX. They off-load the responsibility for address generation,
address translation, and segment checking from the bus interface unit, thereby further
boosting the performance of the MPU. The segment unit implements the
segmentation model of the 80386DX's memory management. That is, it contains
dedicated hardware for performing high-speed address calculations, logical-to-linear
address translation, and protection check. For instance, when in the real mode, the
execution unit requests the segment unit to obtain the address of the next instruction
to be fetched by adding an appended version of the current contents of the code
segment (CS) register with the value in the instruction pointer (IP) register to obtain
the 20-bit physical address that is to be output on the address bus. This address is
passed on to the bus unit.
For protected mode, the segment unit performs the logical-to-linear address
translation and various protection checks needed when performing bus cycles. It
contains the segment registers and the 6-wordx64-bit cache that is used to hold the
current descriptors within the 80386DX.
The page unit implements the protected mode paging model of the 80386DX's
memory management. It contains the translation lookaside buffer that stores recently
used page directory and page table entries. When paging is enabled, the linear address
produced by the segment unit is used as the input of the page unit. Here the linear
address is translated into the physical address of the memory or I/O location to be
accessed. This physical memory or I/O address is output to the bus interface unit.

Dr. Hadeel Nasrat

Software Model of the 80386DX
Microprocessor
Lecture Five-Page 1 of 8
Dr. Hadeel Nasrat
SOFTWARE MODEL OF THE 80386DX
MICROPROCESSOR
The purpose of a software model is to aid the programmer in understanding
the operation of the microcomputer system from a software point of view. To be
able to program a microprocessor, one does not necessarily need to know all its
hardware architecture features. For instance, we do not need to know the function of
the signals at its various pins, their electrical connections, or their electrical
switching characteristics. The function interconnection, and operation of the internal
circuits of the microprocessor also need not normally be considered. What is
important to the programmer is to know the various registers within the device and
to understand their purpose, functions, operating capabilities, and limitations.
Furthermore, it is essential to know how external memory is organized and
how it is accessed to obtain instructions and data.
4.1 Memory Organization and Segmentation
The physical memory of an 80386 system is organized as a sequence of 8-bit
bytes. Each byte is assigned a unique address that ranges from zero to a maximum of
232-1 (4 gigabytes). 80386 programs, however, are independent of the physical
address space. This means that programs can be written without knowledge of how
much physical memory is available and without knowledge of exactly where in
physical memory the instructions and data are located.
The model of memory organization seen by applications programmers is determined
by systems-software designers. The architecture of the 80386 gives designers the
freedom to choose a model for each task. The model of memory organization can
range between the following extremes:
A "flat" address space consisting of a single array of up to 4 gigabytes.
A segmented address space consisting of a collection of up to 16,383 linear
address spaces of up to 4 gigabytes each.
With the flat memory model (see Figure 4-1), memory appears to a program as a
single, continuous address space, called a linear address space. Code (a programs
instructions), data, and the procedure stack are all contained in this address space.
The linear address space is byte addressable, with addresses running contiguously

Microprocessor
Dr. Hadeel Nasrat
from 0 to 232 - 1. An address for any byte in the linear address space is called a
linear address.
Fig. (4.1): Three Memory Management Models
`
With the segmented memory model, memory appears to a program as a group
of independent address spaces called segments. When using this model, code, data,
and stacks are typically contained in separate segments. To address a byte in a
segment, a program must issue a logical address, which consists of a segment selector
and an offset. (A logical address is often referred to as a far pointer.) The segment
selector identifies the segment to be accessed and the offset identifies a byte in the
address space of the segment. The programs running on an Intel Architecture

Microprocessor
Dr. Hadeel Nasrat
processor can address up to 16,383 segments of different sizes and types, and each
segment can be as large as 232 bytes.
The real-address mode model uses the memory model for the Intel 8086 processor,
the first Intel Architecture processor. It was provided in all the subsequent Intel
Architecture processors for compatibility with existing programs written to run on the
Intel 8086 processor. The real address mode uses a specific implementation of
segmented memory in which the linear address space for the program and the
operating system/executive consists of an array of segments of up to 64K bytes in
size each. The maximum size of the linear address space in real-address mode is 220
bytes.
4.2. REGISTERS
The processor provides 16 registers for use in general system and application
programing. These registers can be grouped as follows:
1. General-purpose data registers. These eight registers are available for storing
operands and pointers.
2. Segment registers. These registers hold up to six segment selectors.
3. Status and control registers. These registers report and allow modification of
the state of the processor and of the program being executed.
4.2.1. General-Purpose Data Registers
The 32-bit general-purpose data registers EAX, EBX, ECX, EDX, ESI, EDI, EBP,
and ESP are provided for holding the following items:
Operands for logical and arithmetic operations
Operands for address calculations
Memory pointers.
Although all of these registers are available for general storage of operands, results,
and pointers, caution should be used when referencing the ESP register. The ESP
register holds the stack pointer and as a general rule should not be used for any other
purpose. Many instructions assign specific registers to hold operands. For example,
string instructions use the contents of the ECX, ESI, and EDI registers as operands.
When using a segmented memory model, some instructions assume that pointers in
certain registers are relative to specific segments. For instance, some instructions
assume that a pointer in the EBX register points to a memory location in the DS
segment.
The following is a summary of these special uses:
EAXAccumulator for operands and results data.
EBXPointer to data in the DS segment.

Microprocessor
Dr. Hadeel Nasrat
ECXCounter for string and loop operations.
EDXI/O pointer.
ESIPointer to data in the segment pointed to by the DS register; source pointer
for string operations.
EDIPointer to data (or destination) in the segment pointed to by the ES register;
destination pointer for string operations.
ESPStack pointer (in the SS segment).
EBPPointer to data on the stack (in the SS segment).
Fig. (4.2): Alternate General-Purpose Register Names
4.2.2. Segment Registers
The segment registers (CS, DS, SS, ES, FS, and GS) hold 16-bit segment
selectors. A segment selector is a special pointer that identifies a segment in memory.
When using the segmented memory model, each segment register is ordinarily loaded
with a different segment selector so that each segment register points to a different
segment within the linear-address space (as shown in Figure 4-3).
Code segment (CS) is a 16-bit register containing address of 64 KB segment
with processor instructions. The processor uses CS segment for all accesses to
instructions referenced by instruction pointer (IP) register. CS register cannot be
changed directly. The CS register is automatically updated during far jump, far call
and far return instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment
with program stack. By default, the processor assumes that all data referenced by the
stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS
register can be changed directly using POP instruction.

Microprocessor
Dr. Hadeel Nasrat
Data segment (DS) is a 16-bit register containing address of 64KB segment
with program data. By default, the processor assumes that all data referenced by
general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data
segment. DS register can be changed directly using POP and LDS instructions.
Extra segment (ES) is a 16-bit register containing address of 64KB segment,
usually with program data. By default, the processor assumes that the DI register
references the ES segment in string manipulation instructions. ES register can be
changed directly using POP and LES instructions.
Figure (4-3): Use of Segment Registers in Segmented Memory Model
4.2.3. EFLAGS Register
The 32-bit EFLAGS register contains a group of status flags, a control flag, and a
group of system flags. Figure (4-4) defines the flags within this register. Some of the
flags in the EFLAGS register can be modified directly, using special-purpose
instructions (described in the following sections). There are no instructions that allow
the whole register to be examined or modified directly.
When a call is made to an interrupt or exception handler procedure, the processor
automatically saves the state of the EFLAGS registers on the procedure stack. When

Microprocessor
Dr. Hadeel Nasrat
an interrupt or exception is handled with a task switch, the state of the EFLAGS
register is saved in the TSS for the task being suspended.
S Indicates a Status Flag
C Indicates a Control Flag
X Indicates a System Flag
Figure (4-4): EFLAGS Register
STATUS FLAGS
The status flags (bits 0, 2, 4, 6, 7, and 11) of the EFLAGS register indicate the
results of arithmetic instructions, such as the ADD, SUB, MUL, and DIV
instructions. The functions of the status flags are as follows:
CF (bit 0) Carry flag: Set if an arithmetic operation generates a carry or a borrow
out of the most-significant bit of the result; cleared otherwise. This flag indicates an
overflow condition for unsigned-integer arithmetic. It is also used in multiple-
precision arithmetic.
PF (bit 2) Parity flag: Set if the least-significant byte of the result contains an even
number of 1 bits; cleared otherwise.

Microprocessor
Dr. Hadeel Nasrat
AF (bit 4) Adjust flag: Set if an arithmetic operation generates a carry or a borrow
out of bit 3 of the result; cleared otherwise. This flag is used in binarycoded decimal
(BCD) arithmetic.
ZF (bit 6) Zero flag: Set if the result is zero; cleared otherwise.
SF (bit 7) Sign flag: Set equal to the most-significant bit of the result, which is the
sign bit of a signed integer. (0 indicates a positive value and 1 indicates a negative
value.)
OF (bit 11) Overflow flag: Set if the integer result is too large a positive number or
too small a negative number (excluding the sign-bit) to fit in the destination operand;
cleared otherwise. This flag indicates an overflow condition for signed-integer (twos
complement) arithmetic.
Control Flags
DF (bit 10) Direction flag: Controls the string instructions (MOVS, CMPS, SCAS,
LODS, and STOS). Setting the DF flag causes the string instructions to auto
decrement (that is, to process strings from high addresses to low addresses). Clearing
the DF flag causes the string instructions to auto-increment (process strings from low
addresses to high addresses). The STD and CLD instructions set and clear the DF
flag, respectively.
TF (bit 8) Trap flag: Set to enable single-step mode for debugging; clear to disable
single-step mode.
IF (bit 9) Interrupt enable flag: Controls the response of the processor to maskable
interrupt requests. Set to respond to maskable interrupts; cleared to inhibit maskable
interrupts.
System Flags and IOPL field
The system flags and IOPL field in the EFLAGS register control operating-
system or executive operations. They should not be modified by application
programs. The functions of the status flags are as follows:
IOPL (bits 12 and 13) I/O privilege level field: Indicates the I/O privilege level of
the currently running program or task. The current privilege level (CPL) of the
currently running program or task must be less than or equal to the I/O privilege level
to access the I/O address space. This field can only be modified by the POPF and
IRET instructions when operating at a CPL of 0.
NT (bit 14) Nested task flag: Controls the chaining of interrupted and called tasks.
Set when the current task is linked to the previously executed task; cleared when the
current task is not linked to another task.

Microprocessor
Dr. Hadeel Nasrat
RF (bit 16) Resume flag. Controls the processors response to debug exceptions.
VM (bit 17) Virtual-8086 mode flag. Set to enable virtual-8086 mode; clear to
return to protected mode.
AC (bit 18) Alignment check flag: Set this flag and the AM bit in the CR0 register
to enable alignment checking of memory references; clear the AC flag and/or the AM
bit to disable alignment checking.
VIF (bit 19) Virtual interrupt flag: Virtual image of the IF flag. Used in
conjunction with the VIP flag. (To use this flag and the VIP flag the virtual mode
extensions are enabled by setting the VME flag in control register CR4.)
VIP (bit 20) Virtual interrupt pending flag: Set to indicate to that an interrupt is
pending; clear when no interrupts are pending. (Software sets and clears this flag. The
processor only reads it.) Used in conjunction with the VIF flag.
ID (bit 21) Identification flag: The ability of a program to set or clear this flag
indicates support for the CPUID instruction.
TM-1
Microcomputer Block Diagram

CPU
RAM ROM
Int erf ace Circ uit r y
Peripher al Devices
Addre ss Bus
Da ta Bus
Control Bus
F1-1
TM-2
CPU Functional Units

CPU
Inst r uc t i on Reg i st er ( IR)
Pro gr am Count er ( PC)
Inst r uct ion Decode
and Con t r ol Unit
Ar i t h met i c an d
Logi c Uni t ( ALU)
Re gi st er 0
Re gi st er 1
Reg i st er n - 1
F1-2
TM-3
Opcode Fetch

RAM
N
Pr ogram
Count er
CPU
Addr ess Bus
Dat a Bus
Opcode
Inst ruct ion
Regist er
Opc ode
Clock
Read
Cont rol
Bus
N+2
N+1
N
N-1
F1-3
TM-4
Memory Maps

FFFF
7 0 1 2 3 4 5 6
0 00 0
6 5,5 3 5
0
Hexadec im al
Addr esses
Decimal
Addresses
1 Byt e
0 00 1
0 00 2
0 00 3
0 00 4
4
3
2
1
.
.
.

FFFF
0 000
4K ROM
16K RAM
44 K Em pt y
F000
EFFF
3FFF
4 000
F1-6/7
TM-5
16-Bit Addresses

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0
Bit 1 5 =
mos t -sign if i cant b it
(a )
(b )
1
0
0 1 1 1 0 0 1 1 1 1 0 0
1
1
9 C
F 3
Bit 0 =
least -si gn if icant bi t
F1-8
TM-6
The Development Cycle

Concept
Specify
software
Design
software
Edit Translat e
Preliminary
t est ing
Int egrate
and
verify
Product
Specify
hardware
Design
hardware
Build
prot otype
Preliminary
t est ing
1-11
TM-7
Steps in
the Development Cycle

Fact ory
mask
process
ROM
Simulat or
Sof t ware
simulat ion
Linker/
locat or
Assembler Edit or
List ing
f ile
( .LST)
List ing
f ile
( .MAP)
Absolut e
object
f ile
Object
f ile
(. OBJ)
Sourc e
f ile
(. SRC)
Legend:
Ut ilit y program or
dev elopment t ool
User f ile
Ex ec ut ion env ironment
(For absolut e f iles)
Emulat or
Hardw are
emulat ion
EPROM
Programm er
EPROM
Download/
t erminal
emulat e
OBJHEX
c onv er sion
Hex
f ile
(. HEX)
RAM
1-13
TM-8
Motorola S-records
S00900006D796E616D656F
S11320003C3C000A327C201661000020534666F4F2
S11320101E3C00E44E4E53636F7474204D61634B59
S10C2020656E7A6965200D0A0061
S113202A1E3C00F81019670000064E4E60F64E7505
S9030000FC
(a)

S1 1 3 2 0 0 0 3 C3 C0 0 0 A3 2 7 C2 0 1 6 6 1 0 0 0 0 2 0 5 3 4 6 6 6 F4 F2
Check sum
Dat a By t es
Load Addr ess
Byt e Count
Recor d Ty pe
(b)
1-14
TM-9
68000 Programmer's Model

D0
D1
D2
D3
D4
D5
D6
D7
3 1 1 6 1 5 8 7 0
A0
A1
A2
A3
A4
A5
A6
3 1 1 6 1 5 0
3 1
3 1
1 6 1 5 0
0
A7
A7
PC
0 1 5
User St ack Po int er ( USP)
Program Count er
SR St at us Reg ist er
Dat a
Regis t ers
Address
Regist ers
Sup erv isor St ac k Point er (SSP)
7 8
123
CCR
2 3 2 4
F2-1
TM-10
68000 Status Register

T S I 2 I 1 I 0 C V Z N X
1 5 1 3 1 0 9 8 4 3 2 1 0
Carry
Overf l ow
Zero
Negat ive
Sign Ex t end
Int er rupt Mask
Supervi sor St at e
Trac e Mode
User By t e
( Condit ion Code Regi st er ) Syst em Byt e
1 2 3
F2-4
TM-11
Condition Code Computation

V = Sm Dm Rm + Sm Dm Rm
= 0 0 + 0 0 + 0 0
= 0
= 0 0 0 + 1 1 1
= 1
00011001
01110000
1 1 1
+
10001001
Z = 0
N = 1
Rm = 1
Dm = 0
Sm = 0
C = Sm Dm + Rm Dm + Sm Rm
X = C = 0
F2-5
TM-12
68000 Memory Map
-- Byte View --

00 000 0
FFFFFF
1 By t e
( 8 bit s)
0 000 01
0 000 02
0 000 03
0 000 04
F2-7
TM-13
68000 Memory Map
-- Word View --

00 000 0
FFFFFE
1 Word ( 16 bit s)
0 000 02
0 000 04
By t e 1
Byt e 3
By t e 0
By t e 2
By t e 4
By t e 5
By t e FFFFFE
By t e FFFFFF
Not e:
Ev en by t es cor respond
t o up per byt es on t he
ex t ernal dat a bus. Od d
byt es c or r espond t o lo wer
byt es on t he ext er nal
dat a bus.
F2-8
TM-14
68000 Memory Map
-- Longword View --

n
n + 4
n + 8
Byt e n
Wo rd ad d ress: n
1 Lo ngw or d ( 32 bi t s )
Wor d a dd re ss: n + 4
Byt e n + 1 By t e n + 2
Wo rd ad dr ess: n + 2
By t e n + 3
Byt e n + 4 et c.
1 2 3 1 2 3
Lo ngword s
can b e at any
eve n add ress
F2-9
TM-15
68000 Addressing Modes
Mode
Assembler
Syntax
Effective Address
Generation
Data Register Direct
Address Register Direct
Dn
An
EA = Dn
EA = An
Absolute Short
Absolute Long
xxx.W or <xxx
xxx.L or >xxx
EA = (next word)
EA = (next two words)
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Register Indirect with Index & Offset
(An)
(An)+
-(An)
d16(An)
d8(An,Xn)
EA = (An)
EA = (An), An ` An + N
An ` An - N, EA = (An)
EA = (An) + d16
EA = (An) + (Xn) + d8
PC Relative with Offset
PC Relative with Index and Offset
d16(PC)
d8(PC,Xn)
EA = (PC) + d16
EA = (PC) + (Xn) + d8
Immediate #data DATA = next word(s)
Implied Register CCR, SR, USP,
SSP, PC
EA = CCR, SR, USP, SSP, PC
Notes:
EA = effective address
An = address register
Dn = data register
Xn = address or data register used as index register
CCR = condition code register
SR = status register
USP = user stack pointer
SSP = supervisor stack pointer
PC = program counter
( ) = contents of
d8 = 8-bit offset (displacement)
d16 = 16-bit offset (displacement)
N = 1 for byte, 2 for word, 4 for longword. (If An is the
stack pointer and the operand size is byte, N = 2 to
keep the stack pointer on a word boundary.)
` = is replaced by
T2-1
TM-16
Data Register Direct

Instruction: MOVE.B D0,D3
Register Contents
Before:....D0.....10204FFF
...........D3.....1034F88A
After:.....D0.....10204FFF
...........D3.....1034F8FF
Only bit s 0-7
af f ec t ed
F2-10
TM-17
Address Register Direct

Instruction: MOVEA.L A3,A0
Register Contents
Before: A0.....00200000
A3.....0004F88A
After: A0.....0004F88A
A3.....0004F88A
Move t o
ad dr ess r egist er
32 bit s are
m ov ed
F2-11
TM-18
Absolute Short

Instruction: MOVE.L #$1E,$800
**** MEMORY ****
Address Contents
Before: 000800 12
000801 34
000802 56
000803 78
After: 000800 00
000801 00
000802 00
000803 1E
32-bi t o perand siz e
mov es dat a t o f o ur
c onse cut iv e by t e
lo cat ion s
Dest i nat io n a ddressin g
mo de is absol ut e short
So urc e a ddressin g
mode i s i mme diat e
F2-13
TM-19
Absolute Long

Instruction: MOVE.B #$1E,$8F000
**** MEMORY ****
Address Contents
Before: 08F000 FF
After: 08F000 1E
Dest ina t io n ad dressin g
m od e i s a bso lut e lo ng
Op era nd siz e
is b yt e
F2-14
TM-20
Register Indirect

Instruction: MOVE.L D0,(A0)
**** MEMORY ****
Address Contents Registers
Before: 001000 55 A0 00001000
001001 02 D0 1043834F
001002 3F
001003 00
After: 001000 10 A0 00001000
001001 43 D0 1043834F
001002 83
001003 4F
A0 cont ai n s t h e
a ddr ess o f t h e
de st i n at i on
A l on g wor d i s wr i t t e n t o
ad dr e ss $0 0 1 0 0 0
A0 do es no t
ch ang e
F2-17
TM-21
Postincrement Address
Register Indirect

Instruction: MOVE.W (A5)+,D0
**** MEMORY ****
Before: 001000 45 A5 00001000
001001 67 D0 0000FFFF
001002 89
001003 AB
After: 001000 45 A5 00001002
001001 67 D0 00004567
001002 89
001003 AB
Address regi st er
incr ement ed by
number of by t es
m ov ed, 2
F2-18
TM-22
Predecrement Address
Register Indirect

Instruction: MOVE.W D0,-(A7)
**** MEMORY ****
Before: 001000 10 A7 00001002
001001 12 D0 00000143
001002 83
001003 47
After: 001000 01 A7 00001000
001001 43 D0 00000143
001002 83
001003 47
Address regist er
decrement ed by
number of by t es
m ov ed, 2
F2-19
TM-23
Register Indirect
With Offset

Instruction: MOVE.W 6(A0),D0
**** MEMORY ****
Before: 001026 07 A0 00001020
001027 BF D0 00000000
After: 001026 07 A0 00001020
001027 BF D0 000007BF
Address r egis t er
does not change
Ef f ect ive addr ess is
6 plus value in A0
F2-20
TM-24
Register Indirect
With Index and Offset

Instruction: MOVEA $10(A0,D0.L),A1
**** MEMORY ****
Before: 00101C EF A0 0000100A
00101D 10 A1 00000000
D0 00000002
After: 00101C EF A0 0000100A
00101D 10 A1 FFFFEF10
D0 00000002
Wo r d v al u e i s
sig n-e xt en ded
be cause d est i na t i on
is a n a ddr e ss r egi st e r
Ad dr ess r eg i st e r
Inde x r egi st er , 32 bi t s
No t e:
EA = $ 1 0 + $ 10 0A + $ 2 = $ 10 1 C
F2-22
TM-25
PC-Relative
With Offset

Instruction: MOVE.W $1020(PC),D5
**** MEMORY ****
Before: 001020 AB PC 00001000
001021 CD D5 12345678
After: 001020 AB PC 00001004
001021 CD D5 1234ABCD

Inst r uc t io n i s t wo
wo rds l ong , s o PC is
incr emen t ed b y f our
F2-23
TM-26
PC-Relative
With Index and Offset

Instruction: MOVE.W $1020(PC,D0.W),D5
**** MEMORY ****
Before: 001026 FE PC 00001000
001027 DC D0 ABCD0006
D5 12345678
After: 001026 FE PC 00001004
001027 DC D0 ABCD0006
D5 1234FEDC

Only low- order
16 bit s of D0 used
as index
F2-26
TM-27
Immediate

Instruction: MOVE.L #$1FFFF,D0
Register Contents
Before: D0 12345678
After: D0 0001FFFF
Immediat e dat a
f ol low
Base :
$ = hexadecim al
@ = oc t al
% = binary
& ( or not hing) = dec imal
' AB' = ASCII charact er s
F2-28
TM-28
68000 Signals

AS
R/ W
UDS
LDS
DTACK
BR
BG
BGACK
IPL0
IPL1
IPL2
Dat a Bus
Addr ess Bus A1 -A23
D0 -D1 5
Vc c (2 )
GND (2 )
CLK
FC0
FC1
FC2
E
VMA
VPA
BERR
RESET
HALT
6 8 0 0 0
Processor
St at us
MC680 0
Peripheral
Cont rol
Sy st em
Cont r ol
Asynchronous
Bus
Cont rol
Bus
Arbi t rat i on
Cont rol
Int errupt
Cont rol
F2-33
TM-29
Upper Data Strobe and
Lower Data Strobe

A 2 3
A1
A0
WORD/ BYTE
A2 3
A1
Int er nal
Signals
Bus
Si gnals
UDS
( ev en byt e)
LDS
( odd byt e)
WORD/ BYTE
1
0
0
A0
X
0
1
UDS
0
0
1
LDS
0
1
0
(b) ( a)
F2-34
TM-30
Decoding with
-UDS and -LDS

UDS
D8 -D15
A1 -A2 3
D0- D7
L DS
Ad dr ess Bus
Dat a Bus ( upp er by t e)
Dat a Bus ( l ow er by t e)
68 0 00
Addre ss
De co di ng
CS
Lo wer
RAM
CS
Up per
RAM
F2-36
TM-31
Generation of -DTACK

DTA CK
+5 V
10 K
Ad dress Bus
6 80 0 0
Addre ss
Decod ing
CS
RA M
74 07
Address
Decoding
CS
RAM
740 7
Fro m ot h er RAMs ,
ROMs, I/ O Dev ic es , et c.
F2-36
TM-32
Function Code Outputs
Function Code
FC2 FC1 FC0 Address Space Type
0 0 0 (Undefined, reserved)
0 0 1 User Data
0 1 0 User Program
1 0 1 Supervisor Data
1 1 0 Supervisor Program
1 1 1 CPU Space (Interrupt Acknowledge)
T2-3
TM-33
Read Cycle Timing

CLK
S0 S1 S2 S3 S4 S5 S6 S7
FC0 -FC2
A1 - A2 3
D8 - D1 5
D0 - D7
AS
UDS
LDS
DTACK
R/ W
DT ACK mu st b e
asse rt ed b ef or e t he en d
o f S4 , ot herwise wait
st at es ar e i n sert ed
Dat a l at che d i nt o
CPU at be gi nnin g
of S7
F2-39
TM-34
Write Cycle Timing

CLK
S0 S1 S2 S3 S4 S5 S6 S7
FC0 -FC2
A1 - A2 3
D8 - D1 5
D0 - D7
AS
LDS
DT ACK
R/ W
UDS
F2-40
TM-35
Data Movement Instructions
Instruction Operation
EXG Exchange registers
LEA Load effective address
LINK Link and allocate stack
MOVE Move source to destination
MOVEA Move source to address register
MOVEM Move multiple registers
MOVEP Move to peripheral
MOVEQ Move short data to destination
PEA Push effective address
UNLK Unlink stack
T3-3
TM-36
Integer Arithmetic Instructions
ADD Add source to destination
ADDA Add source to address register
ADDI Add immediate data to destination
ADDQ Add short data to destination
ADDX Add with extend bit to destination
CLR Clear operand
CMP Compare source to destination
CMPA Compare source to address register
CMPM Compare memory
DIVS Signed divide
DIVU Unsigned divide
EXT Sign extend
EXTB Sign extend byte
MULS Signed multiply
MULU Unsigned multiply
NEG Negate
NEGX Negate with extend
SUB Subtract source from destination
SUBA Subtract source from address register
SUBI Subtract immediate from destination
SUBQ Subtract short from destination
SUBX Subtract with extend bit from destination
T3-4
TM-37
CMP Example

01111010
01111010
00000000
123
Instruction: CMP.B #'z',D7
Register Contents
Before: D7 FFFFFF7A
SR 001F
After: D7 FFFFFF7A
SR 0014
Notes:
D7 also con t ains
ASCII cod e f or ' z'
A SCII co de f o r
' z ' i s $ 7 A
-
Z = 1
N = 0
V = 0 ( si gn bit d oe s not ch an ge)
C = 0 ( bo rrow not re qu ir ed )
X = 1 (no chan ge)
D7 do es no t
chang e
F3-5
TM-38
DIVS Example

Instruction: DIVS #-3,D7
Register Contents
Before: D7 0000000E
SR 001F
After: D7 0002FFFC
SR 0018
Notes: 14 / -3 = -4 with a remainder of 2
Dividend, 14
Div is or , - 3
Quot ient , -4
Remainder , 2
F3-8
TM-39
Boolean Instructions
AND AND source to destination
ANDI AND immediate data to destination
EOR Exclusive OR source to destination
EORI Exclusive OR immediate data to destination
NOT Complement destination
OR OR source to destination
ORI OR immediate data to destination
Scc Test condition codes and set operand
TST Test operand and set condition codes
T3-5
TM-40
EOR Example

1 2 3
Instruction: EOR.L D6,(A4)+
**** MEMORY ****
Before: 003100 AB A4 00003100
003101 CD D6 12345678
003102 EF SR 0000
003103 10
After: 003100 B9 A4 00003104
003101 F9 D0 12345678
003102 B9 SR 0008
003103 68
Notes:
Sour ce operand
A4 increment ed
by f our
Dest inat ion operand
ABCDEF10
12345678
B9F9B968
+
Z = 0
N = 1
V = C = 0 ( always)
X = not af f ect ed ( assume 0 )
F3-10
TM-41
Shift and Rotate Instructions
Instruction Operation Bit Movement
ASL Arithmetic shift left

0
X
C Op era n d
ASR Arithmetic shift right

X
C Op er a nd
LSL Logical shift left

X
0 C Ope ra nd
LSR Logical shift right

X
C 0 Op e ran d
ROL Rotate left

Op e ran d C
ROR Rotate right

C Op er an d
ROXL Rotate left with extend bit

Op e ran d C X
ROXR Rotate right with extend bit

Op era nd C X
SWAP Swap words of a longword

1 6 b i t s 1 6 b it s
T3-6
TM-42
ASR Example

0 00011010
00110100
Instruction: ASR.B D3,D2
Register Contents
Before: D3 00000002
D2 00000068
SR 001F
After: D3 00000002
D2 0000001A
SR 0000
Sh if t c ount in D3
Shif t dat a in D2
Notes:
01101000
1 2 3
C = X = 0
Z = 0
N = 0
V = 0 ( alway s)
Ari t hmet i c shi f t
right : sig n b it
d oes not chang e!
F3-11
TM-43
Bit Manipulation Instructions
BCHG Change bit
BCLR Clear bit
BSET Set bit
BTST Test bit
T3-7
TM-44
BTST Example

Instruction: BTST #7,D5
Register Contents
Before: D5 FFFFFF7F
SR 0000
After: D5 FFFFFF7F
SR 0004
Bi t 7 = 0
Z = 1
Test bi t 7 of D5
F3-12
TM-45
Binary-Coded Decimal Instructions
ABCD Add source to destination
NBCD Negate destination
SBCD Subtract source from destination
T3-8
TM-46
ABCD Example

Instruction: ABCD -(A3),-(A4)
**** MEMORY ****
Before: 00200E 98 A3 0000200F
00210E 54 A4 0000210F
SR 001F
After: 00200E 98 A3 0000200E
00210E 53 A4 0000210E
SR 0011
X = 1
9 8 + 5 4 + 1 = 1 5 3
( t he hu nd r ed s di g i t
i s st or e d i n C & X)
Bot h ad dr ess r eg i st e r s
d ecr emen t ed by on e
Ope r an d siz e
alwa ys by t e
Notes: 10011000
01010100
1
11101101
00000110
11110011
01100000
01010011
+
+
+
1
1 1
1 1 1
( ad d 0 6)
( X = 1 )
( ad d 6 0 )
Z = 0
C = X = 1
N = V = u nd e f i ned ( assum e 0 )
---XNZVC
00010001
1 2 3
F3-13
TM-47
Program Flow Instructions
Bcc Branch conditionally
BRA Branch always
BSR Branch to subroutine
DBcc Test, decrement, and branch
JMP Jump to address
JSR Jump to subroutine
NOP No operation
RTE
+ Return and deallocate stack
RTR Return and restore condition codes
RTS Return from subroutine
+
privileged instruction
T3-9
TM-48
BRA Example

Displacement = X
2052 + X = 20A0
X = 20A0 - 2052
= 4E
Instruction: BRA $20A0
**** MEMORY ****
Before: 002050 60 PC 00002050
002051 4E

After: 002050 60 PC 000020A0
002051 4E
Inst r uc t ion wor d
Branch of f s et , 8 bit s
Br anch dest inat ion
Notes:
F3-15
TM-49
BSR/RTS Example

BSR $ 4 0 F2
RTS
00 501 A
00 501 8
00 501 6
BSR $4 0 F2
F0 DA
6 1 0 0
MA IN
PROGRA M
0 040 F2
00 40FA 4 E75 RTS
SUBROUTINE
00 3 05 0
00 3 04 E
00 3 04 C
1 234
5 678
9 ABC
STA CK
PC
A 7
0 0 5 0 16
0 000 305 0
REGISTERS:
MEMORY:
BEFORE
00 5 01 A
00 5 01 8
00 5 01 6
BSR $40 F2
F0 DA
61 00
MAIN
PROGRAM
0 04 0 F2
00 4 0FA 4E75 RTS
SUBROUTINE
003 050
003 04E
003 04C
1 2 34
5 0 1A
0 0 00
STACK
PC
A7
0 04 0FA
0 00 0 3 04 C
REGISTERS:
MEMORY:
BEFORE
00 50 1A
00 50 18
00 50 16
BSR $4 0 F2
F0 DA
6 1 00
MA IN
PROGRA M
0 040 F2
00 40FA 4 E75 RTS
SUBROUTINE
00 3 05 0
00 3 04 E
00 3 04 C
1 234
5 01A
0 000
STA CK
PC
A 7
0 0 40 F2
0 000 304 C
REGISTERS:
MEMORY:
AFTER
00 5 01 A
00 5 01 8
00 5 01 6
BSR $40 F2
F0 DA
61 00
MAIN
PROGRAM
004 0F2
00 4 0FA 4E7 5 RTS
SUBROUTINE
003 050
003 04E
003 04C
1 23 4
5 01 A
0 00 0
STACK
PC
A7
0 05 01A
0 00 0 30 5 0
REGISTERS:
MEMORY:
AFTER
add re ss o f
i ns t ru ct ion
f oll owi ng BSR
ret ur n t o
i nst r uct ion
f ollowing BSR
A7
A 7
A 7
A 7
F3-16
TM-50
System Control Instructions
ANDI
++ AND immediate to status register/condition code register
CHK Trap on upper out-of-bounds operand
EORI
++ Exclusive OR immediate to status register/condition code
register
ILLEGAL Illegal instruction trap
MOVE
++ Move to/from status register/condition code register
ORI++ OR immediate to status register/condition code register
RESET
+ Assert RESET line
STOP
+ Stop processor
TAS Test and set operand
TRAP Trap unconditionally
TRAPV Trap on overflow
+
privileged instruction
++
privileged instruction if SR specified
T3-10
TM-51
TRAP Example

Instruction: TRAP #5
**** MEMORY ****
Before: 002FFA 12 PC 00002000
002FFB 34 A7' 00003000
002FFC 56 SR 001F
002FFD 78
002FFE 9A
002FFF BC
000094 00
000095 01
000096 80
000097 F0
After: 002FFA 00 PC 000180F0
002FFB 1F A7' 00002FFA
002FFC 00 SR 201F
002FFD 00
002FFE 20
002FFF 02
000094 00
000095 01
000096 80
000097 F0
Notes: Vector read from address $80 + (5 x 4) = $94
Sy st em
St a ck Point er
V ec t or f or
t rap 5
Sy st em
St a ck Point er
d ecr ement ed
by 6
Exc ept ion p ro cessing
begins at addr ess
$0 180 F0
Super vi sor St at e
b it = 1
PC sav ed on
sy st em st ack
SR save d on
syst em st ac k
V ec t o r
ad dr ess
f or t r ap 5
F3-18
TM-52
68000 Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Operation Word
(1st word specifies operation and addressing modes)
Immediate Operand
(if any, one or two words)
Source Effective Address Extension
Destination Effective Address Extension
F3-19
TM-53
Effective Address Encoding
T3-11
Addressing Mode Mode Bits Register Bits
Data Register Direct 000 register number
Address Register Direct 001 register number
Address Register Indirect 010 register number
Address Register Indirect with
Postincrement
011 register number
Predecrement
100 register number
Displacement
101 register number
Address Register Indirect with Index* 110 register number
Absolute Short 111 000
Absolute Long 111 001
Program Counter with Displacement 111 010
Program Counter with Index* 111 011
Immediate or Status Register 111 100
*
One extension word required
Two extension words required
For Immediate addressing, one or two extension words required
depending on the size of the operation
One extension word required; see Table C-4 for the encoding
TM-54
68000 Condition Code Encoding
Mnemonic Condition Encoding Test
T
true 0000 1
F
false 0001 0
HI high 0010

C
Z
LS low or same 0011 C+Z
CC(HS) carry clear 0100

C
CS(LO) carry set 0101 C
NE not equal 0110

Z
EQ equal 0111 Z
VC
overflow clear 1000

V
VS
overflow set 1001 V
PL plus 1010

N
MI minus 1011 N
GE
greater or equal 1100

N V + N
V
LT
less than 1101
N V + N V
GT
greater than 1110
N V Z +N V Z
LE
less or equal 1111
Z + N V + NV
Not available for Bcc instruction
Twos complement arithmetic

= Boolean AND
+ = Boolean OR
T3-12
TM-55
Opcode Map
Bits
15 through 12 Operation
0000 Bit Manipulation/MOVEP/Immediate
0001 Move Byte
0010 Move Long
0011 Move Word
0100 Miscellaneous
0101 ADDQ/SUBQ/Scc/DBcc
0110 Bcc/BSR
0111 MOVEQ
1000 OR/DIV/SBCD
1001 SUB/SUBX
1010 (Unassigned)
1011 CMP/EOR
1100 AND/MUL/ABCD/EXG
1101 ADD/ADDX
1110 Shift/Rotate
1111 (Unassigned)
T3-13
TM-56
Assembler Operation

A68 K PROG.SRC
PROG.OBJ
PROG.LST
Legend:
Ut ilit y p rogram
User f ile
A6 8 K PROG.SRC, PROG. LST , PROG.OBJ, X S
( a)
( b)
Command
Inp ut
f i le
List ing
out ut f ile
Object code
out put f ile
Assem bler
op t ions
F4-1
TM-57
Assembler Files

1 00001000.................ORG.....$1000
2 00001000.41F80800.PROG...LEA.....$800,A0
3 00001004.103C0032........MOVE.B..#50,D0
4 00001008.4247............CLR.W...D7
5 0000100A.DE58.....LOOP...ADD.W...(A0)+,D7
6 0000100C.5300............SUBQ.B..#1,D0
7 0000100E.60FE............BRA.....*
8 00001010.................END
ORG.....$1000
PROG LEA.....$800,A0
MOVE.B..#50,D0
CLR.W...D7
LOOP ADD.W...(A0)+,D7
SUBQ.B..#1,D0
BRA.....*
END
So u rce f i le A d d re ss Co n t e n t s
L ine nu mb e r
La b el
f ield
Mn e mo ni c
f ie l d
Op er an d
f i e ld
( a)
( b )
Sou r ce
f i le
L i st i n g
f i le
Com men t
f ield (e mpt y )
F4-2
TM-58
Listing Examples
1 00001000 ORG $1000
2 00001000 6006 BRA *+8 ;"*" location counter
3 00001002 60FE BRA * ;branch to itself
4 00001004 6000FFFE HERE BRA HERE ;branch to itself
5 00001008 181B MOVE.B (A3)+,D4 ;indirect addressing
6 00000064 COUNT EQU 100 ;equate symbol to value
7 0000100A 3A3C0064 MOVE.W #COUNT,D5 ;symbol as immed. data
8 0000100E 3A3C0064 MOVE.W #100,D5 ;decimal
9 00001012 3A3C0064 MOVE.W #$64,D5 ;hexadecimal
10 00001016 3A3C0064 MOVE.W #144Q,D5 ;octal (A68K format)
11 0000101A 3A3C0064 MOVE.W #%01100100,D5 ;binary
12 0000101E 3E3CFFFB MOVE.W #-5,D7 ;negative number, decimal
13 00001022 3E3CFFFB MOVE.W #$FFFB,D7 ;negative number, decimal
14 00001026 3A390000 MOVE $F000,D5 ;data address
0000102A F000
15 0000F000 PORT EQU $F000 ;equate symbol as address
16 0000102C 3A390000 MOVE PORT,D5 ;data address (symbol)
00001030 F000
17 00001032 4E71 BACK NOP ;code address (NOP =
18 00001034 4E71 NOP ; no operation)
19 00001036 67FA BEQ BACK
20 00001038 END
F4-4
TM-59
Assemble-Time Operators
Operator
Function Precedence Type
- Unary minus 1 Unary
.NOT. Logical NOT 1 Unary
.LOW. Low byte 1 Unary
.HIGH. High byte 1 Unary
.LWRD. Low word 1 Unary
.HWRD. High word 1 Unary
* Multiplication 3 Binary
/ Division 3 Binary
+ Addition 4 Binary
- Subtraction 4 Binary
.MOD. Modulo 3 Binary
.SHR. Logical shift right 3 Binary
.SHL. Logical shift left 3 Binary
.AND. Logical AND 5 Binary
.OR. Logical OR 6 Binary
.XOR. Logical XOR 6 Binary
.EQ.
Equal
7 Binary
.NE.
Not Equal
7 Binary
.GE.
Greater or equal
7 Binary
.LE.
Less or equal
7 Binary
.GT.
Greater than
7 Binary
.LT.
Less than
7 Binary
.UGT.
Unsigned greater than
7 Binary
.ULT.
Unsigned less than
7 Binary
Operators apply to A68K. Different assemblers may support different

operators.
Relational operators return 1s (true) or 0s (false).

T4-1
TM-60
Examples of
Assemble-Time Operators
1 00000064 COUNT EQU 100
2 00002000 ORG $2000
3 00002000 3A3CFFFF MOVE #-1,D5
4 00002004 3A3C0009 MOVE #4+50/10,D5
5 00002008 3A3C0001 MOVE #25.mod.6,D5
6 0000200C 3A3C0400 MOVE #$8000.shr.5,D5
7 00002010 3A3C0040 MOVE #$45&$F0,D5
8 00002014 3A3C0041 MOVE #.high.'AB',D5
9 00002018 3A3CFFFF MOVE #5.gt.4,D5
10 0000201C 3A3C0032 MOVE #COUNT/2,D5
11 00002020 END
F4-5
TM-61
Assembler Directives
Directive Operation Syntax
ORG set program origin ORG value
EQU equate value to symbol symbol EQU value
END end of source program END label
DC define data constant [label] DC number[,number][...]
DS define RAM storage [label] DS count
RSEG begin relocatable segment RSEG name
EXTERN define external symbol EXTERN symbol[,symbol][...]
PUBLIC define public symbol PUBLIC symbol[,symbol][...]
T4-2
TM-62
Listing Examples
Address Contents *************** CH4-6.SRC *********************
1 00001000 ORG $1000
2 00001000 1A3C0064 START MOVE.B #100,D5
3 00000064 COUNT EQU 100
4 00002000 ORG $2000
5 00002000 1A3C0064 HERE MOVE.B #COUNT,D5
6 0000000D CR EQU $0D define a symbol
7 00003000 ORG $3000 set origin
8 00003000 0005FFFF NUM DC 5,-1 word size default
9 00003004 05FF MORE DC.B 5,-1 byte size constants
10 00003006 4A4F484E NAME DC.B 'JOHN' ASCII string
11 0000300A 0D00 DC.B CR,0 CR is a symbol
12 00004001 ORG $4001
13 00004002 000F VALUE DC 15 decimal constant
14 00005000 ORG $5000
15 00005000 6100 DC.W 'a'
16 00000050 LENGTH EQU 80
17 00006000 ORG $6000
18 00006000 BUFFER DS.B LENGTH
19 00006050 TEMP DS.B 1
20 00007000 ORG $7000
21 00007000 7250 MOVE.L #LENGTH,D1 use R1 as counter
22 00007002 327C6000 MOVEA #BUFFER,A1 A1 points to buff
23 00007006 12FC0000 LOOP MOVE.B #0,(A1)+ clear location
24 0000700A 5301 SUBQ.B #1,D1 done?
25 0000700C 66F8 BNE LOOP no: clear again
26 00000000 RSEG EPROM
27 00000000 1A3C002C BEGIN MOVE.B #44,D5
28 00000004 END
F4-8
TM-63
Linker Operation

XLINK
PROG.HEX
PROG. MA P
Le gend :
Ut i l i t y pr o g r a m
Us er f i l e
FILE1 . OB J
FIL E2 .OBJ
FILE3 . OB J
FILE4 . OBJ
XLINK 6 8 K FILE1 .OBJ FILE2.OBJ FILE3.OBJ FILE4 .OBJ / O= PROG.HEX M=PROG.MA P
( a)
( b)
Co mman d
CPU
In p ut
f i l e s
A bso l u t e
o u t p u t f i l e
f o r mat t e d
i n S- r eco r d s
L i st in g
f il e
Opt i o ns
f o l l o w
F4-10
TM-64
User Mode vs. Supervisor Mode
Feature User Mode Supervisor Mode
Entered by Clearing S-bit in SR Exception processing
FC2 = 0 1
Active stack pointer USP SSP
Other stacks using A0 - A6 USP, A0-A6
SR access
Read:
Write:
Entire SR
CCR bits only
Entire SR
Entire SR
Instructions available All except
AND #data,SR
EOR #data,SR
MOVE <ea>,SR
MOVE USP,An
MOVE An,USP
OR #data,SR
RESET
RTE
STOP
All
T6-1
TM-65
Changing Between
User Mode and Supervisor Mode

Supe rv isor
Mode
Tra ns it i o n ma y o cc ur o n ly
d ur in g ex ce pt io n p r oce ssi ng
Tran si t io n may occu r
t hr ou gh f ou r in st r uc t io n s:

User
Mode
MOV E t o SR
A NDI t o SR
EOR t o SR
RTE
F6-1
TM-66
Exception Tree

Exec ut i o n
Er r o r
Use r
V e ct o r
A ut o
V e ct o r
Bu s
Er r o r
Re se t
Tr a ce
TRA P
TRA PV
CHK
Div i d e-
b y - ze r o
Pr i v il eg e
V io la t i o n
A - l in e o r
F- li ne
Emula t i o n
Il le g al
In st r uc t i o n
A d dr ess
Er r o r
In t er r u p t
Ext e r n al Int e r na l
In st r uc t i o n
Exc ep t i on
F6-2
TM-67
Exception Processing Sequence

St art exc ept ion
Make in t ernal
c opy of SR
Obt a in v ec t or
num ber
Vec t or a ddre ss =
vect or n umber x 4
Pus h PC and c opi ed
SR on t o st ac k
Up dat e i nt erru pt
mask lev el
S = 1, T = 0
Int err upt
?
no
y es
( Vec t o r address)
-----> PC
Cont inue execu t i on
F6-3
TM-68
Stack Frame for Exceptions
(except bus error and address error)

Pro g r am Co u nt e r ( lo w)
Pr o g ra m Co un t e r (h i g h )
St at us Re g i st e r
SP ( old )
SP ( n ew)
0 1 5
Hi g h -Me mo r y
Lo w -Mem or y
n
n +2
n +4
n +6
F6-4
TM-69
Exception Vector Address

V7 V6 V5 V4 V3 V2 V1 V0
0 0 all zer o s
A3 1 A 1 0 A9 A 8 A 7 A6 A5 A 4 A3 A2 A 1 A0
Ve ct o r n u mb er
1 2 3
F6-5
TM-70
Reset and Exception
Vector Assignments
Vector
Number
Hexadecimal
Address Assignment
0 000
Reset SSP
004
Reset PC
2 008 Bus Error

3 00C Address Error
4 010 Illegal instruction
5 014 Divide-by-zero
6 018 CHK instruction
7 01C TRAPV instruction
8 020 Privilege violation
9 024 Trace
10 028 Line 1010 emulator
11 02C Line 1111 emulator
12 030 (reserved)
13 034 (reserved)
14 038 Format error (68010)
15 03C Uninitialized interrupt vector
16-23 040-05C (reserved)
24 060
Spurious interrupt
25 064 Level 1 interrupt autovector

27 06C Level 3 interrupt autovector
31 07C Level 7 interrupt autovector
32-47 080-0BC
TRAP instruction vectors
48-63 0C0-0FC (reserved)

64-255 100-3FC User interrupt vectors
The reset vector is four words and resides in the supervisor program (SP)
space. All other vectors reside in the supervisor data (SD) space.
The spurious interrupt vector is taken when there is a bus error during an
interrupt acknowledge cycle.
Trap #n uses vector number 32 + n. See Table 6-5.
T6-2
TM-71
Exception Grouping and Priority
Group Exception Processing
0 Reset
Address Error
Bus Error
Exception processing begins
within two CPU cycles
1 Trace
Interrupt
Illegal Instruction
Privilege Violation
Exception processing begins
before the next instruction
2 TRAP, TRAPV
CHK
Zero Divide
Exception processing begins by
normal instruction execution
T6-3
TM-72
Traps vs. Subroutines
Features Traps Subroutines
Initiated from user mode or
supervisor mode
user mode or
supervisor mode
Routine executes in supervisor mode user mode or
supervisor mode
Registers saved PC and SR PC
Registers saved on system stack user stack or
system stack
Routine ends with RTE RTS
Privilege state after is user mode or
supervisor mode
user mode or
supervisor mode
T6-4
TM-73
Vector Assignments for
TRAP Instructions
Instruction Vector
Number
Vector
Address
TRAP #0 32 $000080
TRAP #1 33 $000084
TRAP #2 34 $000088
TRAP #3 35 $00008C
TRAP #4 36 $000090
TRAP #5 37 $000094
TRAP #6 38 $000098
TRAP #7 39 $00009C
TRAP #8 40 $0000A0
TRAP #9 41 $0000A4
TRAP #10 42 $0000A8
TRAP #11 43 $0000AC
TRAP #12 44 $0000B0
TRAP #13 45 $0000B4
TRAP #14 46 $0000B8
TRAP #15 47 $0000BC
T6-5
TM-74
Stack Frame for
Bus Error and Address Error

Prog r a m Co u nt er ( l o w)
Pr o g ram Co u n t e r ( h ig h)
St at us Re g i st e r
In st ruc t io n Re g ist e r
Ac ce ss ad d r es s ( l o w)
Acc ess a dd re ss (h i g h )
A cc es s t yp e
SP (o l d )
SP ( ne w)
0 1 5
Hig h - Me mo ry
Lo w-Memo ry
n
n+ 2
n+ 4
n+ 6
n+ 8
n +1 0
n +1 2
n +1 4
0 1 2 3 4 5 1 5
123
I/ N R/ W FC2 FC1 FC0
Fu nc t i o n Co de
I/ N
0 = in st r uc t io n
1 = n o t a n i n st r u ct i o n
R/ W
0 = w r it e c yc l e
1 = re ad cy cl e
( a)
( b)
u n de f in ed
TM-75
F6-6
TM-76
Power-on Reset Timing

123 123
+ 5 V
0 V
CL K
V c c
RESET
HA LT
Bu s Cyc l es
> 1 0 0 ms
< 4 c lo c ks
SSP SSP PC PC H L H L
In it i al ize SSP In it i al ize PC Exec ut e 1 st
in st ru ct i o n
12
...
1
Int er na l st art -u p t i me
Bus st at e u n kn ow n
1
A l l c o nt r o l si g n als i n act i ve .
Dat a b us i n r ea d mo d e
Bu s cy cl e ( me mo ry r e ad o r m emo r y wr i t e )
Legend:
F6-7
TM-77
A Switch as an Input Device and an
LED as an Output Device

+5 V
Wir e
Swit c h
LED
Resist or
22 0
Swit c h
OPEN
CLOSED
LED
OFF
ON
+5 V
Swit c h
LED
Resis t or
22 0
Swit c h
OPEN
CLOSED
LED
?
?
Comput er
( b)
( a)
F7-1
TM-78
Interface to Switches and LEDs
(conceptual)

D1 5
D1 4
D1 3
D1 2
D1 1
D1 0
D9
D8
A 2 3
A 2 2
A 2 1
A 2 0
A 1 9
A 1 8
A 1 7
A 1 6
A 1 5
A 1 4
A 1 3
A 1 2
A 1 1
A 1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
UDS
A S
R/ W
0
0
C
0
0
0
A2 3
A2 2
A2 1
A2 0
A1 9
A1 8
A1 7
A1 6
A1 5
A1 4
A1 3
A1 2
A1 1
A1 0
A 9
A 8
A 7
A 6
A 5
A 4
A 3
A 2
A 1
UDS
A S
R/ W
0
0
C
0
0
0
D1 5
D1 4
D1 3
D1 2
D1 1
D1 0
D9
D8
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
+ 5 V
Dat a Bus
DTA CK
+ 5 V
REA D SWITCHES
WRITE LEDS
6 8 00 0
Cont rol Bus
Addre ss Bus
LED # 0
L ED # 7
F7-2
TM-79
Timing for MOVE.B $00C000,D0

t i me
CPU cl ock :
One cl ock
per iod
123
Hi gh- w ord of
addr ess
( $0 000 )
Low- w ord of
address
( $C0 00)
Opcode
f et ch
Memory
r ead
Memor y
r ead
Mem or y
r ead
Mem or y
r ead
Memory
locat i on
$00 C00 0
CL K
S0 S1 S2 S3 S4 S5 S6 S7
F C0 -FC2
A1 - A2 3
D 8 -D1 5
D 0 -D7
A S
UDS
LD S
DTACK
R/ W
Dat a f r om sw it ches
lat ched int o r egist er
D0, bit s 0 -7, at
t he st ar t of S7
$00 C000
swi t c h dat a
t hree- st at e
buf f ers enabl ed
F7-3
TM-80
Example of Partial Decoding

A 2 3
A 2 2
A 2 1
A 2 0
A 1 9
A 1 8
A 1 7
A 1 6
A 1 5
A 1 4
A 1 3
A 1 2
UDS
AS
R/ W
0
0
C
A 2 3
A 2 2
A 2 1
A 2 0
A 1 9
A 1 8
A 1 7
A 1 6
A 1 5
A 1 4
A 1 3
A 1 2
UDS
AS
R/ W
0
0
C
REA D SWITCHES WRITE L EDS
A2 3
0 0 0 0 0 0 0 0 1 1 0 0 X X X X X X X X X X X 0
A1 5 A 0
0 0 C X X XXX0
A1 1 A1 9 A7 A3
Ad dr e ss:
( a)
( b )
F7-5
TM-81
Flowcharts for
Program-Conditional I/O

Ent er En t e r
Rea d De vice
St a t u s Fl ag
Re ad Dev i ce
St at us Fla g
De vi ce
Re ad y
?
De v ic e
Rea d y
?
In p ut
Dat a
Ou t p u t
Da t a
Exi t Exi t
N O NO
YES YES
Cl ea r Fl ag Cl e ar Fl a g
( a) ( b )
In pu t Fl o wch ar t : Out p ut Fl o wch a r t :
F7-7
TM-82
Keyboard Interface

V al id Dat a
Da ta Bus
Ke yb o ard
KBD
DATA
K EYHIT
S
Q
R
READ K BD DATA
READ KBD STATUS
D1 5
D1 4
D1 3
D1 2
D1 1
D1 0
D9
D8
D8
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
K EYHIT
A k ey is
pr esse d
FL AG
( a)
( b)
Da t a ar e st o re d
i n l at ch an d
f la g is se t
KBD DA TA
F7-6
TM-83
Interface Using a
Peripheral Interface IC

CPU
Addr ess
Dec oding
CS
R/ W
A1
A0
St at us
et c.
et c. et c .
et c .
Read Writ e
Input Out put
Cont rol
Cont rol Bus
Addr ess Bus
Per ipher al Int er f ace IC
Peri pher al Dev ic e
Da t a Bus
F7-9
TM-84
Program Execution
Without Interrupts or
With Interrupts

t ime
Mai n Pr o g r am
Mai n Ma in Mai n Ma i n
ISR ISR ISR
* * * * * * * * *
*
* *
Int er r up t
Ret ur n f r o m int e r r up t in st r uc t i o n
Int er r up t - le v el
exe cu t io n
Base - l ev el
exe cu t io n
( a)
( b)
F7-11
TM-85
Interrupt Priority Conditions on -
IPL2, -IPL1, and -IPL0
Signal
IP2 IP1 IP0 Interrupt Condition Maskable Priority
1 1 1 0 No interrupt - -
1 1 0 1 Interrupt Yes Lowest
1 0 1 2 Interrupt Yes (etc.)
0 0 0 7 Interrupt No Highest
T7-3
TM-86
Autovectors for
Automatic IACK Cycles
Interrupt
Vector Address
(Autovector)
0 -
1 $000064
2 $000068
3 $00006C
4 $000070
5 $000074
6 $000078
7 $00007C
T7-4
TM-87
Vector Addresses for
User IACK Cycles
Vector Number Vector Address
0 $000000
1 $000004
2 $000008
etc. etc.
255 $0003FC
T7-5
TM-88
Interrupt Circuitry

FC2
FC1
FC0
A S
C
B
A
E1
E2
E3
7
6
5
4
3
2
1
0
7 4 HC1 3 8
IA ( In t e rr up t Ac kn o wl ed g e )
SP ( Sup e r viso r Pr og r a m)
SD ( Su p e r viso r Da t a )
UP ( Us er Pro g ram)
UD ( Us er Dat a)
C
B
A
E1
E2
E3
7
6
5
4
3
2
1
0
7 4 HC1 3 8
A3
A2
A1
IACK7
IACK6
IACK5
IACK4
IACK3
IACK2
IACK1
V PA
6 8 0 0 0
7
6
5
4
3
2
1
0
E1
7 4 HC1 4 8
A 2
A 1
A 0
+ 5 V
IPL 2
IPL 1
IPL 0
+5 V
INT7
INT6
INT5
INT4
INT3
INT2
INT1 +5 V
+5 V
No n - Mask ab le
In t er r u p t ( NMI)
+5 V
1 0 K
7 4 0 7
F7-12
TM-89
Bus Connections for DMA Interface

CPU
Memor y
Dev ic e
DMA
Cont r oller
Address Bus
Dat a Bus
Cont rol Bus
F7-13
TM-90
Device-to-Memory
Transfer Using DMA

Memor y
Dev ic e
DMA
Cont rol ler
Address Bus
Dat a Bus
Cont r ol Bus
F7-14
TM-91
68000 Bus Arbitration
Control Signals

BR
BG
BGA CK
BR
BG
BGA CK
6 8 0 0 0
CPU
DMA
Co nt ro l le r
F7-15
TM-92
Bus Arbitration

6 80 0 0 CPU DMA Cont r ol ler
Requ est t he Bus
Acknowl edge Bus Mast er shi p
Oper at e as Bu s Mast er
Release Bus Mast ershi p
Resume No rmal Pr oce ssi ng
Ter mi nat e Bus Arbi t r at ion
1 . Assert bus r equest
( BR = 0)
1 . Per f or m dat a t r ansf ers
acc or din g t o sam e r ul es
t he CPU u ses
1 . Assert bus gr ant
ack nowle dge (BGACK = 0 )
2 . Negat e bus request
( BR = 1 )
1. Asser t bus grant ( BG = 0 )
1 . Negat e bus grant
ack now ledge ( BGACK = 1 )
1. Negat e bus gr ant ( BG = 1)
and wai t f or BGACK t o be
nega t ed
t ime
Gr an t t he Bus
F7-16
TM-93
Timing for Bus Arbitration

BR
BG
BGACK
1 2 3 1 2 3 1 2 3
CPU
cy cles
DMA
cy cl es
CPU
cy cle s
t ime
F7-17
TM-94
Block Diagram of the 68KMB

6 8 0 0 0
CPU
Sy st e m
Cl oc k
Re se t
Cir c uit
Int e r rup t
Ci rcu it
A dd r e ss
Dec od e
Cir c uit
Mo ni t o r
EPROMs
(1 6 K)
User
EPROMs
( 1 6 K)
RAMs
( 1 6 K)
Sy st e m Bu ses
Ext e rn al
Int err u p t s
Te rmi na l /
Ho st Co mp u t e r
6 8 6 8 1 DUA RT
Mi sce l la n eo u s
In pu t / Ou t p u t
De vi c es
F8-3
TM-95
68000 CPU

A 2 3
A 2 2
A 2 1
A 2 0
A 1 9
A 1 8
A 1 7
A 1 6
A 1 5
A 1 4
A 1 3
A 1 2
A 1 1
A 1 0
A 9
A 8
A 7
A 6
A 5
A 4
A 3
A 2
A 1
D1 5
D1 4
D1 3
D1 2
D1 1
D1 0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
V cc
GND
CLK
E
V MA
V PA
BR
BG
BGACK
A S
R/ W
UDS
L DS
DTACK
FCO
FC1
FC2
IPL 0
IPL 1
IPL 2
BERR
RESET
HA LT
+5 V
7 X
1 0 K
+5 V
6 8 0 0 0
CPU
Co n t r o l
Bu s
A d d r ess
Bu s
Dat a
Bu s
1 4 , 4 9
1 6 , 5 3
1 5
2 0
1 9
2 1
1 3
1 1
1 2
6
9
7
8
1 0
2 8
2 7
2 6
2 5
2 4
2 3
2 2
1 8
1 7
5 2
5 1
5 0
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
1
2
3
4
5
F8-4
TM-96
68KMB Clock Circuit

5
1K 1K
74 HC14
0. 01 F
4 7
3. 68 64
MHz
10
pF
CLK
BAUD CLK
t o
6 80 00
t o
6 86 81
1 3 1 2
6
1 2 3 4
F8-6
TM-97
68KMB Reset Circuit

7 407
1N
9 14
+5 V +5 V
74 HC1 4
1 0K
100
RESET
22F
+
RESET
HALT
t o
68 000
3 4
1
2
9 8
1 1
1 0
F8-7
TM-98
68KMB Interrupt Circuit

6
1 0
FC2
FC1
FC0
AS
C
B
A
E1
E2
E3
7
6
5
4
3
2
1
0
74HC13 8
SP
SD
UP
UD
+5V
C
B
A
E1
E2
E3
7
6
5
4
3
2
1
0
7 4HC138
A3
A2
A1
IACK7
IACK6
IACK5
IACK4
IACK3
IACK1
+5V
IACK2
t o
686 81
VPA
IPL2
IPL1
IPL0
7
6
5
4
3
2
1
0
E1
74 HC1 48
A2
A1
A0
E0
GS
+5 V
+5V
INT7
INT3
INT2
INT1
MONITOR
22 F
X16
Ext er nal
Int er rupt s
f rom
680 00
t o
68 000
740 7
1 3 1 2
1 1
5
INT6
INT5
INT4
+
7 x
1 0 K
IA 3
3
2
2
1
1
6
6
4
4
5
5
7
7
9
9
1 0
1 0
1 1
1 1
1 2
1 2
1 3
1 3
1 4
1 4
1 5
1 5
4
3
2
1
1 3
1 2
1 1
1 0
5
6
7
9
1 5
1 4
F8-8
TM-99
68KMB Address Decoding

EPROM0 U
EPROM0 L
EPROM1 U
EPROM1 L
RAM0 U
RAM0 L
DUA RT
1 6 L8
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
Vc c
GND
O8
O7
O6
O5
O4
O3
O2
O1
DTACK
7 4 0 7
A2 0
A1 9
A1 8
A1 7
A1 6
A1 5
A1 4
UDS
LDS
A S
f ro m
6 8 0 0 0
t o EPROM,
RAM, & DUA RT
c hi p se le ct inp u t s
t o 6 80 0 0
9 8
1
2
3
4
5
6
7
8
9
1 1
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
+5 V
2 0
1 0
F8-9
TM-100
68KMB Memory Map

000000
003FFE
004000
007FFE
008000
00BFFE
00C000
010000
00FFFE
1FFFFE
200000
FFFFFE
Ex pans ion
Re f le ct ed
9 92 K wor d s
8K wo r ds
( MON68 K)
8K w or d s
( user )
8K w or d s
( syst em/ user )
8K w or d s
( I/ O)
7 M wo r ds
8 M wor d s
( 16 M by t es)
1 M wor ds
( 2M b y t e s)
EPROM0U EPROM0L
EPROM1U EPROM1L
RA M0 U RA M0 L
DUA RT
F8-10
TM-101
Monitor EPROMs

A1 3
A1 2
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
EPROM0 U
D1 5
D1 4
D1 3
D1 2
D1 1
D1 0
D9
D8
2 7 6 4 A
EPROM
A1 2
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CS
D7
D6
D5
D4
D3
D2
D1
D0
Vcc
Vp p
PGM
OE
GND
+ 5 V
A1 3
A1 2
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
EPROM0 L
D7
D6
D5
D4
D3
D2
D1
D0
2 7 6 4 A
EPROM
A1 2
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CS
D7
D6
D5
D4
D3
D2
D1
D0
Vcc
Vp p
PGM
OE
GND
+ 5 V
t o / f ro m
68 0 0 0
f ro m
6 8 0 0 0
f r om
6 8 0 0 0
f ro m Add r e ss
De co d e Cir cui t
f ro m Addr ess
Dec od e Cir cu i t
( mo nit or )
( mo nit or )
2
2 3
2 4
2 5
3
4
5
2 1
6
7
8
9
1 0
2 0
2
2 3
2 4
2 5
3
4
5
2 1
6
7
8
9
1 0
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
2 8
1
2 7
2 2
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
2 8
1
2 7
2 2
F8-12
TM-102
User EPROMs

A1 3
A1 2
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
EPROM1 U
D1 5
D1 4
D1 3
D1 2
D1 1
D1 0
D9
D8
2 7 6 4 A
EPROM
A1 2
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CS
D7
D6
D5
D4
D3
D2
D1
D0
Vc c
Vp p
PGM
OE
GND
+5 V
A1 3
A1 2
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
EPROM1 L
D7
D6
D5
D4
D3
D2
D1
D0
2 7 6 4 A
EPROM
A1 2
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CS
D7
D6
D5
D4
D3
D2
D1
D0
Vc c
Vp p
PGM
OE
GND
+5 V
t o/ f ro m
6 8 0 0 0
f ro m
6 8 0 0 0
f ro m
6 8 0 0 0
f ro m Addr ess
Dec od e Cir cu i t
f ro m Add r ess
Dec o de Cir cu i t
(u ser )
( user )
2
2 3
2 4
2 5
3
4
5
2 1
6
7
8
9
1 0
2 0
2
2 3
2 4
2 5
3
4
5
2 1
6
7
8
9
1 0
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
2 8
1
2 7
2 2
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
2 8
1
2 7
2 2
F8-13
TM-103
System/User RAM

A1 3
A1 2
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
R/ W
RAM0 U
D1 5
D1 4
D1 3
D1 2
D1 1
D1 0
D9
D8
6 2 6 4
RAM
A1 2
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
W
CS
D7
D6
D5
D4
D3
D2
D1
D0
Vc c
OE
GND
+5 V
A1 3
A1 2
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
R/ W
RAM0 L
D7
D6
D5
D4
D3
D2
D1
D0
6 2 6 4
RAM
A1 2
A1 1
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
W
CS
D7
D6
D5
D4
D3
D2
D1
D0
Vc c
OE
GND
+5 V
t o / f ro m
68 0 0 0
f ro m
6 8 0 0 0
f ro m
6 8 0 0 0
f ro m Addr ess
Dec od e Cir cu i t
f r o m Ad dr ess
Dec od e Cir cu it
2
2 3
2 4
2 5
3
4
5
2 1
6
7
8
9
1 0
2 0
2
2 3
2 4
2 5
3
4
5
2 1
6
7
8
9
1 0
2 0
2 7
2 7
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
2 8
2 6
2 2
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
2 8
2 6
2 2
F8-14
TM-104
68681 DUART

+
D7
D6
D5
D4
D3
D2
D1
D0
RESET
R/ W
DTA CK
RS4
RS3
RS2
RS1
IRQ
IA CK
CS
CLK/ X1
X2
V cc
GND
D7
D6
D5
D4
D3
D2
D1
D0
RESET
R/ W
DTACK
A 4
A 3
A 2
A 1
INT2
IA CK 2
DUA RT
BA UD
CL K
6 8 6 8 1
DUART
TxDA
Rx DA
TxDB
Rx DB
T1I
R10
T2I
R20
C1+
C1-
C2+
C2-
T1 O
R1I
T2 O
R2I
V c c
V +
V -
GND
MAX
2 3 2
+
+ +
4 X
10 F
J3
J8
+ 5V
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
IP5
IP4
IP3
IP2
IP1
IP0
+ 5V
J1
Misc el laneous
Inp ut / Ou t put
Dev ices
Ter minal/
Hos t Co mp ut er
DB25 S
DB25 S
Opt i onal
Ser ial
Por t
+ 5 V
t o/ f r om
68 00 0
t o / f r om
Int e r r upt Ci r cu it
f r om A ddr ess
De co de Cir c uit
f r om Clock
Cir cuit
8
7
9
3
1 7
4
1 1
5
1 4
1 5
1 6
1 2
1 3
6
2 0
1 0
3
2
7
3
2
7
2
1 4
7
8
1 6
2
6
1 5
1 1
1 2
1 0
9
1
3
4
5
3 0
3 1
1 1
1 0
1 5
2 6
1 4
2 7
1 3
2 8
1 2
2 9
3 8
3 9
2
3 6
4
7
2 0
4 0
3 3
3 2
3 5
3 7
2 1
1
3
5
6
9
8
3 4
2 5
1 6
2 4
1 7
2 3
1 8
2 2
1 9
F8-15
TM-105
Expansion to 6800 Peripherals

J2
D7
D6
D5
D4
D3
D2
D1
D0
A16
A3
A2
A1
RESET
VPA
E
R/ W
INT3
SD
t o / f ro m
6 80 0 0
t o/ f ro m
In t e r ru pt
Ci rcu it
Exp an si on t o
6 8 0 0 Pe ri p he r als
2 0 - pi n
h ea de r
+5 V
1
2
3
4
5
6
7
8
1 1
1 4
1 5
1 6
1 3
1 8
1 7
1 9
1 2
9
2 0
1 0
F8-16
TM-106
68681 Interface to
LEDs and Switches
(I/O Board #1)

7
4
3 6
2
3 9
3 8
2 6
6 8 6 8 1
DUART
OP6
OP7
OP5
OP4
OP3
OP2
OP1
OP0
1 5
1 4
2 7
1 3
2 8
1 2
2 9
8
2 2 0
7 4 LS2 44
2 1 8
4
6
8
1 1
1 3
1 5
1 7
5
3
7
9
1 2
1 4
1 6
1 , 19
+ 5 V
J1
IP3
IP4
IP5
IP2
IP1
IP0
+5 V
8
7
9
3
1 7
4
1 1
5
1 4
1 5
1 6
1 2
1 3
6
2 0
1 0
+ 5 V
6
1 0 k
F9-3
TM-107
Interface to Switches and
7-Segment LED
(I/O Board #2)

7
2 2 0
2 6
6 8 6 8 1
DUART
OP6
OP7
OP5
OP4
OP3
OP2
OP1
OP0
1 5
1 4
2 7
1 3
2 8
1 2
2 9
7 4 LS2 4 4
2 1 8
4
6
8
1 1
1 3
1 5
1 7
5
3
7
9
1 2
1 4
16
1 , 1 9
J1
IP3
IP2
IP1
IP0
2
3 6
4
7
+5 V
+ 5 V
a
a
b
b
c
c
d
d
e
e
f
f
g
g
MAN7 2A
7 -s eg me nt
commo n
an od e LED
1
14 , 3
1 3
1 0
8
7
2
1 1
8
7
9
3
1 7
4
1 1
5
1 6
1 2
1 3
6
2 0
1 0
+5 V
4
1 0 k
F9-4
TM-108
4-Digit 7-Segment Display
(I/O Board #3)

dp
MC14 499
a
b
c
d
e
f
a
b
c
d
e
f
g
a
b
c
d
e
f
g
a
b
c
d
e
f
g
a
b
c
d
e
f
g
dp
g
f
e
d
c
b
a
4 MA N474 0A
a
b
c
d
e
f
g
h ( dp)
14
13
8
7
6
1
2
4
4
3
2
1
17
16
15
14
8
47
D1 D2 D3 D4
6 868 1
OP2
OP1
OP0
28
12
29
DA TA
CLOCK
ENABLE
5
13
12
OSC
GND
0 .01 5
F
6
9
18
+ 5 V
7 8 10 11
4, 12 4 ,12 4,1 2 4 ,12
4
2 N3 904
Vcc
dp dp
J1
+5 V
4
1 1
5
2 0
1 0
dp
F9-6
TM-109
MC14499 Timing

ENABLE ( OP0 )
CLOCK ( OP1 )
DAT A ( OP2 )
t ime
d
1
d
2
d
3
d
4
d
1 9
d
2 0
F9-7
TM-110
MC14499 Digit and Bit Sequence

t ime
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 16 1 7 18 1 9 20
123 123 123 123 123
Decimal
Point s
Digit
1
Digit
2
Digit
3
Digit
4
Bit No.
F9-8
TM-111
8-Digit 7-Segment Display
(I/O Board #4)

DATA
CL OCK
ENABLE
DIGIT SEG
MC1 4 49 9
h DA TA
CLOCK
ENABLE
DIGIT SEG
MC1 44 9 9
h
et c.
F9-9
TM-112
68681 Input Expansion
Using 74LS165s

9 9
6 86 8 1
DUA RT
IP0
OP1
OP0
1 2
2 9
7
8 , 1 5
H G F E D C B A
DA TA
IN
CLK LOAD
+ 5V
Vc c
n c
DAT A
OUT
6 5 4 3 1 4 1 3 1 2 11
1 0
2 1 1 6 7
7 4L S1 6 5
GND
8 , 1 5
H G F E D C B A
DA TA
IN
CLK LOAD
+ 5V
V c c
n c
DATA
OUT
6 5 4 3 1 4 1 3 1 2 11
10
2 1 1 6 7
7 4L S1 6 5
GND
MSB L SB
+ 5 V
2 0
1 0
6
1 1
5
J1
Ex t er n al Inpu t s
et c .
F9-10
TM-113
6821 Interface to the 68000
(I/O Boards #5 & #6)

6 8 2 1
PIA
D6 D6
D7 D7
D5 D5
D4 D4
D3 D3
D2 D2
D0
2 7
2 6
2 8
2 9
3 0
3 1
J2
D0
3 3 8
1
2
3
4
5
6
+ 5 V
+ 5 V
2 0
1 0
D1 D1
3 2 7
CS2 SD
2 3
7 4 HC0 0
9
CS1
CS0
A 1 6
2 4
2 2
1 1
VPA
1 8
1 2
4
5
3
6
RESET RESET
3 4
1 3
R/ W R/ W
2 1 1 9
E E
2 5 1 7
IRQA INT 3
3 8 1 2
IRQB A 3
n c
3 7 1 4
RS1 A 2
3 5 1 5
RS0
V cc
GND
A 1
3 6
2 0
1
1 6
3 9
CA 2
4 0
CA 1
9
PA 7
8
PA 6
7
PA 5
6
PA 4
5
PA 3
4
PA 2
3
PA 1
2
PA 0
1 7
PB 7
1 6
PB 6
1 5
PB 5
1 4
PB 4
1 3
PB 3
1 2
PB 2
1 1
PB 1
1 0
PB 0
1 9
CB2
1 8
CB1
+ 5 V
F9-11
TM-114
Keypad Interface to the 6821
(I/O Board #5)

0 1 2 3
4 5 6 7
8 9 A B
C D E F
Gra yhi ll PN 8 8BA2
F G H J
K
L
M
N
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
2
3
4
5
6
7
8
9
68 21
PIA
F9-12
TM-115
Output to a MC1408L8 DAC
(I/O Board #6, 1 of 4)

4 .7 k
PA 7
9 5
PA 6
8 6
PA 5
7 7
PA 4
6 8
PA 3
5
9
PA 2
4
1 0
PA 1
3
1 1
PA 0
2 1 2
1 3
1 6
2
3
6 8 21 MC1 40 8L 8
D7
D6
D5
D4
D3
D2
D1
D0
V
COMP
GND
+5 V
V
EE
- 1 2V
14
15
1
4
V r ef +
V r ef -
1 k
1 k
nc
I
O
V
O
7
4
2
3
1
8
6
+ 12 V -1 2 V
LM3 0 1
CC
3 3 pF
1 5 pF
+5V
1 50
1 0 0
F9-13
TM-116
Low-Pass Filter and Audio Output

V
O
0 .0 22 F
0 .0 44 F
1 .2 k
2 .4 k
1 .2 k
V
O
( f ilt er ed )
2 5 F
Sp ea ker
+
6
7
4
2
3
1
8
+ 1 2 V
- 1 2 V
L M3 0 1
( lo w - pa ss
f i l t e r )
3 3 p F
6
7
4
2
3
1
8
+1 2 V -1 2 V
LM3 0 1
( vo l t age
f o ll o we r )
3 3 pF
A ux i li a r y
Jack
5 k
F9-15
TM-117
Interface to ADC0804
Analog-to-Digital Converter

6 82 1
CB2
CB1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
D7
D6
D5
D4
D3
D2
D1
D0
WR
INTR
CS
RD
3
5
1
2
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
Vr ef
CLK R
CLK IN
D GND
A GND
1 5 k
150 pF
Vcc
+5V
10 k
t r i mp ot
( t r ansduc er)
2 0
6
Di f f e re nt ial In p ut s
7
9
1 9
4
1 0
8
nc
1 7
1 9
1 8
1 6
1 5
1 4
1 3
1 2
1 1
1 0
ADC0 804
Vi n( +)
Vi n( - )
F9-16
TM-118
Timing for ADC0804 Conversions

WR
INTR
Cl ear
INTR
St ar t o f
Co n ve rsi o n
En d o f
Co nv er si on
St ar t Next
Conv er sio n
Clear
INTR
1 00 s
F9-17
TM-119
Microphone Input to the ADC0804

2 0
7
V
A
7
4
2
3
1
8
6
+ 1 2 V -1 2 V
L M3 0 1
( lo w-p a ss f i lt er )
3 3 p F
0 .0 2 2 F
0 .0 4 4 F
1 .2 k
2 .4 k
1 8 k
5 . 6 k
1 .2 k
7
4
2
3
1
8
6
+ 1 2 V -1 2 V
LM3 0 1
( pr e -amp )
3 3 p F
1 k
1 %
4 7
1 0 0 k
1%
1 k
1 %
10 0 k
1 %
Mic rop h o ne
2 0 0
7
4
2
3
1
8
6
+ 1 2 V -1 2 V
LM3 01
(a mp )
3 3 p F
1 k
47
1 0 k
2 2 k
2 2 k
+5 V
1 0 F
+
V
B
3
6
5
6
7
3 1 9
1 8 5
-1 2 V
0 .0 0 1 F
1
4
8
+ 1 2 V
L F3 9 8
( sa mp le an d h o ld )
V
C
ADC0 8 0 4
Vin (+ )
Vin (- )
WR
INTR
6 8 2 1
CB2
CB1
V
D
+ 5 V
1 N9 1 4
D7
D6
D5
D4
D3
D2
D1
D0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0
Vre f
CL K R
CL K IN
D GND
A GND
1 5 0 p F
9
1 9
4
1 0
8
n c
1
2
CS
RD
Vcc +5 V
1 5 k
TM-120
F9-19
TM-121
Sample-and-Hold Waveforms

Si gn a l at V
C
Sig n al at V
D
1 00 s min im un
Time
Vol t a ge
F9-20
TM-122
68000-Family Features
48-pin
68008
52-pin
68008 68000 68010 68020 68030 68040
Data Bus (bits) 8 8 16 16 32 32 32
Address Bus (bits) 20 22 24 24 32 32 32
Data Cache (bytes) 256 4096
Instruction Cache
(bytes)
256 256 4096
On-Chip Memory
Management
No No No No No Yes Yes
On-Chip Floating-
Point Unit
No No No No No No Yes
T10-1
TM-123
Comparison of Five Recent
Microprocessors
68040 80486 PowerPC Pentium

Alpha
21064
Company Motorola Intel IBM/Motorola Intel DEC
Introduced 1989 6/91 4/93 3/93 2/92
Architecture CISC CISC RISC CISC RISC
Width (bits) 32 32 32 32 64
Registers
(general/FP)
16/8 8/8 32/32 8/8 32/32
Multiprocessing
Support?
No No Yes Yes Yes
Device Size (mm) 10.8 x
11.7
not
available
11 x 11 17.2 x
17.2
15.3 x 12.7
Transistors
(millions)
1.2 1.2 2.8 3.1 1.68
Clock (MHz) 25 50 80 66 200
SPECint 92
21 27.9 85 67.4 130
SPECfp 92
15 13.1 105 63.6 184
Peak Power
(Watts)
6 5 9.1 16 30
Price ($US/1000
units)
$233 $432 $557 $898 $505
Source: IEEE Spectrum, December 1993, p. 21

Integer and floating-point performance benchmarks
T10-10
1
SPECIFICATION AND IMPLEMENTATION OF A MICROCOMPUTER
BASIC COMPONENTS OF A COMPUTER SYSTEM
INFORMAL AND vhdl-BASED DESCRIPTION
ARCHITECTURE
IMPLEMENTATION
OPERATION OF SIMPLE MICROCOMPUTER SYSTEM:
XMC: eXample MicroComputer
ITS CYCLE TIME
Introduction to Digital Systems 15 Specication and Implementation of a Microcomputer
2
BASIC COMPONENTS OF A COMPUTER
PROCESSOR;
MEMORY SUBSYSTEM;
INPUT/OUTPUT (I/O) SUBSYSTEM
Processor
Memory
subsystem
I/O
subsystem
I/O devices
Memory bus
(Address, data, control)
I/O bus
(Address, data, control)
Figure 15.1: COMPUTER SYSTEM.
3
MEMORY HIERARCHY
Virtual memory
(Disk)
Main memory
(Dynamic devices)
Cache memory
(Static devices)
Processor
Faster
Larger
size
2 Gbyte
16 Mbyte
64 Kbyte
Figure 15.2: MEMORY HIERARCHY.
4
SPECIFICATION (architecture) OF A SIMPLE MICROCOMPUTER SYSTEM
Processor
Memory
subsystem
MemAddr
I/O
subsystem
IOAddr
MemData IOData
MemLength
MemRd
MemWr
MemRdy
IOLength
IORd
IOWr
IORdy
Clk Reset
I/O
devices
I/O Bus Memory Bus
24
1
1
1
1
32
11
1
1
1
1
32
Status
MemEnable 1
IOEnable 1
Figure 15.3: STRUCTURE OF XMC.
5
vhdl STRUCTURAL DESCRIPTION
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE comp_pkg IS
SUBTYPE WordT IS STD_LOGIC_VECTOR(31 DOWNTO 0);
SUBTYPE MAddrT IS STD_LOGIC_VECTOR(23 DOWNTO 0);
SUBTYPE IOAddrT IS STD_LOGIC_VECTOR(10 DOWNTO 0);
SUBTYPE ByteT IS STD_LOGIC_VECTOR( 7 DOWNTO 0);
TYPE StatusT IS (undef, p_reset, fetch, execute, memop, ioop);
FUNCTION get_carry(RA_Data,RB_Data,Imm,Opcode: STD_LOGIC_VECTOR)
RETURN STD_LOGIC;
FUNCTION get_ovf (RA_Data,RB_Data,Imm,Opcode: STD_LOGIC_VECTOR)
RETURN STD_LOGIC;
FUNCTION get_cc (RA_Data,RB_Data,Opcode: STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
END comp_pkg;
PACKAGE BODY comp_pkg IS
FUNCTION get_carry(RA_Data,RB_Data,Imm,Opcode: STD_LOGIC_VECTOR)
RETURN STD_LOGIC
6
IS VARIABLE cy: STD_LOGIC:= 0;
BEGIN
-- description of carry generation included here
RETURN(cy);
END get_carry;
FUNCTION get_ovf (RA_Data,RB_Data,Imm,Opcode: STD_LOGIC_VECTOR)
RETURN STD_LOGIC
IS VARIABLE ovf: STD_LOGIC:= 0;
BEGIN
-- description of overflow generation included here
RETURN(ovf);
END get_ovf;
FUNCTION get_cc (RA_Data,RB_Data,Opcode: STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR
IS VARIABLE cc: STD_LOGIC_VECTOR(3 DOWNTO 0):= "0000";
BEGIN
-- description of cc generation included here
RETURN(cc);
END get_cc;
END comp_pkg;
7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE WORK.ALL, WORK.comp_pkg.ALL;
ENTITY Computer IS
PORT (Reset, Clk : IN STD_LOGIC);
END Computer;
ARCHITECTURE structural OF Computer IS
SIGNAL MemAddr : MAddrT ; -- memory address bus
SIGNAL MemLength, MemRd : STD_LOGIC; -- memory control signals
SIGNAL MemWr, MemEnable : STD_LOGIC;
SIGNAL MemRdy : STD_LOGIC; -- memory status signal
SIGNAL MemData : WordT ; -- memory data bus
SIGNAL IOAddr : IOAddrT ; -- I/O address bus
SIGNAL IOLength, IORd : STD_LOGIC; -- I/O control signals
SIGNAL IOWr, IOEnable : STD_LOGIC;
SIGNAL IORdy : STD_LOGIC; -- I/O status signal
SIGNAL IOData : WordT ; -- I/O data bus
SIGNAL Status : StatusT;
8
BEGIN
U1: ENTITY Memory
PORT MAP (MemAddr, MemLength, MemRd, MemWr, MemEnable,
MemRdy, MemData);
U2: ENTITY IO
PORT MAP (IOAddr, IOLength, IORd, IOWr, IOEnable,
IORdy, IOData);
U3: ENTITY Processor
PORT MAP (MemAddr, MemData, MemLength, MemRd, MemWr,
MemEnable, MemRdy,
IOAddr, IOData, IOLength, IORd, IOWr,
IOEnable, IORdy,
Status, Reset, Clk);
END structural;
9
MEMORY SUBSYSTEM
Addr
Length
Rd
Wr
Data
Rdy
Memory
32
24
Word 0
Word 4
32 bits
Byte 3 Byte 2 Byte 1 Byte 0
(b)
Word 2 -4
24
(a)
Enable
Addr
Rd
Wr
Data
Rdy
t
mem
Idle Idle
Enable
t
su
t
mem
t
su
t
mem
= mem. cycle
= setup time
t
su
= data valid
t
dv
t
dv
t
dv
(c)
Figure 15.4: MEMORY SUBSYSTEM. (a) EXTERNAL SIGNALS. (b) INTERNAL ORGANIZATION. (c) TIMING DIAGRAM
10
vhdl ENTITY DECLARATION FOR MEMORY SUBSYSTEM
LIBRARY ieee;
USE WORK.comp_pkg.ALL;
ENTITY Memory IS
PORT (Addr : IN MAddrT ; -- memory address bus
Length : IN STD_LOGIC; -- byte/word operand
Rd, Wr : IN STD_LOGIC; -- access control signals
Enable : IN STD_LOGIC; -- enable signal
Rdy : OUT STD_LOGIC; -- access completion signal
Data : INOUT WordT ); -- memory data bus
END Memory;
11
vhdl BEHAVIORAL DESCRIPTION OF MEMORY SUBSYSTEM
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
ARCHITECTURE behavioral OF Memory IS
CONSTANT Tmem : TIME := 8 ns; -- nanoseconds
CONSTANT Td : TIME := 200 ps; -- picoseconds
CONSTANT Tsu : TIME := 200 ps; -- picoseconds
BEGIN
PROCESS (Rd, Wr, Enable)
CONSTANT byte_l: STD_LOGIC:= 0; -- constant declarations
CONSTANT word_l: STD_LOGIC:= 1;
-- memory declaration
CONSTANT MaxMem : NATURAL := 16#FFFFFF#; -- 2**24 bytes
TYPE MemArrayT IS ARRAY(0 TO MaxMem-1) OF ByteT;
VARIABLE Mem : MemArrayT;
-- working variables
VARIABLE tAddr : NATURAL;
VARIABLE tData : WordT ;
VARIABLE tCtrls: STD_LOGIC_VECTOR(2 DOWNTO 0);
12
BEGIN
tCtrls:= Rd & Wr & Enable; -- group signals for simpler decoding
CASE tCtrls IS
-- output to tri-state
WHEN "000" => Data <= (OTHERS => Z) AFTER Td;
WHEN "011" => -- write access;
-- indicate module busy
Rdy <= 0 AFTER Td, 1 AFTER Tmem;
IF (Length = byte_l) THEN -- read address
tAddr:= CONV_INTEGER(Addr); -- bit-vector to integer
-- from pkg std_logic_unsigned
ELSE
tAddr:= CONV_INTEGER(Addr(23 DOWNTO 2) & "00");
END IF;
CASE Length IS
WHEN byte_l => Mem(tAddr) := (Data( 7 DOWNTO 0));
WHEN word_l => Mem(tAddr) := (Data( 7 DOWNTO 0));
Mem(tAddr+1):= (Data(15 DOWNTO 8));
WHEN OTHERS => NULL;
13
END CASE;
WHEN "101" => -- read access
-- indicate module busy
Rdy <= 0 AFTER Td, 1 AFTER Tmem;
IF (Length = byte_l) THEN -- read address
tAddr:= CONV_INTEGER(Addr); -- bit-vector to integer
ELSE
tAddr:= CONV_INTEGER(Addr(23 DOWNTO 2) & "00");
END IF;
CASE Length IS
WHEN byte_l => tData( 7 DOWNTO 0):= (Mem(tAddr));
WHEN word_l => tData( 7 DOWNTO 0):= (Mem(tAddr));
tData(15 DOWNTO 8):= (Mem(tAddr+1));
END CASE;
Data <= tData AFTER Tmem; -- deliver data
WHEN OTHERS => NULL; -- memory not enabled
END CASE;
END PROCESS;
14
-- timing verifications
ASSERT NOT (RdEVENT AND Rd=1 AND NOT AddrSTABLE(Tsu))
REPORT "Read address setup time violation";
ASSERT NOT (RdEVENT AND Rd=1 AND NOT EnableSTABLE(Tsu))
REPORT "Read enable setup time violation";
ASSERT NOT (WrEVENT AND Wr=1 AND NOT AddrSTABLE(Tsu))
REPORT "Write address setup time violation";
ASSERT NOT (WrEVENT AND Wr=1 AND NOT EnableSTABLE(Tsu))
REPORT "Write enable setup time violation";
END behavioral;
15
INPUT/OUTPUT (I/O) SUBSYSTEM
I/O Port 0
I/O Port 1
I/O Port 2047
32 bits
Addr
Length
Rd
Wr
Data
Rdy
I/O
subsystem
(a) (b)
32
11
Enable
Figure 15.5: INPUT/OUTPUT SUBSYSTEM.
16
vhdl I/O ENTITY DECLARATION
LIBRARY ieee;
ENTITY IO IS
PORT (Addr : IN IOAddrT ; -- I/O address bus
Length : IN STD_LOGIC; -- byte/word control
Rd, Wr : IN STD_LOGIC; -- I/O access control
Enable : IN STD_LOGIC; -- I/O enable control
Rdy : OUT STD_LOGIC; -- I/O completion signal
Data : INOUT WordT ); -- I/O data bus
END IO;
17
PROCESSOR
Processor state
32 general-purpose registers (32-bits wide), called R0, R1, ..., R31;
a 24-bit Program Counter register (PC);
a 4-bit Condition Register (CR); and
a 32-bit Instruction Register (IR).
Memory Bus I/O Bus
CR Z N C V
PC
IR
General Purpose Registers
R0
R1
R2
R31
Figure 15.6: PROCESSOR STATE.
18
BEHAVIOR OF PROCESSOR
Fetch instruction
Execute instruction and
compute address of next instr.
(a)
MemAddr
Clk
DataBus
MemRdy
MemRd
Fetch Execute
Memory
access
Inst. Data
Inst. Addr. Data Addr.
Execute
(Addr.
calc.)
Fetch
(i) (ii)
Inst.
Inst. Addr.
MemEnable
Figure 15.7: BEHAVIOR OF THE PROCESSOR. (a) INSTRUCTION LOOP. (b) MEMORY BUS BEHAVIOR FOR REGISTER
OPERATION. (c) MEMORY BUS BEHAVIOR FOR LOAD OPERATION.
19
BEHAVIOR OF INSTRUCTIONS
R1
R5
R7
CR
conds.
Memory
IR= branch 2000
addr.gen.
(a)
(b)
Memory
IR= add R7,R1,R5
PC
+4
branch 2000 add R7,R1,R5
PC
Memory
IR= branch cond,2000
addr.gen.
(c)
branch cond,2000
PC
cond?
+4
selector
Figure 15.8: BEHAVIOR OF INSTRUCTIONS. (a) ADD instruction. (b) UNCONDITIONAL BRANCH INSTRUCTION. (c) CON-
DITIONAL BRANCH INSTRUCTION.
20
INSTRUCTION SEQUENCING
SEQUENTIAL UNLESS
1. UNCONDITIONAL BRANCH
2. CONDITIONAL BRANCH
21
31 25 20 15 10 0
RT:= op(RA) Opcode RT RA --
RT:= RA op RB Opcode RT RA RB --
RT:= RA op SI Opcode RT RA SI
RT:= RA op UI Opcode RT RA UI
RT:= M[RA+D] Opcode RT RA D
M[RA+D]:= RS Opcode RS RA D
RT:= IO[PN] Opcode RT RA -- PN
IO[PN]:= RS Opcode RS RA -- PN
PC:= PC + 4 + D Opcode -- D
PC:= RA Opcode -- RA --
Figure 15.9: INSTRUCTION FORMATS.
22
Table 15.2: INSTRUCTION SET
Name Opcode Function CR Assembly Language
No-op 000000 no operation nop
not 000010 RT:= not(RA) Y not RT,RA
Left shift 000100 RT:= lshift(RA) Y lsh RT,RA
Right shift 000110 RT:= rshift(RA) Y rsh RT,RA
Left rotate 001000 RT:= lrot(RA) Y lrt RT,RA
Right rot. 001010 RT:= rrot(RA) Y rrt RT,RA
Add 010000 RT:= RA + RB Y add RT,RA,RB
Add immed. 010001 RT:= RA + SI Y adi RT,RA,SI
Subtract 010010 RT:= RA - RB Y sub RT,RA,RB
Sub. immed. 010011 RT:= RA - SI Y sbi RT,RA,SI
and 010100 RT:= RA and RB Y and RT,RA,RB
and immed. 010101 RT:= RA and UI Y ani RT,RA,UI
or 010110 RT:= RA or RB Y or RT,RA,RB
or immed. 010111 RT:= RA or UI Y ori RT,RA,UI
xor 011000 RT:= RA xor RB Y xor RT,RA,RB
xor immed. 011001 RT:= RA xor UI Y xri RT,RA,UI
23
Table 15.3: INSTRUCTION SET (cont.)
Load byte 100000 RT( 7 to 0):= Mem(RA+D,1) ldb RT,D(RA)
Load word 100001 RT(31 to 0):= Mem(RA+D,4) ldw RT,D(RA)
Store byte 100010 Mem(RA+D,1):= RS( 7 to 0) stb RS,D(RA)
Store word 100011 Mem(RA+D,4):= RS(31 to 0) stw RS,D(RA)
I/O Rd byte 100100 RT( 7 to 0):= IO(PN,1) irb RT,PN
I/O Rd word 100101 RT(31 to 0):= IO(PN,4) irw RT,PN
I/O Wr byte 100110 IO(PN,1):= RS( 7 to 0) iwb RS,PN
I/O Wr word 100111 IO(PN,4):= RS(31 to 0) iww RS,PN
24
Table 15.4: INSTRUCTION SET (cont.)
Branch 111000 PC:= PC + 4 + D br D
Branch indirect 111001 PC:= RA bri RA
Branch if N=0 110000 If N=0 then PC:= PC+4+D brp D
Branch if N=1 110001 If N=1 then PC:= PC+4+D brn D
Branch if Z=0 110010 If Z=0 then PC:= PC+4+D bnz D
Branch if Z=1 110011 If Z=1 then PC:= PC+4+D brz D
Branch if C=0 110100 If C=0 then PC:= PC+4+D bnc D
Branch if C=1 110101 If C=1 then PC:= PC+4+D brc D
Branch if V=0 110110 If V=0 then PC:= PC+4+D bnv D
Branch if V=1 110111 If V=1 then PC:= PC+4+D brv D
25
vhdl SPECIFICATION OF PROCESSOR
LIBRARY ieee;
ENTITY processor IS
PORT (MemAddr : OUT MAddrT ; -- memory address bus
MemData : INOUT WordT ; -- data bus to/from memory
MemLength: OUT STD_LOGIC; -- memory operand length
MemRd : OUT STD_LOGIC; -- memory read control signal
MemWr : OUT STD_LOGIC; -- memory write control signal
MemEnable: OUT STD_LOGIC; -- memory enable signal
MemRdy : IN STD_LOGIC; -- memory completion signal
IOAddr : OUT IOAddrT ; -- I/O address bus
IOData : INOUT WordT ; -- data bus to/from I/O
IOLength : OUT STD_LOGIC; -- I/O operand length
IORd : OUT STD_LOGIC; -- I/O read control signal
IOWr : OUT STD_LOGIC; -- I/O write control signal
IOEnable : OUT STD_LOGIC; -- memory enable signal
IORdy : IN STD_LOGIC; -- I/O completion signal
Status : OUT StatusT ; -- processor status signal
Reset : IN STD_LOGIC; -- reset signal
Clk : IN STD_LOGIC); -- clock signal
END processor;
26
vhdl SPECIFICATION OF BEHAVIOR
LIBRARY ieee;
USE ieee.std_logic_arith.all; -- use definitions and operations
USE ieee.std_logic_signed.all; -- on signed values
ARCHITECTURE behavioral OF processor IS
-- registers (processor state)
TYPE RegFileT IS ARRAY(0 to 31) OF WordT;
SIGNAL GPR: RegFileT ; -- general registers
SIGNAL PC : MAddrT ; -- Program Counter register
SIGNAL CR : STD_LOGIC_VECTOR( 3 DOWNTO 0); -- Condition Register
SIGNAL IR : STD_LOGIC_VECTOR(31 DOWNTO 0); -- Instruction register
-- signals used by output function
SIGNAL Phase: StatusT ; -- instr. cycle phase
SIGNAL tMemAddr: WordT ; -- memory address
SIGNAL tData : WordT ; -- memory/io data
ALIAS Z : STD_LOGIC IS CR(0) ; -- Condition code Zero
ALIAS N : STD_LOGIC IS CR(1) ; -- Condition code Negative
ALIAS C : STD_LOGIC IS CR(2) ; -- Condition code Carry
ALIAS O : STD_LOGIC IS CR(3) ; -- Condition code Overflow
27
ALIAS Opcode : STD_LOGIC_VECTOR(5 DOWNTO 0) IS IR(31 DOWNTO 26);
ALIAS RT : STD_LOGIC_VECTOR(4 DOWNTO 0) IS IR(25 DOWNTO 21);
ALIAS RA : STD_LOGIC_VECTOR(4 DOWNTO 0) IS IR(20 DOWNTO 16);
ALIAS RB : STD_LOGIC_VECTOR(4 DOWNTO 0) IS IR(15 DOWNTO 11);
ALIAS RS : STD_LOGIC_VECTOR(4 DOWNTO 0) IS IR(15 DOWNTO 11);
ALIAS Imm : STD_LOGIC_VECTOR(15 DOWNTO 0) IS IR(15 DOWNTO 0);
ALIAS D : STD_LOGIC_VECTOR(15 DOWNTO 0) IS IR(15 DOWNTO 0);
ALIAS PN : STD_LOGIC_VECTOR(10 DOWNTO 0) IS IR(10 DOWNTO 0);
ALIAS dlength: STD_LOGIC IS IR(26) ;
-- other declarations
CONSTANT delay : TIME := 200 ps; -- register delay
CONSTANT Reset_delay: TIME := 5 ns;
CONSTANT Exec_delay : TIME := 10 ns; -- Execute delay
CONSTANT Mdelay : TIME := 600 ps; -- MemEnable signal delay
CONSTANT Pulse_Width: TIME := 2.6 ns; -- memory signals width
CONSTANT Fetch_delay: TIME := 3 ns; -- disable memory after
-- access completed
28
BEGIN
PROCESS -- transition function
-- working variables
VARIABLE RS_data, RA_data, RB_data : WordT;
VARIABLE RT_addr, RA_addr, RB_addr, RS_addr : Natural;
BEGIN
WAIT ON Clk,Reset;
IF (ResetEvent AND Reset = 1) THEN -- reset function
PC <= (OTHERS => 0); CR <= "0000"; IR <= (OTHERS => 0);
FOR i IN 0 TO 31 LOOP
GPR(i) <= (OTHERS => 0);
END LOOP;
Phase <= p_reset;
Status <= p_reset;
WAIT UNTIL (Reset = 0) AND (Clk = 1);
END IF;
29
IF (ClkEvent AND Clk=1) THEN
-- Instruction cycle
Status <= Fetch AFTER delay;
Phase <= Fetch AFTER delay;
-- instruction fetch
PC <= PC + 4 AFTER Exec_delay;
WAIT UNTIL MemRdy=1; -- wait instr. fetch completed
IR <= MemData;
WAIT FOR Fetch_delay;
-- instruction execution
Status <= Execute;
Phase <= Execute;
RA_addr := CONV_INTEGER(0 & RA); RB_addr := CONV_INTEGER(0 & RB);
-- 0 to force bit-vector to positive value
RA_data := GPR(RA_addr) ; RB_data := GPR(RB_addr) ;
RT_addr := CONV_INTEGER(0 & RT);
RS_addr := CONV_INTEGER(0 & RS); -- source reg. for store
RS_data := GPR(RS_addr) ; -- or I/O write
WAIT FOR Exec_delay;
30
CASE Opcode IS
WHEN "000000" => null; -- nop
WHEN "000010" => GPR(RT_Addr)<= not(RA_data); -- not
WHEN "000100" => GPR(RT_Addr)<= RA_data(30 DOWNTO 0) & 0; -- lshift
WHEN "000110" => GPR(RT_Addr)<= 0 & RA_data(31 DOWNTO 1); -- rshift
-- lrotate
WHEN "001000" => GPR(RT_Addr)<= RA_data(30 DOWNTO 0) & RA_data(31);
-- rrotate
WHEN "001010" => GPR(RT_Addr)<= RA_DATA(0) & RA_data(31 DOWNTO 1);
WHEN "010000" => GPR(RT_Addr)<= RA_data + RB_data ; -- add
WHEN "010001" => GPR(RT_Addr)<= RA_data + Imm;
WHEN "010010" => GPR(RT_Addr)<= RA_data - RB_data ; -- sub
WHEN "010011" => GPR(RT_Addr)<= RA_data - Imm;
WHEN "010100" => GPR(RT_Addr)<= RA_data and RB_data ; -- and
WHEN "010101" => GPR(RT_Addr)<= RA_data and ext(Imm,RA_dataLENGTH);
-- ext: zero extension from ieee pkg
WHEN "010110" => GPR(RT_Addr)<= RA_data or RB_data ; -- or
WHEN "010111" => GPR(RT_Addr)<= RA_data or ext(Imm,RA_dataLENGTH);
31
WHEN "011000" => GPR(RT_Addr)<= RA_data xor RB_data ; -- xor
WHEN "011001" => GPR(RT_Addr)<= RA_data xor ext(Imm,RA_dataLENGTH);
WHEN "100000" | "100001" => -- ldb, ldw
Phase <= MemOp;
Status <= MemOp;
tMemAddr <= RA_data + D; -- mem.addr.
WAIT until MemRdy = 1;
WHEN "100010" | "100011" => -- stb, stw
Phase <= MemOp;
Status <= MemOp;
tMemAddr <= RA_data + D; -- mem. addr.
tData <= RS_data; -- mem. data
WHEN "100100" | "100101" => -- irb, irw
Phase <= IOOp;
Status <= IOOp;
WAIT until IORdy = 1 ;
32
WHEN "100110" | "100111" => -- iwb, iww
Phase <= IOOp;
Status <= IOOp;
tData <= RS_data; -- io data
WHEN "111000" => PC <= PC + D; -- branch
WHEN "111001" => PC <= RA_data(23 DOWNTO 0); -- br.ind.
WHEN "110000" | "110001"
=> IF (N = Opcode(0)) THEN -- br on N
PC <= PC + D;
END IF;
WHEN "110010" | "110011"
=> IF (Z = Opcode(0)) THEN -- br on Z
PC <= PC + D;
END IF;
WHEN "110100" | "110101"
=> IF (C = Opcode(0)) THEN -- br on C
PC <= PC + D;
END IF;
WHEN "110110" | "110111"
=> IF (O = Opcode(0)) THEN -- br on V
PC <= PC + D;
33
END IF;
WHEN others => null;
END CASE;
IF ((Opcode(5 DOWNTO 4) = 0) or (Opcode(5 DOWNTO 4) = 1))
and (Opcode /= 0) THEN
-- set condition register
IF (GPR(RT_Addr) = 0) THEN CR(0) <= 1; -- zero result
ELSE CR(0) <= 0;
END IF;
IF (GPR(RT_Addr)(31) = 1) THEN CR(1) <= 1; -- negative result
ELSE CR(1) <= 0;
END IF;
-- check if operation Opcode generates carry out
CR(2) <= get_carry(RA_Data,RB_Data,Imm,Opcode);
-- check if operation Opcode generates overflow
CR(3) <= get_ovf(RA_Data,RB_Data,Imm,Opcode);
END IF;
WAIT FOR 0 ns; -- force signals to be updated
34
IF (Phase = MemOp) THEN
IF (dlength = 1) THEN -- ldw
GPR(RT_addr) <= MemData;
ELSE -- ldb
GPR(RT_addr)( 7 DOWNTO 0) <= MemData(7 DOWNTO 0);
GPR(RT_addr)(31 DOWNTO 8) <= (OTHERS => 0);
END IF;
END IF;
IF (Phase = IOOp) THEN
IF (dlength = 1) THEN -- irw
GPR(RT_addr) <= IOData;
ELSE -- irb
GPR(RT_addr)( 7 DOWNTO 0) <= IOData(7 DOWNTO 0);
GPR(RT_addr)(31 DOWNTO 8) <= (OTHERS => 0);
END IF;
END IF;
END IF;
END PROCESS;
PROCESS -- output function
35
BEGIN
-- Instruction cycle
WAIT ON Phase;
IF (Phase = p_reset) THEN -- reset
MemRd <= 0; MemWr <= 0; MemEnable <= 0; MemLength <= 0;
MemData <= (OTHERS => Z);
IORd <= 0; IOWr <= 0; IOEnable <= 0; IOLength <= 0;
IOData <= (OTHERS => Z);
ELSIF (Phase = Fetch) THEN -- instruction fetch
MemAddr <= PC AFTER delay;
MemEnable <= 1 AFTER delay;
MemRd <= 1 AFTER Mdelay, 0 AFTER Pulse_Width;
MemLength <= 1 AFTER delay;
WAIT UNTIL MemRdy=1; -- wait instr. fetch completed
MemEnable <= 0 AFTER Fetch_delay;
ELSIF (Phase = Execute) THEN NULL; -- instruction execution
-- no output signals
ELSIF (Phase = MemOp) THEN
MemAddr <= tMemAddr(23 DOWNTO 0) AFTER delay;
36
MemLength <= dlength AFTER delay;
IF ((To_Bitvector(Opcode) = "100000") OR
(To_Bitvector(Opcode) = "100001")) THEN -- ldb, ldw
MemRd <= 1 AFTER Mdelay, 0 AFTER Pulse_Width;
MemEnable <= 0 AFTER Fetch_delay;
END IF;
(To_Bitvector(Opcode) = "100011")) THEN -- stb, stw
MemWr <= 1 AFTER Mdelay, 0 AFTER Pulse_Width;
IF (dlength = 1) THEN -- stw
MemData <= tData AFTER delay;
ELSE -- stb
MemData(7 DOWNTO 0) <= tData(7 DOWNTO 0) AFTER delay;
END IF;
MemData <= (OTHERS => Z) AFTER delay;
WAIT FOR delay;
END IF;
ELSIF (Phase = IOOp) THEN
37
IOAddr <= PN AFTER delay;
IOEnable <= 1 AFTER delay;
IOLength <= dlength AFTER delay;
(To_Bitvector(Opcode) = "100101")) THEN -- irb, irw
IORd <= 1 AFTER Mdelay, 0 AFTER Pulse_Width;
IOEnable <= 0 AFTER Fetch_delay;
END IF;
(To_Bitvector(Opcode) = "100111")) THEN -- iwb, iww
IF (dlength = 1) THEN -- iww
IOData <= tData AFTER delay;
ELSE -- iwb
IOData(7 DOWNTO 0) <= tData(7 DOWNTO 0) AFTER delay;
END IF;
IOWr <= 1 AFTER Mdelay, 0 AFTER Pulse_Width;
WAIT until IORdy = 1;
IOEnable <= 0 AFTER delay;
IOData <= (OTHERS => Z) AFTER delay;
WAIT FOR delay;
END IF;
38
END IF;
END PROCESS;
END behavioral;
39
vhdl SPECIFICATION OF MEMORY CONTENTS
-- memory declaration
CONSTANT MaxMem: NATURAL:= 16#FFF#; -- 4Kbytes
TYPE MemArrayT IS ARRAY(0 to MaxMem-1) OF ByteT;
VARIABLE Mem : MemArrayT:=
(-- program
3=>"01100000", 2=>"00000000", 1=>"00000000", 0=>"00000000",
7=>"01000100", 6=>"00100000", 5=>"00000000", 4=>"00110010",
11=>"10000110", 10=>"10000001", 9=>"00000000", 8=>"00000000",
15=>"10000110", 14=>"10100001", 13=>"00000000", 12=>"00000100",
19=>"01000100", 18=>"01000000", 17=>"00000000", 16=>"00111111",
23=>"10001000", 22=>"01000001", 21=>"00000000", 20=>"00000000",
-- data
51=>"00110011", 50=>"00001111", 49=>"11110000", 48=>"11001100",
55=>"00110011", 54=>"00001111", 53=>"11110000", 52=>"11001100",
OTHERS => "00000000");
where the memory contents corresponds to the following instructions:
0x000000: xor R0,R0,R0 ; R0 = 0
0x000004: adi R1,R0,50 ; R1 = 50
0x000008: ldw R20,0(R1) ; R20= Mem(50,4)= Mem(48,4)
0x00000C: ldw R21,4(R1) ; R21= Mem(54,4)= Mem(52,4)
0x000010: adi R2,R0,63 ; R2 = 63
0x000014: stb R2,0(R1) ; Mem(50,1) = 63
0x000048: 0x330FF0CC
0x000052: 0x330FF0CC
40
IMPLEMENTATION OF XMC
MEMORY SUBSYSTEM
PROCESSOR
1. DATA SUBSYSTEM
2. CONTROL SUBSYSTEM
41
MEMORY SUBSYSTEM
Address
2
Length Selector/Distributor
32
Data
8 8 8 8
Rd
Wr MRdy Controller
22
Controls
2 x1 bits
22
Enable
Figure 15.10: IMPLEMENTATION OF THE MEMORY SUBSYSTEM.
42
PROCESSOR
Data
subsystem
Control
subsystem
Instr
ZE,NG,CY,OV
MemRd
MemWr
MemAddr
Clk
Reset
MemData
IOData
IOAddr
MemEnable
IORd
MemRdy
IOWr
MemLength
IORdy
4
32
24
32
11
32
Condition signals
Control signals
Data
signals
Status
IOLength
IOEnable
Figure 15.11: IMPLEMENTATION OF THE PROCESSOR.
43
DATA SUBSYSTEM
Register
file
IR
PC
Z N C V
WrCR
ALU
DataA
DataB
WrPC
ALUOp
Mux4
MemAddr
MemData
ALU_PC
WrIR
IR_RB
Instr
ZE,NG,CY,OV
ALUdata
Cond
S
w
i
t
c
h
Mux1
Mem_ALU
Reset
AddrC
MemData
Mux3
Reset
Reset
AddrA
AddrB
Reset
WrC
DataC
0 1
0 1
0 1
PCout
PCin
Bin
Sin_Sout
Ain
0
1
SE_ZE
E
x
t
n
d
r
.
Mux2
1 0
PC_RA
B A
C
B
A
C
Clk
Clk
Clk
Clk
Figure 15.12: IMPLEMENTATION OF DATA SUBSYSTEM (I/O signals not shown).
44
ALU
ALUop Operation
0000 Zero 32
0001 A + B
0010 A - B
0011 -B
0100 A and B
0101 A or B
0110 A xor B
0111 not(B)
1000 unused
1001 B
1010 shiftl(A)
1011 shiftr(A)
1100 rotl(A)
1101 rotr(A)
1110 A + 4
1111 unused
45
EVENT SEQUENCE FOR ALU INSTRUCTION
Register
file
IR
PC
Z N C V
MemAddr
MemData
ALU_PC
Instr
ZE,NG,CY,OV
1
AddrA
AddrB
3
ALUOp
Cond
AddrC
WrC
3
2
WrCR
IR_RB
Mem_ALU
PC_RA
2 2
2
2
2
2
2
2
4
4
DataA
DataB
Clk
Clk
DataC
Mux1
Mux3 Mux2
2
2
Figure 15.13: SEQUENCE OF EVENTS IN DATA SUBSYSTEM FOR ALU INSTRUCTION.
46
TIMING DIAGRAM FOR ALU INSTRUCTION
Instr
Clk
AddrA
instruction
decode
register
read delay
Add Instruction
AddrB
DataA
DataB
ALUop
DataC
Cond
AddrC
WrC
ALUop
delay
register
setup
WrCR
3 4 2 1
Figure 15.14: TIMING DIAGRAM FOR ALU INSTRUCTION IN DATA SUBSYSTEM.
47
CONTROL SUBSYSTEM
Instr
OV,CY,ZE,NG
Clk
Reset
State
reg.
Combinational
logic
AddrA
AddrB
AddrC
ALUOp
...
...
ALU_PC
MemRdy IORdy
Figure 15.15: CONTROL SUBSYSTEM.
48
STATE DIAGRAM AND TIMING
Fetch
Execute
Memop
Fetch Execute Fetch
Fetch Execute Memop Fetch
Clk
Register
operations
Memory
operations
ALU_PC <- 1
MemRd <- 1, 0
MemLength <- 1, 0
MemEnable <- 1, 0
PC_RA <- 0
AddrA <- Instr(20 downto 16)
AddrB <- Instr(15 downto 11)
AddrC <- Instr(25 downto 21)
ALU_Op <- 1110
Sin_Sout <- 1
WrIR <- 1, 0
WrPC <- 1, 0
PC_RA <-
ZE_SE <-
IR_RB <-
ALUOp <-
WrPC <-
WrCR <-
WrC <-
Mem_ALU <-
ALU_PC <-
MemLength <-
MemRd <-
MemWr <-
MemEnable <-
Sin_Sout <-
Mem_ALU <-
WrC <-
(Op < 100000)
and (Op > 100111)
(Op >= 100000)
and (Op <= 100111)
Figure 15.16: STATE DIAGRAM AND TIMING FOR CONTROL SUBSYSTEM OF THE PROCESSOR.
49
OPERATION OF THE COMPUTER AND CYCLE TIME
State Register
t0
Control logic
t1
t1
t1
Mux4
t2
t4
Switch
Instruction Register
NS= Execute
ALU_PC=1
MemAddr
MemData
MemRdy=1
Instruction
Mux2
t2
ALU
Register PC
t6
PC+4
PC_RA=0
ALUOp
WrPC=1
WrIR
PC
Clk
t6
Clk
Memory
t3
t5
Figure 15.17: DEPENDENCIES FOR STATE FETCH.
50
STATE EXECUTE
State Register
t7
Control logic
t8
NS= Fetch or Memop t18
Clk
Decode logic
AddrA, AddrB, AddrC
Reg. File
t10
DataA
t9
Instr. specific
control signals
Zero/Sign
Extender
t11
Mux3 Mux2
ALU
t12
t14 ALUData
PC
Mux1
DataC t15
IR
t7
t10
DataB
t13
Reg. File (t16)
t17
Clk
t9
t9 t9
t9
t9
t7
Figure 15.18: DEPENDENCIES FOR STATE EXECUTE.
51
STATE MEMOP
Clk
State Register
t19
Control logic
NS= Fetch
t25
Clk
WrC=1
MemRdy
Reg. File (t24)
t23
DataC
t18
Memory
t21
Switch
t22
Mux1
t25
t15 t20
t19
Figure 15.19: DEPENDENCIES FOR STATE Memop.
52
EXAMPLE 15.1: OBTAIN MIN CYCLE PERIOD
Register Reg delay t
R
2 ns (setup and propagation delay)
Register le RF delay t
RF
4 ns
ALU ALU delay t
ALU
6 ns
Multiplexer Mux delay t
mux
0.5 ns
Zero/sign ext. Ext delay t
ZSE
0.5 ns
Switch Switch delay t
sw
0.5 ns
Control delay Ctrl delay t
ctl
0.5 ns
Decode delay Dec delay t
dec
3 ns
Memory Mem delay t
mem
8 ns (static memory)
CRITICAL PATHS ARE OBTAINED:
t
fetch
= t
R
+ t
ctl
+ t
mux
+ t
mem
+ t
sw
= 2 + 0.5 + 1 + 8 + 0.5 = 12ns
t
exec
= t
R
+ t
ctl
+ t
RF
+ t
mux
+ t
ALU
+ t
mux
+ t
RF
= 2 + 0.5 + 4 + 0.5 + 6 + 0.5 + 4 = 17.5ns
t
memop
= t
R
+ t
ctl
+ t
mem
+ t
sw
+ t
mux
+ t
RF
= 2 + 0.5 + 8 + 0.5 + 0.5 + 4 = 15ns
53
vhdl DESCRIPTION OF IMPLEMENTATION
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE WORK.comp_pkg.ALL, WORK.ALL;
ARCHITECTURE structural OF Processor IS
SIGNAL Instr : WordT;
SIGNAL ZE, NG, CY, OV : STD_LOGIC;
SIGNAL AddrA, AddrB, AddrC : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL ALUOp : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WrC, WrPC, WrCR, WrIR : STD_LOGIC;
SIGNAL Mem_ALU, PC_RA, IR_RB : STD_LOGIC;
SIGNAL ALU_PC, ZE_SE, SinSout: STD_LOGIC;
BEGIN
P1: ENTITY Data_Subsystem
PORT MAP (MemAddr, MemData, IOAddr, IOData,
Instr, ZE, NG, CY, OV, AddrA, AddrB, AddrC, ALUOp,
WrC, WrPC, WrCR, WrIR, Mem_ALU, PC_RA, IR_RB, ALU_PC,
ZE_SE, SinSout, Clk, Reset);
P2: ENTITY Ctrl_Subsystem
PORT MAP (Instr, ZE, NG, CY, OV, AddrA, AddrB, AddrC, ALUOp,
WrC, WrPC, WrCR, WrIR, Mem_ALU, PC_RA, IR_RB, ALU_PC,
ZE_SE, SinSout, MemRd, MemWr, MemLength, MemEnable,
MemRdy, IORd, IOWr, IOLength, IOEnable, IORdy, Status,
Clk, Reset);
END structural;
54
vhdl DESCRIPTION OF DATA SUBSYSTEM
LIBRARY ieee;
USE WORK.comp_pkg.ALL, WORK.ALL;
ENTITY Data_Subsystem IS
PORT(MemAddr : OUT MAddrT ;
MemData : INOUT WordT ;
IOAddr : OUT IOAddrT ;
IOData : INOUT WordT ;
Instr : OUT WordT ;
ZE, NG, CY, OV : OUT STD_LOGIC ;
AddrA, AddrB, AddrC : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
ALUOp : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
WrC, WrPC, WrCR, WrIR : IN STD_LOGIC ;
Mem_ALU, PC_RA, IR_RB : IN STD_LOGIC ;
ALU_PC, ZE_SE, Sin_Sout: IN STD_LOGIC ;
Clk, Reset : IN STD_LOGIC);
END Data_Subsystem;
55
vhdl DESCRIPTION OF DATA SUBSYSTEM (cont.)
ARCHITECTURE structural OF Data_Subsystem IS
SIGNAL DataA, DataB, DataC : WordT ;
SIGNAL Ain , Bin : WordT ;
SIGNAL ALUdata, IRdata : WordT ;
SIGNAL tMemdata : WordT ;
SIGNAL Cond, CRout : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL IRreg, IRext : WordT ;
SIGNAL PCout : WordT:= (OTHERS => 0);
BEGIN
ALU1: ENTITY ALU
PORT MAP(Ain,Bin,ALUop,ALUdata,Cond);
GPR: ENTITY Reg_File
PORT MAP(AddrA,AddrB,AddrC,DataA,DataB,DataC,
WrC,Reset,Clk);
PC: ENTITY Reg
PORT MAP(ALUdata(23 DOWNTO 0),PCout(23 DOWNTO 0),
WrPC,Reset,Clk);
CR: ENTITY Reg
PORT MAP(Cond,CRout,WrCR,Reset,Clk);
ZE <= CRout(0); CY <= CRout(1);
NG <= CRout(2); OV <= CRout(3);
56
IR: ENTITY Reg
PORT MAP(tMemData,IRReg,WrIR,Reset,Clk);
Instr <= IRReg;
MX1: ENTITY Mux
PORT MAP(tMemData,ALUdata,Mem_ALU,DataC);
MX2: ENTITY Mux
PORT MAP(PCout,DataA,PC_RA,Ain);
ZSE: ENTITY Extender
PORT MAP(IRreg,ZE_SE,IRext);
MX3: ENTITY Mux
PORT MAP(IRext,DataB,IR_RB,Bin);
MX4: ENTITY Mux
PORT MAP(ALUdata(23 DOWNTO 0),PCout(23 DOWNTO 0),
ALU_PC,MemAddr);
SL : ENTITY Switch
PORT MAP(MemData,tMemData,DataB,Sin_Sout);
END structural;
57
vhdl DESCRIPTION OF REGISTER FILE
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
ENTITY Reg_File IS
PORT(AddrA, AddrB, AddrC : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DataA, DataB : OUT WordT;
DataC : IN WordT;
WrC : IN STD_LOGIC ;
Reset, Clk : IN STD_LOGIC);
END Reg_File;
ARCHITECTURE behavioral OF Reg_File IS
TYPE RegFileT IS ARRAY(0 to 31) OF WordT;
SIGNAL GPR : RegFileT ;
BEGIN
PROCESS(AddrA,AddrB) -- output function
CONSTANT RF_delay : TIME := 4 ns;
BEGIN
DataA <= GPR(CONV_INTEGER(AddrA)) AFTER RF_delay;
DataB <= GPR(CONV_INTEGER(AddrB)) AFTER RF_delay;
END PROCESS;
58
PROCESS(Reset,Clk) -- transition function
BEGIN
IF (ResetEVENT and (Reset = 1)) THEN
FOR i IN 0 TO 31 LOOP
GPR(i) <= (OTHERS => 0);
END LOOP;
END IF;
IF (ClkEVENT AND Clk = 1 AND WrC = 1) THEN
GPR(CONV_INTEGER(AddrC)) <= DataC;
END IF;
END PROCESS;
END behavioral;
59
vhdl DESCRIPTION OF ALU
LIBRARY ieee;
USE ieee.std_logic_signed.ALL;
ENTITY ALU IS
PORT(A, B: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Op : IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
C : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Cond: OUT STD_LOGIC_VECTOR( 3 DOWNTO 0));
END ALU;
ARCHITECTURE behavioral OF ALU IS
BEGIN
PROCESS(A,B,Op)
CONSTANT ALU_delay : TIME := 6 ns;
BEGIN
CASE Op IS
WHEN "0000" => C <= (OTHERS => 0) AFTER ALU_delay;
WHEN "0001" => C <= A + B AFTER ALU_delay;
WHEN "0010" => C <= A - B AFTER ALU_delay;
WHEN "0100" => C <= A and B AFTER ALU_delay;
WHEN "0101" => C <= A or B AFTER ALU_delay;
WHEN "0110" => C <= A xor B AFTER ALU_delay;
60
WHEN "1000" => C <= A AFTER ALU_delay;
WHEN "1001" => C <= B AFTER ALU_delay;
WHEN "1010" => C <= A(30 DOWNTO 0) & 0 AFTER ALU_delay;
WHEN "1011" => C <= 0 & A(31 DOWNTO 1) AFTER ALU_delay;
WHEN "1100" => C <= A(30 DOWNTO 0) & A(31) AFTER ALU_delay;
WHEN "1101" => C <= A(0) & A(31 DOWNTO 1) AFTER ALU_delay;
WHEN "1110" => C <= A + 4 AFTER ALU_delay;
WHEN "1111" => C <= not(A) AFTER ALU_delay;
END CASE;
Cond <= get_cc(A,B,Op) AFTER ALU_delay;
END PROCESS;
END behavioral;
61
vhdl DESCRIPTION OF REGISTERS
LIBRARY ieee; USE ieee.std_logic_1164.ALL;
ENTITY Reg IS
PORT(Data_in : IN STD_LOGIC_VECTOR;
Data_out: OUT STD_LOGIC_VECTOR;
Wr : IN STD_LOGIC ;
Reset : IN STD_LOGIC ;
Clk : IN STD_LOGIC);
END Reg;
ARCHITECTURE behavioral OF Reg IS
BEGIN
PROCESS(Wr,Reset,Clk)
CONSTANT Reg_delay: TIME := 2 ns;
VARIABLE BVZero: STD_LOGIC_VECTOR(Data_inRANGE):= (OTHERS => 0);
BEGIN
IF (Reset = 1) THEN
Data_out <= BVZero AFTER Reg_delay;
END IF;
IF (ClkEVENT AND Clk = 1 AND Wr = 1) THEN
Data_out <= Data_in AFTER Reg_delay;
END IF;
END PROCESS;
END behavioral;
62
vhdl DESCRIPTION OF OTHER MODULES: MUX
LIBRARY ieee;
ENTITY Mux IS
PORT(A_in,B_in: IN STD_LOGIC_VECTOR;
Sel : IN STD_LOGIC ;
Data_out : OUT STD_LOGIC_VECTOR);
END Mux;
ARCHITECTURE behavioral OF Mux IS
BEGIN
PROCESS(A_in, B_in, Sel)
CONSTANT Mux_delay: TIME := 500 ps;
BEGIN
IF (Sel = 0) THEN
Data_out <= A_in AFTER Mux_delay;
ELSE
Data_out <= B_in AFTER Mux_delay;
END IF;
END PROCESS;
END behavioral;
63
vhdl DESCRIPTION OF EXTENDER
LIBRARY ieee;
ENTITY Extender IS
PORT(X_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ZE_SE : IN STD_LOGIC ;
X_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END Extender;
ARCHITECTURE behavioral OF Extender IS
BEGIN
PROCESS(X_in, ZE_SE)
CONSTANT Ext_delay: TIME := 500 ps;
BEGIN
IF (ZE_SE = 0) THEN
X_out(31 DOWNTO 16) <= (OTHERS => 0) AFTER Ext_delay;
X_out(15 DOWNTO 0) <= X_in(15 DOWNTO 0) AFTER Ext_delay;
ELSE
X_out(31 DOWNTO 16) <= (OTHERS => X_in(15)) AFTER Ext_delay;
X_out(15 DOWNTO 0) <= X_in(15 DOWNTO 0) AFTER Ext_delay;
END IF;
END PROCESS;
END behavioral;
64
vhdl DESCRIPTION OF SWITCH
LIBRARY ieee;
ENTITY Switch IS
PORT(A : INOUT STD_LOGIC_VECTOR;
B_out: OUT STD_LOGIC_VECTOR;
C_in : IN STD_LOGIC_VECTOR;
Sel : IN STD_LOGIC );
END Switch;
ARCHITECTURE behavioral OF Switch IS
BEGIN
PROCESS(A, C_in, Sel)
CONSTANT Switch_delay: TIME := 500 ps;
CONSTANT dataZ: STD_LOGIC_VECTOR(ARANGE):= (OTHERS => Z);
BEGIN
IF (Sel = 0) THEN
B_out <= A AFTER Switch_delay;
A <= dataZ;
ELSE
A <= C_in AFTER Switch_delay;
END IF;
END PROCESS;
END behavioral;
65
vhdl DESCRIPTION OF CONTROL SYSTEM
LIBRARY ieee;
ENTITY Ctrl_Subsystem IS
PORT(Instr : IN WordT ;
ZE, NG, CY, OV : IN STD_LOGIC ;
AddrA, AddrB, AddrC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
ALUOp : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
WrC, WrPC, WrCR, WrIR : OUT STD_LOGIC ;
Mem_ALU, PC_RA, IR_RB : OUT STD_LOGIC ;
ALU_PC, ZE_SE, Sin_Sout: OUT STD_LOGIC ;
MemRd,MemWr : OUT STD_LOGIC ;
MemLength : OUT STD_LOGIC ;
MemEnable : OUT STD_LOGIC ;
MemRdy : IN STD_LOGIC ;
IORd, IOWr : OUT STD_LOGIC ;
IOLength : OUT STD_LOGIC ;
IOEnable : OUT STD_LOGIC ;
IORdy : IN STD_LOGIC ;
Status : OUT StatusT ;
Clk, Reset : IN STD_LOGIC );
END Ctrl_Subsystem;
66
vhdl DESCRIPTION OF CONTROL SYSTEM (cont.)
LIBRARY ieee;
USE ieee.std_logic_signed.ALL;
ARCHITECTURE behavioral OF Ctrl_Subsystem IS
SIGNAL State: StatusT;
BEGIN
PROCESS -- transition function
ALIAS Opcode : STD_LOGIC_VECTOR(5 DOWNTO 0) IS Instr(31 DOWNTO 26);
CONSTANT Reset_delay: TIME:= 500 ps ;
CONSTANT Ctrl_delay : TIME:= 500 ps ;
BEGIN
WAIT ON Clk,Reset;
IF (ResetEVENT AND Reset = 1) THEN
State <= p_reset AFTER Reset_delay;
Status <= p_reset AFTER Reset_delay;
WAIT UNTIL Clk = 1;
END IF;
IF (ClkEVENT) AND (Clk = 1) THEN
CASE State IS
WHEN p_reset => Status <= fetch AFTER Ctrl_delay;
State <= fetch AFTER Ctrl_delay;
WHEN fetch => Status <= execute AFTER Ctrl_delay;
State <= execute AFTER Ctrl_delay;
67
WHEN execute => CASE Opcode IS
WHEN "100000" | "100001" => State <= memop AFTER Ctrl_delay;
Status <= memop AFTER Ctrl_delay;
WHEN "100010" | "100011" => State <= memop AFTER Ctrl_delay;
Status <= memop AFTER Ctrl_delay;
WHEN OTHERS => State <= fetch AFTER Ctrl_delay;
Status <= fetch AFTER Ctrl_delay;
END CASE;
WHEN memop | ioop => Status <= fetch AFTER Ctrl_delay;
State <= fetch AFTER Ctrl_delay;
WHEN undef => NULL;
END CASE;
END IF;
END PROCESS;
PROCESS(State,Instr,MemRdy) -- output function
ALIAS Opcode : STD_LOGIC_VECTOR( 5 DOWNTO 0) IS Instr(31 DOWNTO 26);
ALIAS Imm : STD_LOGIC_VECTOR(15 DOWNTO 0) IS Instr(15 DOWNTO 0);
ALIAS D : STD_LOGIC_VECTOR(15 DOWNTO 0) IS Instr(15 DOWNTO 0);
ALIAS PN : STD_LOGIC_VECTOR(10 DOWNTO 0) IS Instr(10 DOWNTO 0);
CONSTANT Dec_delay : TIME:= 3 ns;
CONSTANT Ctrl_delay : TIME:= 500 ps;
CONSTANT MemRd_delay: TIME:= 2500 ps;
CONSTANT MemRd_pulse: TIME:= MemRd_delay + 3 ns ;
CONSTANT MemWr_delay: TIME:= 2500 ps;
CONSTANT MemWr_pulse: TIME:= MemWr_delay + 3 ns ;
68
TYPE Ctrl_LineT IS
RECORD
MemOp, WrMem : STD_LOGIC;
RS_RB, IR_RB : STD_LOGIC;
WrC, WrPC, WrCR : STD_LOGIC;
ZE_SE : STD_LOGIC;
ALUop : STD_LOGIC_VECTOR(3 DOWNTO 0);
END RECORD;
VARIABLE Ctrl_Line : Ctrl_LineT;
TYPE Ctrl_TableT IS ARRAY(NATURAL RANGE 0 TO 63) OF Ctrl_LineT;
CONSTANT Ctrl_Table: Ctrl_TableT:=
-- Mem Wr RS IR Wr Wr Wr ZE ALU
-- Op Mem RB RB C PC CR SE op
(0 => (0, 0, 1, 1, 0, 0, 0, 0, "0000"), -- nop
2 => (0, 0, 1, 1, 1, 0, 1, 0, "1111"), -- not
4 => (0, 0, 1, 1, 1, 0, 1, 0, "1010"), -- lsh
6 => (0, 0, 1, 1, 1, 0, 1, 0, "1011"), -- rsh
8 => (0, 0, 1, 1, 1, 0, 1, 0, "1100"), -- lrt
10=> (0, 0, 1, 1, 1, 0, 1, 0, "1101"), -- rrt
16=> (0, 0, 1, 1, 1, 0, 1, 0, "0001"), -- add
17=> (0, 0, 1, 0, 1, 0, 1, 1, "0001"), -- adi
18=> (0, 0, 1, 1, 1, 0, 1, 0, "0010"), -- sub
19=> (0, 0, 1, 0, 1, 0, 1, 1, "0010"), -- sbi
20=> (0, 0, 1, 1, 1, 0, 1, 0, "0100"), -- and
21=> (0, 0, 1, 0, 1, 0, 1, 0, "0100"), -- ani
69
22=> (0, 0, 1, 1, 1, 0, 1, 0, "0101"), -- or
23=> (0, 0, 1, 0, 1, 0, 1, 0, "0101"), -- ori
24=> (0, 0, 1, 1, 1, 0, 1, 0, "0110"), -- xor
25=> (0, 0, 1, 0, 1, 0, 1, 0, "0110"), -- xri
32=> (1, 0, 0, 0, 1, 0, 0, 1, "0001"), -- ldb
33=> (1, 0, 0, 0, 1, 0, 0, 1, "0001"), -- ldw
34=> (1, 1, 0, 0, 0, 0, 0, 1, "0001"), -- stb
35=> (1, 1, 0, 0, 0, 0, 0, 1, "0001"), -- stw
36=> (1, 0, 0, 1, 1, 0, 0, 0, "1001"), -- irb
37=> (1, 0, 0, 1, 1, 0, 0, 0, "1001"), -- irw
38=> (1, 1, 0, 1, 0, 0, 0, 0, "1001"), -- iwb
39=> (1, 1, 0, 1, 0, 0, 0, 0, "1001"), -- iww
56=> (0, 0, 1, 0, 0, 1, 0, 1, "0001"), -- br
57=> (0, 0, 1, 0, 0, 1, 0, 1, "1000"), -- bri
48=> (0, 0, 1, 0, 0, 1, 0, 1, "0001"), -- brp
49=> (0, 0, 1, 0, 0, 1, 0, 1, "0001"), -- brn
50=> (0, 0, 1, 0, 0, 1, 0, 1, "0001"), -- bnz
51=> (0, 0, 1, 0, 0, 1, 0, 1, "0001"), -- brz
52=> (0, 0, 1, 0, 0, 1, 0, 1, "0001"), -- bnc
53=> (0, 0, 1, 0, 0, 1, 0, 1, "0001"), -- brc
54=> (0, 0, 1, 0, 0, 1, 0, 1, "0001"), -- bnv
55=> (0, 0, 1, 0, 0, 1, 0, 1, "0001"), -- brv
OTHERS => (0, 0, 1, 1, 0, 0, 0, 1, "0000")
);
70
BEGIN
IF (StateEVENT) THEN
CASE State IS
WHEN undef => NULL;
WHEN p_reset => ALUOp <= "0000";
MemRd <= 0; MemWr <= 0;
MemEnable <= 0; MemLength <= 0;
IORd <= 0; IOWr <= 0;
IOEnable <= 0; IOLength <= 0;
WHEN fetch =>
-- disable write signals from previous cycle
WrCR <= 0 AFTER Ctrl_delay;
WrC <= 0 AFTER Ctrl_delay;
-- fetch instruction
ALU_PC <= 1 AFTER Ctrl_delay;
MemLength<= 1 AFTER Ctrl_delay;
MemEnable<= 1 AFTER Ctrl_delay;
MemRd <= 1 AFTER MemRd_delay, 0 AFTER MemRd_pulse;
Sin_Sout <= 0 AFTER Ctrl_delay; -- switch in
-- increment PC
PC_RA <= 0 AFTER Ctrl_delay;
ALUop <= "1110" AFTER Ctrl_delay; -- PC + 4
WrIR <= 1 AFTER Ctrl_delay;
WrPC <= 1 AFTER Ctrl_delay;
71
WHEN execute =>
-- disable signals from fetch cycle
WrIR <= 0 AFTER Ctrl_delay;
WrPC <= 0 AFTER Ctrl_delay;
-- other actions done by InstrEVENT
WHEN memop | ioop =>
-- initiate memory access
ALU_PC <= 0 AFTER Ctrl_delay; -- address to memory
MemLength<= Opcode(0) AFTER Ctrl_delay; -- operand length
WrC <= Ctrl_Line.WrC AFTER Ctrl_delay;
IF (Ctrl_Line.WrMem = 0) THEN
MemRd <= 1 AFTER MemRd_delay, 0 AFTER MemRd_pulse;
Mem_ALU <= 0 AFTER Ctrl_delay;
ELSE
MemWr <= 1 AFTER MemWr_delay, 0 AFTER MemWr_pulse;
Sin_Sout <= 1 AFTER Ctrl_delay;
END IF;
END CASE;
END IF;
72
IF (InstrEVENT) THEN
-- decode opcode
Ctrl_Line:= Ctrl_Table(CONV_INTEGER(0 & Opcode));
-- decode registers
AddrA <= Instr(20 DOWNTO 16) AFTER Dec_delay;
IF (Ctrl_Line.RS_RB = 0) THEN
AddrB <= Instr(25 DOWNTO 21) AFTER Dec_delay;
ELSE
AddrB <= Instr(15 DOWNTO 11) AFTER Dec_delay;
END IF;
AddrC <= Instr(25 DOWNTO 21) AFTER Dec_delay;
-- decode control signals
PC_RA <= not(Ctrl_Line.WrPC) AFTER Ctrl_delay;
ZE_SE <= Ctrl_Line.ZE_SE AFTER Ctrl_delay;
IR_RB <= Ctrl_Line.IR_RB AFTER Ctrl_delay;
ALUOp <= Ctrl_Line.ALUop AFTER Ctrl_delay;
WrPC <= Ctrl_Line.WrPC AFTER Ctrl_delay;
WrCR <= Ctrl_Line.WrCR AFTER Ctrl_delay;
IF (Ctrl_Line.MemOp = 0) THEN
WrC <= Ctrl_Line.WrC AFTER Ctrl_delay;
Mem_ALU <= 1 AFTER Ctrl_delay;
END IF;
END IF;
73
IF (MemRdyEVENT AND MemRdy=1) THEN
CASE State IS
WHEN memop => IF (Ctrl_Line.WrMem = 1) THEN
-- deactivate data bus
Sin_Sout <= 0 AFTER Ctrl_delay;
END IF;
END CASE;
END IF;
END PROCESS;
END behavioral;

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INTRODUCTION TO COMPUTER, MICROCOMPUTERS and

Address1 (where to save PC);

Not available for Bcc instruction

Twos complement arithmetic

Operators apply to A68K. Different assemblers may support different

Relational operators return 1s (true) or 0s (false).

2 008 Bus Error

25 064 Level 1 interrupt autovector

48-63 0C0-0FC (reserved)

68040 80486 PowerPC Pentium

Source: IEEE Spectrum, December 1993, p. 21

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