5 AdvancedMOSTransistors&AnalogDesign 12-13x2

Analog Integrated Systems
S. Auvanceu N0S Tiansistois anu Analog Besign (S sessions)

#1
Advanced MOS transistor models:
Large Signals. Weak, Moderate and Strong Inversion.
Small Signals #1
Layout Techniques:
The problem; Floorplan; Mismatches; Noise and Crosstalk Latch-up
#2
Introduction to noise in electronic circuits:
Definitions. Filtered noise.
Noise types in components.
Noise analysis for circuits.
#3
4/29/2013 Analog Integrated Systems jrf@ist.utl.pt 2
Advanced Models
Large Signals: Weak-Strong Inversion
2
Strong inversion
2
Subthreshold or Weak in

1
( ) (1 ); ;
2
2

exp ; 1.4 ~1.8
.
version
.
Boundary:
2
2 .
.
n D
m
GS t
D
m
T
m
D D
ox
D GS t DS
E
f BS
G
GS t T G
S
D D
T
G t T
O
S
S
C W
i v V V n
n L V L
V
v
I
g
V V
I
g
nV
g
I I
V V nV V
V V
i I n
nV
nV

= + =
+
| |
=
=
=
=
=
=
|
\
70mV
t
V +
Advanced Models
Large Signals: Weak-Strong Inversion
Bounuaiies uepenu on mouels, technologies anu authois:
"Rules of thumb" foi v
6S
:
Conventional designs: near weak inversion but not in
weak inversion: V
OVD
150mV~200mV.
Advanced Models
Single-Transistor MUS Cain
Bigh uain: v
0vB
; l
.but this leaus to low speeu!
M
1
I
B
V
DD
v
o
v
I
2 2
Example:
10
2
100
00
E E
GS t OVD
E
OVD
V m o
V
A g r
V L V L
V V V
V L V
V
A
mV
= =

=
Advanced Models
Large Signals: Weak-Moderate-Strong
|TSIvIBISj
Advanced Models
Large Signals: Weak Inversion
( )
0
2
.
2 2
1.4
1
2
2
2
0.66
3
:1 3 30 1
exp 1 exp
.
00
D
GS M m
T
t t f SB f
M OX T
f SB
M t T
S B
OX
M
GS M DS
D M
T T
t t
I
V V g
nV
V V v
n
W
I
v V v
i I
C n V
v
L
V V CnV
nV
q N
C
C V V mV V mV
V

< =
(
= + +
(

+

=
=
(
| | | |
=
( | |
\
\

Advanced Models
Large Signals: Strong Inversion
2
GS

( ) (1 );
2
1
1 for long channel
if usually
1.25 f
Strong Inversion: >
or short channel
; 6 +200mV
2
1
1
2
( )
0
2
H H t T t
D
m
GS
ox
D GS t DS
E
n
GS
f A
t
t
A
SB
C W
i v V V
L
V L
v V V V
n
v V
nV V
I
g
V V
v
= +
=
+
= +
= =

=
+
=
+ +
=

Advanced Models
Large Signals: Moderate Inversion
Rules of thumb for v
GS
:
There are unified models. Cost in complexity which
translates in computation time.
There are non-physical based models, fitting on
experimental data as BSIM3
Advanced Models
Large Signals: .at tbe bigber end
At high v
GS
current becomes more linear again;
Mainly due to velocity saturation
Increase in electric field does not cause electrons to travel
through the channel faster due to colisions.

7 7
10 cm/s 10
_
cm/s
Velocity saturation
( ) is absolute max
does not depend on is a constant; not used for analog
VS
DS ox SAT GS t ox SAT
GS
m SAT
i WC V v V WC V g
v

= =
Advanced models
Small Signals: Transconductance
Strong Inversion: Saturation
2 1 1 1
= ( ) 2
2
Strong Inversion: Triode =
Weak Inversion: =
GS GS
D
m
GS
v V
D
m OX GS t OX D
GS t
m OX DS
D
m
T
i
g
v
I W W
g C V V C I
L V V L
W
g C V
L
I
g
nV

= =

Advanced models
Small Signals: Transconductance
'
0
2
0
0
1
/ /
2
m m D
T
DS
OX T GS t
I
g I g I I
nV
I W
I C nV IC V V
L I
=
= =
l
o
g

|
m
S
/
m
A
|
Advanced models
Small Signals: Bulk transconductance and D-S conductance
[ ]
, ,
;
= ( -1)
= 0.1 to 0.3
GS DS BS
GS GS DS DS
t D D
mb m
BS t BS
V V V
mb m
D D D
ds
DS DS E
v V v V
V i i
g g n
v V v
g g
i i I
g
v v V L
= =

= =

= =

r
o
,
r
ds
,
g
ds
v
gs
G
D
S
g
mb
v
bs
g
m
v
gs
B
v
bs
Advanced models
Capacitance
Advanced models
Capacitance {intrinsic]
_
_
_ _
_
_
_
_ _
_
Weak Inversion
1
Strong Inversion
triode ( =0): saturation:
2
1
3
2
0
0
3
2 2
2
2 2
gb i OX
DS
gs i OX
gs i gd i OX
gd i
gb i
OX
OX
gb i
bs i bd i
f SB DS
f SB
bs i
n
C W L C
n
V
C W L C
C C W L C
C
C
W L C
W L C
C
C C
V V
V
C
= =

=
= =

=
_
2
2 2
0
OX
f SB
bd i
W L C
V
C


Advanced models
Capacitance {extrinsic]
_ _
_
_ _
gs e gd e W
gb e L
bs e bd e S S
C C W C
C L C
C C A P
= =
= = +
Bettei to uesign fingei tiansistois insteau of a "big"

tiansistoi. Reuuces the aiea of uiain anu souice by two.
Advanced models
Capacitance
Simple Current SourceJMirror
Mismatcb
REF
REF
Mismatch in Weak inversion
Mismatch in Strong invers
exp 1 15%
. .
( ) ( / )
ion
2
1 6 ~ 10%
/
Better!
OUT t t
T T
OUT n ox
t
n ox GS t
i V V
I nV nV
i C W L
V
I W L C v V
| |

+
|
\

+ + +

#1
Small Signals #1
Layout Techniques:
#2
#3
Introduction
Impoitant to know well the technology available anu
wanteu specifications. It avoius wasting effoit in ciicuits
than cannot achieve the uesiieu peifoimance uue to
element ueviations that cannot be oveicome by ciicuit
techniques
Souices of eiioi in mixeu ciicuits aie ielateu to the
inteiconnection of the uiffeient blocks, theii position in the
flooiplan, anu the iouting of supply lines, clock anu
RFanalogue signals.
Ciicuits peifoimance is limiteu by noise, ciosstalk anu
tempeiatuie giauients which CANNUT usually be uetecteu
fiom computei simulation.
Introduction
The layout of piecise analogueRF ciicuits togethei
with uigital ciicuitiy in the same substiate follow
stiingent guiuelines to
- planning the flooiplan anu the connection to the
exteiioi;
- uesigning the layout to ieuuce mismatches;
- iouting the supply lines, clock anu analogue signals in
such a way as to ieuuce noise anu ciosstalk;
- pieventing latch-up;
- uesigning foi testability.
Introduction
Introduction
V
DD
Input
Pad
v
O
M
1
M
2
R
D
1
D
4
D
3
D
2
Floorplan
is a complexinteiactive evolutive piocess
- uepenus on the type of encapsulation,
- numbei of pins
- uie size
- influenceu by the layout of the inuiviuual cells
When planning the flooiplan the following
guiuelines shoulu be taken into account:
- RFAnalogue anu uigital ciicuits shoulu be sepaiateu.
- Routing of powei supply, bias lines, signal lines anu
clock shoulu be cleaily iuentifieu.
- The paiasitics in the layout shoulu be balanceu
Floorplan
Floorplan
The assignment of signals to paus
The analogue anu uigital powei supplies must have sepaiate pins; if
this is not possible they shoulu be sepaiateu anu only connecteu at
the paus. Remembei that the voltage ueviation is given by
dd
C DD B
di
V R I L
dt
= +
Floorplan
The analogue signals anu
powei supplies shoulu be
connecteu to the miuule
pins because this leaus to
shoitei connections anu,
hence to lowei paiasitic
inuuctance anu capacitance
Package Pin Bond L Bond C
40 Pin Plastic 1,2
10,11
15nH
4.4nH
2.4pF
0.7pF
40 Pin Plastic
with socket
1,2
10,11
18.6nH
7.6nH
2.6pF
0.8pF
40 Pin Ceramic 1,2
10,11
20.9nH
9.0nH
2.7pF
0.8pF
In RF/fast analog use smaller packages or chip on board
Floorplan
The analogue paus shoulu be kept away fiom the uigital
inputs oi outputs, anu shoulu nevei be placeu between
them.
Powei lines wiuth capable of suppoiting the BC cuiients;
electio migiation foi pulseu cuiients may leau to wiuths
that aie an oiuei of magnituue highei than foi BC
cuiients.
Lines length must be evaluateu. Line iesistance is not
always negligible anu voltage uiops of a few mv can
piouuce significant peifoimance uegiauation in
analogue paits.
uiounu planes shoulu be all ovei to avoiu giounu cuiient
loops.
Floorplan
The paiasitics in a line aie:
Resistance
Capacitance
[ ] [ ]
[ ]
2
int int int
/ / /
/ F/cm F
S line S
ox line
R t R R L W
C x C C LW
= =
( = =


Floorplan
If necessaiy multiple powei-bus pins shoulu be useu. It is
usually veiy uifficult to ioute the powei bus without
iesistive cioss-unueis thiough metal layeis.
Tiee type iouting avoius uiffeient piopagation times. It
incieases paiasitics.
Mismatcbes
Component matching accuiacy uepenus on technology.
Bipolai tiansistois aie 1u times moie accuiate than N0S tiansistois
poly-to-poly oi poly-to-n+ capacitois aie moie piecise than metal-to-
poly capacitois.
Bigital Technology iequiie stiuctuies less sensitive to mismatches oi
special techniques such as self-calibiation, oveisampling, tiimming, etc.
Layout iules to ieuuce mismatches
- Elements with same stiuctuie.
- Bevices at minimum uistance to take auvantage of spatial coiielation .
- Bevices with same oiientation to avoiu anisotiopic effects
- Souice to uiain cuiient flowing paiallel specially in uiffeiential stiuctuies.
Mismatcbes
The uevices shoulu have
the same shape anu same
size anu not only the same
aspect iatios to
compensate etching eiiois.
Mismatcbes
The layout shoulu be
common-centioiu
geometiy to compensate
constant giauient of
paiameteis; this is most
commonly useu in paiis
of tiansistois anu sets of
capacitois
Mismatcbes
Foi iesistoi lauueis theie is no neeu to use common-centioiu
techniques because of theii complexity anu it is piefeiable to
use
Mismatcbes
Use top metal layers andJor differential inductor wben
possible
uiauually ieuuce metal wiuth: saves aiea anu maintains the
same iesistanceinuuctance iatio in each tuin.
The uiffeiential inuuctoi can achieve highei self iesonating
fiequencies anu twice the quality factoi of a single enueu
inuuctoi with the same aiea.
Mismatcbes
Nagnetic coupling of the tiansfoimei allows moie
inuuctance without having to inciease the inuuctoi size,
anu incieases the quality factoi by a factoi of K (coupling
between tiansfoimei spiials).
Besign inuuctois anu tiansfoimeis away fiom othei
ciicuit elements.
Mismatcbes
Bevices at same tempeiatuie (isotheim); the components
shoulu be implementeu symmetiically with iespect to the
uissipative uevices
The elements shoulu have similai suiiounuings (uummies)
Minimum size should be
avoided, higher capacitance and
higher area. Transistors
matching is proportional to
1
W L

Noise and Crosstalk
All noues aie capacitively anu iesistively coupleu to the
common substiate: uominant souice of ciosstalk
To ieuuce noise anu ciosstalk obey
- Run clock anu as close anu balanceu.
- Shaipen clock euges locally (buffeis), avoiu a high slope clock
with high eneigy tiavelling thiough the chip.
- Incluue intei-bus capacitance when calculating bus loauing foi
clock uiiveis.
0ptimize the uelay in a uigital buffei with N stages scaleu
by K iatio
clock
1/
ln
N
L L
i i
C C
N K
C C
| | | |
= =
| |
\ \
Noise and Crosstalk
Plan clock uistiibution
Noise and Crosstalk
0se iobust non-oveilapping clock
geneiatois: it ieuuces speeu but
impioves ieliability
Biue analogue uecisions fiom
clock tiansitions
Sepaiate paiallel analogue lines
fiom uigital lines with a giounu
line
Clock Distribution
Two phases
Noise and Crosstalk
Sepaiate uigital powei supplies all the way to the pau anu
the boaiu. Again, bewaie of local l Ji,Jt foiwaiu biasing anu
giounu bounce.
Run sepaiate wiies foi substiate anu well contacts fiom the
powei supplies. Connect them at the pau oi at some
convenient point. Bewaie of l Ji,Jt
Biffeiential logic uoes not pievent switching tiansients on
the powei supply. Cuiient spikes still has to be pioviueu. 0se
low noise logic (ex. CBL)
Latcb-up
Latch-up iesult eithei fiom bau layout techniques oi fiom
impiopei ciicuit uesign.
Clean BRC pievents latch up occuiiing in uigital ciicuitiy.
Latch-up tenus to occui especially in mixeu analogue-uigital
ciicuits poweieu by uiffeient supplies. To pievent
Eveiy well must have a substiate contact of the appiopiiate
type.
Eveiy substiate contact shoulu be connecteu by metal
uiiectly to a supply pau.
Latcb-up
Substiate contacts placeu close to souice connecteu to the
supply iails
A substiate contact shoulu be useu foi S-1u logic tiansistois.
Layout of n- anu p- tiansistois shoulu have packing of n-
uevices towaius v
SS
anu packing of p-uevices towaius v
BB
Avoiu stiuctuies that inteiwine n- anu p- uevices
The n- anu p- uiivei tiansistois shoulu be physically
sepaiateu (i.e., with the bonuing pau).
p+ guaiu iings aiounu n-tiansistois connecteu to v
SS
n+ guaiu iings aiounu p-tiansistois connecteu to v
BB
Testing
veiy few mixeu analogue-uigital ciicuits woik on the fiist
silicon, uesign to pioviue eiioi uetection by
- iouting in top metal layei acessible by a piobing neeule.
- Auuit all ciicuit blocks foi piobe capability anu biing points to top
metal layei without passivation holes
- Besign ciicuits with the ability to uiive the piobe without affecting
the cell peifoimance.
- Avoiu uaisy chain stiuctuies
- 0se of non-minimum spacing easiei to cut anu sepaiate
#1
Small Signals #1
Layout Techniques:
#2
#3
Noise
Small signals
Lineai
- uain (constant)
- Noise
Laige signals
Non-lineai
- uain
- Bistoition
Noise: Inheient noise: ianuom noise
Inteifeience noise: may oi may not be
ianuom
Noise
Inheient Noise is a ianuom inteifeience not coiielateu with
the signal
In electionic ciicuits:
- Noise is chaiacteiizeu by the ims (ioot mean squaie) of a vaiiable,
voltage oi cuiient
- Capacitois anu Inuuctois uo not contiibute to noise
- Tbermol noise (ianuom movement of caiiieis in a iesistance)
- Sbot noise (white noise uue to the chaiges movement thiough an
eneigy baiiiei)
- Ilicker noise (ianuom apiisioneu chaiges between the oxiue anu
silicon)
2 2
0
1
Noise power lim ( )
T
rms
t
x t dt X
T
= =
}
Noise
Time-domain Analysis
We assume all noise signals have mean value of zeio.
ims value
SNR
[ ]
1/ 2 1/ 2
2 2
n(rms) n(rms) n(rms) n(rms)
0 0
2
n(rms)
2
n(rms)
1 1
( ) ( )
normalized value: W
1
T T
diss
V v t dt I i t dt
T T
V
P V
( (
= =
( (

= =
} }
2
X(rms) X(rms)
2
n(rms) n(rms)
signal power
SNR 10log
noise power
example: SNR 10log 20log
V V
V V
(
=
(

( (
= =
( (
( (

Noise
0nits of uBm
Noise summation
[ ]
n(rms)
[mW]
dBm 10log
1 mW
example: 1 mW 0 dBm; 1W 30 dBm
on a 50 resistor: 0 dBm 50 1mW 0.2236V
P
P
V
(
=
(

= =
n1(rms) n2(rms)
no n1 n2
2 2 2 2
no(rms) n1(rms) n2(rms) n1(rms) n2(rms) n1 n2
0 0
2
( ) ( ) ( )
1 2
( ) ( ) ( ) ( )
correlation coefficient -1 1 =0 uncorrelated
T T
CV V
v t v t v t
V v t v t dt V V v t v t dt
T T
C C C
= +
( = + = + +

} }

Noise
Noise summation
- To ieuuce oveiall noise, ieuuce the highest souice! Is moie
efficient!
2 2 2
no(rms) n1(rms) n2(rms)
n1(rms) n2(rms) no(rms)
example: uncorrelated
10V; 5V 11.2V
V V V
V V V
= +
= = =
Noise
Frequency-domain Analysis
Noise spectial uensity
- Noimalizeu in a 1Bz banuwiuth
- in a single fiequency is zeio
- In a spectium analyzei it uepenus on the iesolution banuwiuth
Noise
White noise
1f oi Flickei oi pink noise
( )
V
n
K
V f
f
=
Noise
Filteieu noise
Noise
Basic components
( )
2
2 1
2
0
2 2 1
2 2 1
Noise spectral density: ; depending on frequency,
[units of ] Hz
Noise Power ( )
1) Thermal noise (white):
Resistors: MOS Transistors :
4 V Hz
1
4 A Hz
: 1 k ; 300K
T
n
n
x f
x
x f df
v kTR
i kT
R
ex R T
=
( =

( =

= =
}
2 2 1
2 2 1
_
1
4 V Hz
4 A Hz
;
: 2 / 3 for long channels,
1 MHz; 0.2V
1 for short channels (empirical)
n
m
n m
n rms
v kT
g
i kT g
ex
f v
( =

( =

=
= =
=
Noise
Basic components
2 2 1
2 2 1
-25 2
2) noise in forward biased junctions:
2 A Hz
quiescient current white noise
3) noise in MOS :
1
V Hz
depends on technology (in the order of 10 V F)
freque
(
=

(
=

n C
n
ox
Shot
i qI
Flicker
K
v
C WL f
K
ncy dependent: "1/ noise" f
Noise
Basic components
|}ohnsNaitinj
Noise
|}ohnsNaitinj
Noise Analysis
of an Input-stage CMUS amplifier
V
DD
M
5
M
3
M
2
M
1
M
4
v
in- v
in+
v
out
v
n5
(t)
v
n1
(t) v
n2
(t)
v
n3
(t)
v
n4
(t)
( )
( ) ( )
1
1 2
3
3 4
5
5 3
2 2
2 2 2
1 1 3 3
2
2 2 2 3
1 3
1
2
output referred noise
( ) 2 ( ) 2 ( )
input referred noise
( ) 2 ( ) 2 ( )
no no
m o
n n
no no
m o
n n
no m
n m
no m o n m o n
m
neq n n
m
V V
g R
V V
V V
g R
V V
V g
V g
V f g R V f g R V f
g
V f V f V f
g
= =
= =
= <<
= +
| |
= +
|
\
Noise Analysis
( )
2
2
2 3
1
1 3 1
2
for white noise term:
2 1
( ) 4
3
input referred noise
16 1 16 1
( ) should be as large as possible to minimize noise
3 3
for the 1/ term : 2 /
(
ni
mi
m
neq m
m m m
mi i ox Di
i
neq
V f kT
g
g
V f kT kT g
g g g
f g C W L I
V
| |
=
|
\
| |
= +
|
\
=
( )
( )
2
2 2 2 2 3 3
1 3 1 3
1
1
/
) 2 ( ) 2 ( ) 2 ( ) 2 ( )
/
n
m
n n n n
m p
W L
g
f V f V f V f V f
g W L
(
| |
= + = +
(
|
( \

2 2 3 1 1
2
1 1 1 3
1 2
( ) ( )
i n
ni neq
ox i i ox p
K K L K
V f V f
C W L f C f W L W L
(
= = +
(
(

Noise Analysis
NN0S 1f noise > PN0S 1f noise
l
S
laige (limits common-moue, can inciease W
S
to
compensate uoes not affect noise)
W
1
laige ; l
1
small
2
1
2
1 2 2 3 1 1 1 2
(rms)
2 2
1 1 1 3 1 1 1 1 3
ln
2
( ) 2 ln
p
f
ox
n n n
neq neq
ox p ox p f
K
f
C f
K L K L K f
V f V
C f W L W L W L C f W L

(
| |
( |
(
| |
\
(
= + = +
(
|
(
( \

(
(

}

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Analog Integrated Systems

S. Auvanceu N0S Tiansistois anu Analog Besign (S sessions)

4/29/2013 Analog Integrated Systems jrf@ist.utl.pt 8

4/29/2013 Analog Integrated Systems jrf@ist.utl.pt 11

4/29/2013 Analog Integrated Systems jrf@ist.utl.pt 15

Bettei to uesign fingei tiansistois insteau of a "big"

Analog Integrated Systems

4/29/2013 Analog Integrated Systems jrf@ist.utl.pt 29

4/29/2013 Analog Integrated Systems jrf@ist.utl.pt 38

4/29/2013 Analog Integrated Systems jrf@ist.utl.pt 51

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Analog Integrated Systems

S. Auvanceu N0S Tiansistois anu Analog Besign (S sessions)

4/29/2013 Analog Integrated Systems jrf@ist.utl.pt 8

4/29/2013 Analog Integrated Systems jrf@ist.utl.pt 11

4/29/2013 Analog Integrated Systems jrf@ist.utl.pt 15

Bettei to uesign fingei tiansistois insteau of a "big"

Analog Integrated Systems

4/29/2013 Analog Integrated Systems jrf@ist.utl.pt 29

4/29/2013 Analog Integrated Systems jrf@ist.utl.pt 38

4/29/2013 Analog Integrated Systems jrf@ist.utl.pt 51

S-ar putea să vă placă și

5 AdvancedMOSTransistors&AnalogDesign 12-13x2

5 AdvancedMOSTransistors&AnalogDesign 12-13x2