Email: project@tripleninfotech.

com


Triple N Infotech T.Nagar Chennai -17 Triple N Infotech Salai Road Trichy-18
Contact No:-044-42868371, 9566234284 Contact No:-0431-4050403, 7200021404

www.tripleninfotech.com
IEEE 2014-2015 PROJECT CAPTION VLSI
Sl.No PROJECT CAPTION
TNIVI1
An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel
Conditional Probability
TNIVI2 Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
TNIVI3 A Low Power Linear Phase Programmable Long Delay Circuit
TNIVI4
VLSI Implementation of an Adaptive Edge-Enhanced Color Interpolation
Processor for Real-Time Video Applications
TNIVI5
Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for
Efficient FIR Filter Implementation
TNIVI6
Efficient FPGA and ASIC Realizations of DA-Based Reconfigurable FIR Digital
Filter
TNIVI7
An Efficient VLSI Architecture of A Reconfigurable Pulse-Shaping FIR
Interpolation Filter for Multi Standard DUC
TNIVI8
Low Power FSK Receiver Using an Oscillator-Based Injection-Locked Frequency
Divider
TNIVI9
Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded
DRAM
TNIVI10
Low-Power Pulse-Triggered Flip-Flop Design Based on A Signal Feed-Through
Scheme
TNIVI11 Dual-Metastability Time-Competitive True Random Number Generator
TNIVI12 High Speed Low-Power Viterbi Decoder Design for TCM Decoders
TNIVI13 Efficient Parallel Turbo-Decoding for High-Throughput Wireless Systems
TNIVI14
Designing A SAR-Based All-Digital Delay-Locked Loop With Constant
Acquisition Cycles Using A Resettable Delay Line
TNIVI15 Fast Radix-10 Multiplication Using Redundant BCD Codes
TNIVI16 A 5.8-Ghz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler
TNIVI17
A Novel Direct Injection-Locked QPSK Modulator Based on Ring VCO in 180 Nm
CMOS
TNIVI18 Quaternary Logic Lookup Table in Standard CMOS
TNIVI19
An FPGA Based High Speed IEEE-754 Double Precision Floating Point Multiplier
Using Verilog
Email: project@tripleninfotech.com


Triple N Infotech T.Nagar Chennai -17 Triple N Infotech Salai Road Trichy-18
Contact No:-044-42868371, 9566234284 Contact No:-0431-4050403, 7200021404

www.tripleninfotech.com
TNIVI20 Design and Implementation of Truncated Multipliers for Precision Improvement
TNIVI21 A High Speed Binary Floating Point Multiplier Using DADDA Algorithm
TNIVI22
High Performance and Power Efficient 32-Bit Carry Select Adder Using Hybrid
PTL/CMOS Logic Style
TNIVI23
VLSI Implementation of Fast Addition Using Quaternary Signed Digit Number
System
TNIVI24
Design of High Speed Low Power Multiplier Using Reversible Logic: A Vedic
Mathematical Approach
TNIVI25 Design of High Performance 64 Bit MAC Unit
TNIVI26 Enhanced Area Efficient Architecture for 128 Bit Modified CSLA
TNIVI27
Least Complex S-Box and its Fault Detection for Robust Advanced Encryption
Standard Algorithm
TNIVI28 Optimized Reversible Vedic Multipliers for High Speed Low Power Operations
TNIVI29 Adaptive Low Power RTPG for BIST Based Test Applications
TNIVI30 ADPLL Design and Implementation on FPGA
TNIVI31
DC Noise Margin and Failure Analysis of Proposed Low Swing Voltage SRAM
Cell for High Speed CMOS Circuits
TNIVI32 A Design Approach of Low Power VLSI for Down Sampler
TNIVI33 Design and Analysis of Scan Power Reduction Based on LFSR Reseeding
TNIVI34 Low Power Low Area High Throughput Adaptive FIR Based on DA Project
TNIVI35 Area-Delay Efficient Binary Adders in QCA
TNIVI36 Achieving Reduced Area by Multi-Bit Flip Flop Design
TNIVI37 FPGA Implementation of High Speed 8-Bit Vedic Multiplier Using Barrel Shifter.
TNIVI38 The Design of High Speed UART
TNIVI39
Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density
Parity Check (EG-LDPC) Codes
TNIVI40 Multi-Operand Redundant Adders on FPGA
TNIVI41
The LUT-SR Family of Uniform Random Number Generators for FPGA
Architectures