Fabrication, Characterization, and Modeling of Metallic Source/drain Mosfets

Fabrication, characterization, and
modeling of metallic source/drain

MOSFETs

Doctoral Thesis
by
Valur Gumundsson

Stockholm, Sweden
2011

Integrated Devices and Circuits
School of Information and Communication Technology (ICT)
KTH Royal Institute of Technology

ii

Fabrication, characterization, and modeling of metallic source/drain
MOSFETs
A dissertation submitted to KTH Royal Institute of Technology, Stockholm, Sweden, in
partial fulfillment of the requirements for the degree of Teknologie Doktor (Doctor of
Philosophy)

TRITA-ICT/MAP AVH Report 2011:15
ISSN 1653-7610
ISRN KTH/ICT-MAP/AVH-2011:15-SE
ISBN 978-91-7501-161-5

2011 Valur Gumundsson

Cover image: Tri-gate SB-MOSFET. (top) Schematic drawing, (bottom) top-view SEM
image, (small inset) cross-sectional TEM of the tri-gate channel.
iii

Valur Gumundsson: Fabrication, characterization, and modeling of metallic source/drain
MOSFETs, Integrated Devices and Circuits, School of Information and Communication
Technology (ICT), KTH Royal Institute of Technology, Stockholm 2011.
TRITA-ICT/MAP AVH Report 2011:15, ISSN 1653-7610, ISRN KTH/ICT-MAP/AVH-
2011:15-SE, ISBN 978-91-7501-161-5

Abstract
As scaling of CMOS technology continues, the control of parasitic source/drain (S/D)
resistance (R
SD
) is becoming increasingly challenging. In order to control R
SD
, metallic
source/drain MOSFETs have attracted significant attention, due to their low resistivity,
abrupt junction and low temperature processing (700 C). A key issue is reducing the
contact resistance between metal and channel, since small Schottky barrier height (SBH) is
needed to outperform doped S/D devices. A promising method to decrease the effective
barrier height is dopant segregation (DS). In this work several relevant aspects of Schottky
barrier (SB) contacts are investigated, both by simulation and experiment, with the goal of
improving performance and understanding of SB-MOSFET technology:
First, measurements of low contact resistivity are challenging, since systematic error
correction is needed for extraction. In this thesis, a method is presented to determine the
accuracy of extracted contact resistivity due to propagation of random measurement error.
Second, using Schottky diodes, the effect of dopant segregation of beryllium (Be),
bismuth (Bi), and tellurium (Te) on the SBH of NiSi is demonstrated. Further study of Be is
used to analyze the mechanism of Schottky barrier lowering.
Third, in order to fabricate short gate length MOSFETs, the sidewall transfer
lithography process was optimized for achieving low sidewall roughness lines down to
15 nm. Ultra-thin-body (UTB) and tri-gate SB-MOSFET using PtSi S/D and As DS were
demonstrated. A simulation study was conducted showing DS can be modeled by a
combination of barrier lowering and doped Si extension.
Finally, a new Schottky contact model was implemented in a multi-subband Monte
Carlo simulator for the first time, and was used to compare doped-S/D to SB-S/D for a
17 nm gate length double gate MOSFET. The results show that a barrier of 0.15 eV is
needed to comply with the specifications given by the International Technology Roadmap
for Semiconductors (ITRS).

Keywords:

Metallic source/drain, contact resistivity, Monte Carlo, NiSi, PtSi, SOI, UTB, tri-gate,
FinFET, multiple-gate, nanowire, MOSFET, CMOS, Schottky barrier, silicide, SALICIDE.
v

Table of contents

Abstract ................................................................................................................................. iii
Table of contents .................................................................................................................... v
List of appended papers ........................................................................................................ vi
Related work not included in the thesis ............................................................................... vii
Summary of appended papers ............................................................................................. viii
Acknowledgements............................................................................................................... ix
List of symbols and acronyms ............................................................................................... x
1. Introduction ................................................................................................................... 1
2. Metal-Semiconductor contacts ...................................................................................... 5
2.1 Current transport .................................................................................................. 5
2.2 Modeling of Schottky barrier height .................................................................... 8
2.3 Ohmic contacts ................................................................................................... 11
2.3.1 Contact resistivity measurements ................................................................... 12
3. MOSFETs ................................................................................................................... 17
3.1 MOSFET fundamentals and scaling ................................................................... 17
3.2 Fully depleted MOSFETs ................................................................................... 22
3.3 Schottky barrier MOSFETs ................................................................................ 24
3.3.1 Fundamentals of SB-MOSFETs ..................................................................... 25
3.3.2 SB-MOSFETs with doped extensions ............................................................ 28
4. Metal silicides and dopant segregation ....................................................................... 33
4.1 Choice of silicides .............................................................................................. 33
4.2 Dopant segregation ............................................................................................. 35
4.3 Dopant segregation on NiSi ............................................................................... 37
4.4 Modeling of dopant segregation ......................................................................... 41
5. SB-MOSFETs: fabrication and characterization ......................................................... 47
5.1 Sidewall transfer lithography ............................................................................. 47
5.2 Device fabrication .............................................................................................. 52
5.3 Electrical characteristics ..................................................................................... 54
5.4 State-of-the-art ................................................................................................... 57
6. Modeling of transport in short channel SB-MOSFETs ............................................... 59
6.1 The multi-subband Monte Carlo method ........................................................... 59
6.2 Implementation of Schottky barriers .................................................................. 61
6.3 Schottky diode simulator .................................................................................... 63
6.4 Current transport in nanoscale SB-MOSFETs.................................................... 66
7. Summary and future outlook ....................................................................................... 69
References ........................................................................................................................... 71

vi

List of appended papers
I. Error propagation in contact resistivity extraction using cross-bridge Kelvin
resistors
V. Gudmundsson, P-E. Hellstrm, and M. stling,
In manuscript, intended for Transactions of Electron Devices.

II. Effect of Be segregation on NiSi/Si Schottky barrier heights
V. Gudmundsson, P-E. Hellstrm, and M. stling,
Proceedings of 41st European Solid-State Device Research Conference (ESSDERC),
2011.

III. Direct measurement of sidewall roughness on Si, poly-Si and poly-SiGe by AFM
V. Gudmundsson, P.-E. Hellstrm, S.-L. Zhang, and M. stling,
Journal of Physics: Conference Series, vol. 100, Mar. 2008.

IV. Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low
Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation
V. Gudmundsson, P.-E. Hellstrom, J. Luo, J. Lu, S.-L. Zhang, and M. Ostling,
IEEE Electron Device Letters, vol. 30, May. 2009, pp. 541-543.

V. Characterization of dopant segregated Schottky barrier source/drain contacts
V. Gudmundsson, P.-E. Hellstrom, S.-L. Zhang, and M. Ostling
10th International Conference on Ultimate Integration of Silicon (ULIS), pp. 73-76,
2009.

VI. Multi-subband Monte Carlo simulation of fully-depleted silicon-on-insulator
Schottky barrier MOSFETs
V. Gudmundsson, P. Palestri, P.-E. Hellstrm, L. Selmi, and M. stling,
11th International Conference on Ultimate Integration of Silicon (ULIS), 2010.

VII. Investigation of the performance of low Schottky barrier MOSFETs using an
improved Multi-subband Monte Carlo model
V. Gudmundsson, P. Palestri, P-E. Hellstrm, L. Selmi, and M. stling,
Submitted to Transactions of Electron Devices.

vii

Related work not included in the thesis
[1] M. stling, J. Luo, V. Gudmundsson, P.-E. Hellstrm, and B.G. Malm, Integration of
metallic source/drain (MSD) contacts in nanoscaled CMOS technology, 10th IEEE
International Conference on Solid-State and Integrated Circuit Technology (ICSICT),
pp. 41-45. Nov. 2010.

[2] M. stling, J. Luo, V. Gudmundsson, P.-E. Hellstrm, and B.G. Malm, Nanoscaling
of MOSFETs and the implementation of Schottky barrier S/D contacts, 27th
International Conference on Microelectronics Proceedings (MIEL), 2010 pp. 9-13,
May. 2010.

[3] M. stling, V. Gudmundsson, P-E. Hellstrm, J. Luo, Z. Zhang, Z. Qiu, B.G. Malm
and S-L. Zhang, Implementation of Schottky Barrier contact technology in ultra
scaled MOSFETs, 1st International Workshop on Si based nano-electronics and
photonics (SiNEP), Sep. 2009.

[4] M. stling, V. Gudmundsson, P.-E. Hellstrm, B.G. Malm, Z. Zhang, and S.-L. Zhang,
Towards Schottky-barrier source/drain MOSFETs, 9th International Conference on
Solid-State and Integrated-Circuit Technology (ICSICT), pp. 146-149, Oct. 2008.

viii

Summary of appended papers
Paper I. This paper explores propagation of random measurement error when using
systematic error correction for the cross-bridge Kelvin resistor. This is accomplished by
providing generalized curves for estimating the propagation of measurement error on the
extracted resistivity. The author has performed 100% of the simulation work, 100% of the
data analysis, and 90% manuscript writing.
Paper II. This paper presents the effect of Be dopant segregation on the Schottky barrier
height of NiSi. The author has performed 100% of the experimental work, 100% of the
measurements, 100% of the data analysis, and 90% manuscript writing.
Paper III. This paper presents direct measurements of rougness for dry-etched Si and SiGe
sidewalls by AFM, for the purpose of reducing line-edge roughness of the MOSFET gate.
The author has performed 90% of the experimental work, 100% of the measurements, 80%
of the data analysis, and 80% manuscript writing.
Paper IV. This paper presents ultra-thin-body and tri-gate SB-MOSFETs using PtSi-
source/drain metal and As dopant segregation. The author has performed 90% of the
experimental work, 100% of the measurements, 80% of the data analysis, and 80%
manuscript writing.
Paper V. This paper is a simulation study of the utra-thin-body devices presented in Paper
IV. The dependence of R
SD
on gate bias is used to analyse if dopant segregated devices
behave as Schottky or ohmic contacts. The author has performed 100% of the simulation
work, 80% of the data analysis, and 90% manuscript writing.
Paper VI. This paper presents preliminary simulation study of SB-MOSFETs using the
multi-subband Monte Carlo (MSMC) method. To our knowledge this is the first paper using
SB contacts in a MSMC simulator. The author has performed 90% of the simulation work,
70% of the data analysis, and 70% manuscript writing.
Paper VII. This paper is a extension of Paper VI. The SB contact model is validated by
comparison to full quantum simulations. A study of the 2015 International Technology
Roadmap for Semiconductors (ITRS) high-performance node is presented, comparing
doped S/D to SB-S/D. The author has performed 90% of the simulation work, 70% of the
data analysis, and 70% manuscript writing.
ix

Acknowledgements
This thesis summarizes my work for the last five years as a Ph.D. student at KTH.
During this work I have received help from many people.
First of all, I want to thank Docent Per-Erik Hellstrm, who has been my supervisor for
both my M.Sc. and Ph.D. work, for his invaluable advice, support and patience during this
time. Prof./Dean Mikael stling has been my co-supervisor and first suggested that I do a
M.Sc. project at the Integrated Devices and Circuits group. He has always encouraged me
in my work and given me good advice. I am also grateful for his vision to build up and
maintain a first class research facility which enabled this work. Prof. Shi-Li Zhang I want to
thank for our collaboration during the first part of my work and for his dedication and
interest in research, which I always find inspiring.
My work builds on the excellent work done by previous Ph.D. students, especially the
work of Dr. Zhen Zhang and Dr. Jun Luo. I want to thank them for their discussions and
collaboration during this work.
I would also like to thank Prof. Carl-Mikael Zetterling, Prof. Gunnar Malm, Prof.
Anders Halln, and Docent Henry Radamson for valuable help and discussions.
I have been very lucky with office roomates over the years. Dr. Julius Hllstedt for all
his help when I was starting out and continued friendship. Ana Lopez for her friendship and
Maziar Amir Manouchehry Naiini for being a good friend and for all the insightful
discussions.
Many people have helped me in the cleanroom, including: Christian Ridder, Cecilia
Aronsson, Zhibin Zhang, Dr. Yong-Bin Wang, and Timo Sderqvist.
Everyone else at the group I want to thank for their discussions and help: Benedetto
Buono, Dr. Jiantong Li, Dr. Reza Ghandi, Dr. Mohammadreza Kolahdouz Esfahani, Dr.
Christoph Henkel, Dr. Max Lemme, Gunilla Gabrielsson, Dr. Martin Domeij, Muhammad
Usman, Dr. Yohannes, Assefaw-Redda, Eugenio Dentoni Litta, Sam Vasiri, Arash Salemi,
Oscar Gustafsson, Mattias Hammar, Jesper Berggren, and Luigia Lanni.
Part of this work was conducted in collaboration with the University of Udine. I would
especially like to thank Prof. Pierpaolo Palestri for all his help and patience. I also want to
thank Prof. Luca Selmi, Prof. David Esseni, and Prof. Francesco Driussi for their
collaboration and helpful advice, as well as all the students at the time I was there: Davide
Ponton, Paolo Toniutti, Francesco Conzatti, Alban Zaka, Nicola Serra, Marco De Michielis,
Jan-Laurens van der Steen.
Finally, I want to thank my family and my fiance Emily for their continuous support
and encouragement.

Valur Gumundsson, Stockholm, November 2011
x

List of symbols and acronyms
Two dimensional Richardson constant

A
*
Effective Richardson constant
C
d
Depletion capacitance [F/cm
2
]
C
ox
Gate oxide capacitance [F/cm
2
]
Conduction band energy
Valence band energy
Fermi level
Metal Fermi level
Semiconductor Fermi level
Band gap
Electric field
f Frequency
I
ball
Ballistic on current
I
d
Drain current
I
off
Off current (V
g
=0, V
d
=V
DD
)
I
on
On current (V
g
= V
DD
, V
d
= V
DD
)
J Current density
Boltzmann constant
Length of the contact region
Effective channel length
Extension length
Underlap between source metal and gate

L Gate length
L
ext
Length of the doped extension
l Contact length
Valley degeneracy for Richardson constant
Effective mass for Richardson constant

m Body coefficient
m
*
Effective mass
m
0
Electron mass
Doping concentration
Effective density of states for conduction band
Donor doping concentration

N
ext
Doping concentration of the extension
Dynamic power dissipation
Static power dissipation
Series source/drain resistance
Channel resistance [/sq.]
Extension resistance
Contact resistance in a MOSFET
Spreading resistance
MOSFET total resistance [-m]

xi

R
c
Contact resistance
Pinning factor using electronegativity
Pinning factor using work function
Thickness of Ni
Thickness of NiPt
Silicon layer thickness
Gate insulator oxide thickness

Temperature
<v
+
> Mean velocity of carriers going from source to drain
<v
-
> Mean velocity of carriers going from drain to source
V
d
Drain bias
V
DD
Circuit operation voltage
V
fb
Flat band voltage
V
g
Gate bias
v
sat
Saturation velocity
V
t
Threshold voltage
Depletion width
Effective depletion width
Depletion width of the Schottky contact when used in SB-MOSFETs
Electronegativity
Electron affinity
Junction depth
Decrease in effective barrier height due to tunneling
Decrease in effective barrier height due to image force lowering
Optical dielectric constant
0
Permittivity of vacuum
Si Permittivity of Silicon
Geometric factor for source field
Characteristic length
Channel mobility
c
Contact resistivity
s
Bulk resistivity
Switching time
Metal work-function
Schottky barrier height
Schottky barrier height to conduction band
Schottky barrier height to valence band
Charge neutrality level
Effective Schottky barrier height
Barrier predicted by Schottky-Mott theory
Built in voltage
Long channel surface potential

BOX Buried oxide
B-P Bond-polarization
BTE Boltzmann Transport Equation
CBKR Cross bridge Kelvin resistor
CER Contact end resistor
xii

CESL Contact etch stop layer
CMOS Complementary metaloxidesemiconductor
CV Capacitance voltage
DG Double gate
DIBL Drain induced barrier lowering
DS Dopant segregation
EOT Equivalent oxide thickness
FD Fully depleted
GAA Gate all around
I/I Ion implant
IFBL Image force barrier lowering
ITM Implantation to metal
ITRS International Technology Roadmap for Semiconductors
IV Current Voltage
IVT Current Voltage Temperature
LEAP Local electron atom probe
LER Line edge roughness
LOCOS Local oxidation of silicon
LWR Line width roughness
MC Monte Carlo
MIGS Metal induced gap states
MOSFET Metal-oxide-semiconductor field-effect transistor
M-S Metal-Semiconductor
MSMC Multi-subband Monte Carlo
NEGF Non-equilibrium Green function
NW Nanowire
PE Photoelectric emission
S/D Source/drain
SADS Silicide as diffusion source
SALICIDE Self-aligned silicide
SB Schottky barrier
SBH Schottky barrier height
SCE Short channel effect
SIDS Silicidation induced dopant segregation
SIMS Secondary ion mass spectrometry
SOI Silicon on insulator
STL Sidewall transfer lithography
TE Thermionic emission
TED Transient enhanced diffusion
TLTR Transmission line tap resistor
TM Transfer matrix
UTB Ultra-thin-body
WKB WentzelKramersBrillouin approximation
1

1. Introduction
Over the past decades, the improvement in performance of complementary metaloxide
semiconductor (CMOS) technology has been extremely rapid and it is the backbone of the
incredible advancements in digital technology. One of the main driving forces behind the
improvement is downscaling of the metal-oxide-semiconductor field-effect transistor
(MOSFET). Over the past 50 years, the number of transistors has doubled every two years.
This trend, first observed by Gordon Moore [1], is very interesting; especially that it has
been possible to continue this exponential growth for such a long time. The rate of growth
is related to the economics of scaling. Though scaling makes fabrication of each transistor
cheaper, development of a new technology is, nonetheless, expensive. The rate of
development does not have to be limited by Moores law, but since the law has held for
decades, it appears it is difficult for the semiconductor industry to improve faster while
remaining profitable.
Generally, by reducing the device dimensions, the density of MOSFETs on the chip is
increased, power consumption per device is decreased, and the switching speed can be
increased. However, in recent years the scaling has become increasingly challenging, as
both limits to existing fabrication technologies and fundamental physical limits, have
required many changes in the way the devices are fabricated. As the gate length (L) is
scaled, the source/drain (S/D) junction depth (x
j
), depletion width (W
d
), and oxide thickness
(t
ox
) have to be scaled as well, so that the gate maintains electrostatic control over the
device. Reduction of t
ox
is limited by leakage tunneling current, which has caused the
industry to change to high-k oxides [2]. Reducing W
d
requires higher bulk doping which
reduces mobility. In order to circumvent these scaling limitations, fully depleted (FD)
structures with a thin Si body, such as ultra-thin-body (UTB), and multiple-gate (double-
gate, tri-gate, and gate all around) MOSFETs have, in recent years, been the subject of
intensive research [3-5]. In these FD structures, the junction depth is equal to the Si
thickness (t
Si
) and as the dimensions are scaled down the doping concentration in the
source/drain region has to be increased to maintain low parasitic source/drain resistance
(R
SD
) [3]. However, the increase in doping concentration is limited by the dopant solid
Fabrication, characterization, and modeling of metallic source/drain MOSFETs
2

solubility and maintaining low R
SD
is extremely challenging in these devices [3]. One
solution to decrease the R
SD
is the use of metallic S/D instead of doped-S/D [6], [7]. A
Schottky barrier (SB) junction is formed at the start and end of the channel and the device is
therefore commonly called a SB-MOSFET. For the SB-MOSFET a critical challenge is
obtaining a low contact resistance at the SB junction.
This thesis aims to improve the performance and understanding of SB-MOSFET
technology. The experimental part has focused on achieving low temperature formation of
SB-S/D with low SB height (SBH) (or contact resistivity) by fabrication of both SB-
MOSFETs and SB diodes. In order to improve understanding of SB-MOSFETs, simulation
work has been conducted both for comparison to measured data and for analyzing behavior
of SB-S/D if implemented in future generations of CMOS technology.
The structure of the thesis is as follows: In Chapter 2, some aspects of Metal-
Semiconductor (M-S) contact theory, relevant for this work, are reviewed. The current
transport, Schottky barrier formation, and ohmic contacts are discussed. The results in
Paper I are referred to in connection with the discussion on ohmic contacts.
Fundamentals of MOSFETs are discussed in Chapter 3, with emphasis on device scaling. In
relation to scaling, fully depleted device architectures are introduced. The SB-MOSFET is
introduced with discussion on SB-S/D with shallow doped extensions.
Metal silicides are a key ingredient, for realizing SB-MOSFETs, due to the possibility of
fabricating self-aligned silicide (SALICIDE) in the S/D regions. The choice of silicides for
integration in SB-MOSFETs, is discussed in Chapter 4. Low SBH (or low contact
resistance) is needed to be useful in CMOS technology. The modification of SBH by dopant
segregation (DS) is shown by experimental data and possible mechanisms of segregation
are discussed. A part of the DS results in this Chapter are extended in Paper II.
The fabrication, characterization and analysis of SB-MOSFETs are the subject of Chapter 5.
First, the development of a sidewall transfer lithography (STL) process is discussed,
referring also to sidewall roughness analysis shown in Paper III. With the STL process,
lines down to 15 nm were achieved, and the STL process was subsequently used to
fabricate UTB and tri-gate SB-MOSFETs, which were published in Paper IV. The
extraction of R
SD
is discussed and the analyzed by simulations of the UTB devices, which
1. Introduction
3

are the subject of Paper V.
The modeling of deca-nanometer SB-MOSFETs requires simulations that take the non-
equilibrium transport in these devices into account. In Chapter 6, the implementation of SB
contacts in a multi-subband Monte Carlo (MSMC) simulation tool is demonstrated. The
contact model was used in Papers VI and VII to analyze the behavior of SB-MOSFETs
down to 17 nm gate length.
In Chapter 7, the work is concluded with a summary and future outlook.
5

2. Metal-Semiconductor contacts
In the next Section the current transport across the M-S interface is described. The primary
parameter for M-S contacts is the Schottky barrier height (SBH), and in Section 2.2 the two
main theories for Schottky barrier formation are reviewed. In Section 2.3 ohmic contacts
are discussed in order to introduce the work done in Paper I. For further information on M-
S contacts, the reader is referred to some of the excellent references available in the
literature [8-10].
2.1 Current transport

Fig. 2.1. Energy band diagram of (a) forward biased and (b) reverse biased Schottky junction on n-
type substrate (V
F
= -V
R
).
The band diagram of a Schottky junction is shown in Fig. 2.1. The main contributors to
current transport across a Schottky barrier are thermionic emission (TE) of charge carriers
above, and tunneling through the barrier. The total current can be described as two fluxes of
charge carriers (Fig. 2.3(b)), one coming from the metal and the other from the
semiconductor. If we consider the current flux as a function of energy (), then the portion
of charge carriers within the current flux with larger than the barrier height are
thermionically emitted above the barrier, and carriers with lower energy have a probability
of tunneling through the barrier. The total current density (J) through the barrier is
6

given by [11], [12]:

(2.1)
where

(2.2)
is the 2D carrier concentration and represents the magnitude of the current flux as a
function of energy (see Fig. 2.3). Here
is the effective Richardson mass, and

the degeneracy [13].
If the doping concentration is low, it is sometimes sufficient to consider only thermionic
emission above the barrier. We define
and set = 1 if
and = 0
otherwise. Eq. 2.1 reduces to:

(2.3)

(2.4)
where A
*
is the effective Richardson constant [13]. According to Eq. 2.4 the TE current
does not depend on the doping concentration in the semiconductor. However, there are two
effects that are dependent on the doping concentration: image force barrier lowering (IFBL)
and tunneling. When an electron in the semiconductor is close to the metal its image force
attracts it towards the metal, which causes an energy barrier reduction:

(2.5)
Thus the peak of the barrier is reduced (Fig. 2.2) and is dependent on the electric field at the
contact, the larger the electric field at the contact, the larger the barrier lowering by image
force.
7

Fig. 2.2. Band diagram of n-type Schottky contact showing IFBL.
For semiconductors with moderate or large impurity concentration, the tunneling through
the barrier must be taken into account. Using the WentzelKramersBrillouin (WKB)
approximation the tunneling probability is given by:

(2.6)
Where
and
are the classical turning points (tunneling path) at energy level E, and k(x)
is the wavenumber:

(2.7)
To obtain the conduction (or valence) band profile must be known. This model was
implemented in a 1-D Schottky diode simulator that solves self consistently the Poisson and
Fermi-Dirac equations. The simulator was used in papers VI and VII to compare the WKB
model to a simpler effective potential model. This comparison will be discussed in more
detail in Chapter 6.
In Fig. 2.3(a) the conduction band profile adjusted by IFBL (
+ IFBL) is shown for a SB

diode with
bn
= 0.4 eV and N
D
= 510
18
cm
-3
. Using this energy profile the current flux can
be obtained using Eq. 2.1. Fig. 2.3(b) shows the carrier flux across the barrier, from metal
to semiconductor and vice versa, as a function of energy. Integrating the flux over energy
gives the current density. Since the doping concentration is large, the IFBL reduces the peak
of the barrier by 0.1 eV. Also, the depletion layer is only 10 nm and current is primarily due
to tunneling.
8

Fig. 2.3. A SB diode with
bn
= 0.4 eV, N
D
= 510
18
cm
-3
, and V
R
= 50 meV. (a) Conduction band
profile with IFBL applied. (b) Transmitted carrier fluxes as a function of energy. The metal to
semiconductor flux corresponds to the left side of Eq. 2.1 and the semiconductor to metal one to the
right side.
2.2 Modeling of Schottky barrier height
Modeling of the experimentally observed SBH of different metals and semiconductors has
been the subject of extensive research [10]. A first order model for the n-type barrier height
is given by the Schottky-Mott relationship [14]:
(2.8)
where
is the metal work-function and
is the electron affinity of the semiconductor.

However, experimentally it was found that as the
changes the barrier height changes

less than Eq. 2.8 indicates. It was observed that a linear relation was found between the
observed barrier heights and the metal electronegativity (
), that which is defined as the
. Using that
, where A is a conversion factor [15], the quantity
is defined. A reasonable agreement to experimental results is

found by the simple relationship:
(2.9)
where
is the charge neutrality level of the semiconductor. If
=1, the relation given

by Eq. 2.8 holds, and if
= 0, then
. In reality
is often small [16] and in

those cases the
changes slowly as
is changed, this effect is called Fermi-level

9

pinning. For Si,
is 0.32 eV from the valence band [17] and the factor
0.03-0.035
[15-17]. Therefore the
of Si is pinned strongly and it is easier to obtain small p-type

barriers than n-type. Experimentally the smallest barrier heights of metal silicides to Si are
~0.2 eV to p-type (IrSi, PtSi) and ~0.3 eV to n-type (ErSi, YbSi
2-x
).
Metal induced gap states (MIGS) theory is likely the most common way to explain the
Fermi level pinning effect. First pointed out by Heine [18], in essence the theory considers
that when a metal is put into contact with a semiconductor, the metal wave functions that
have energy levels within the semiconductor band gap penetrate some distance into the
semiconductor. The charge associated with the wave functions gives rise to states within the
band gap. The width of the dipole that they form, can be approximated as the decay length
of the wave functions inside the semiconductor.
Based on the MIGS model, an equation for the pinning parameter (
) has been found to be

in reasonable agreement with experimental data by correlating the semiconductor optical
dielectric constant
to
[19]:

(2.9)
where C = 0.1 has been found by fitting to experimental data [19]. Therefore, for higher

the slope parameter
is decreased, and the Fermi-level pinning increased. Also, since E

g

tends to be inversely proportional to
, the Fermi level pinning decreases as E

g
increases.
The MIGS theory has also been used to obtain predictive estimations of band alignment of
metal-dielectric interfaces [20], which is relevant for predicting the threshold voltage for
high-k metal-gate stacks in CMOS technology.
The MIGS theory depends only on bulk parameters. However, experiments show that
epitaxially grown NiSi
2
has a barrier shift of 0.14 eV depending on its interface properties
[21]. This indicates that the chemical bonding at the interface plays a role in the SB
formation, something that is not included in MIGS theory. These observations have
motivated the development of the bond-polarization (B-P) model [15], [22], which looks at
the problem from a molecular point of view. The charge transfer, caused by chemical
bonding, between the first monolayers of the metal and semiconductor is calculated. In the
10

B-P model the pinning parameter is given by:

(2.10)
where
is the number of interfacial bonds,
is the bond distance, and is the sum of

the hopping interactions [15].
Both B-P and MIGS theories are similar in many aspects, the B-P model is based on the
charge transfer when two molecules come into contact, whereas the MIGS is based on the
charge transfer by gap states in the semiconductor [15], [22]. Neither method can predict
exactly the SBH of a certain M-S system, but the B-P model is especially interesting since
it suggests the SBH can be modified by changing the chemical bonding at the interface.
A comparison between the B-P and MIGS models is made in [15], where a set of
,
and
for 16 semiconductors is used to find a fit of the unknown parameters in Eq. 2.9 and
Eq. 2.10. Since both models use assumptions to arrive at their simple equations, it is
interesting to see which model predicts pinning parameters better. For MIGS Eq. 2.9 is
plotted as
and C is fitted to the data. For B-P, Eq. 2.10 is plotted

as
, where D and F are fitted to the data. Using the

fitted parameters, Fig. 2.4 shows the prediction of
from model vs. the measured
. The
figure shows both models follow the correct trend. However, the MIGS model has
somewhat more accurate predictions than B-P, especially when
is low.
By inserting a thin insulator, such as SiO
2
or Si
3
N
4
, between the metal and semiconductor,
the Fermi-level pinning can be decreased, since the Fermi-level pinning is smaller for large
bandgap materials. Since an increased
is obtained [20],[23], a small SBH can be

achieved by choosing the correct metal. However, the insulator creates a tunneling barrier,
which must be kept extremely thin. Also, the insulator must be chosen so that the band
offset between Si and insulator is small [24]. The physical mechanism for insulator
modulation of SBH has been debated by Robertson and Lin [25]. They argue that the
observed changes in barrier heights for thin Al
2
O
3
insulator on Ge [26] are due to a dipole
between the insulator and Ge and not Fermi-level depinning.
11

Fig. 2.4 Measured and predicted
for B-P and MIGS models. Both models show the correct trend
but are fairly limited in their ability to predict pinning factors.The data points are based on tabulated
, and
values of 16 semiconductors from [15].

2.3 Ohmic contacts
When a M-S contact has low resistance compared to the resistance of the device, the
potential drop across the contact is small and the I-V behavior is approximately linear
(ohmic). This ohmic condition usually only becomes relevant when the semiconductor
layer of a M-S contact is highly doped (approximately >110
19
cm
-3
). In this case, tunneling
becomes the dominating contributor to current, and the contact resistance becomes low. The
depletion layer is only a few nm in these contacts. Contact resistivity (
c
, unit [cm
2
]) is
the figure-of-merit for ohmic contacts [9] :

(2.11)
The contact resistivity is affected by barrier height
and doping concentration, when

tunneling is the primary current transport mechanism we have [9]:
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
S
|
measured
S
|

m
o
d
e
l

Ge BP model S
|
=33
Ge
Si
Si
GaAs
CdTe
CdTe
GaTe
GaTe
CdSe
CdSe
GaSe
GaSe
GaP
GaP
CdS
GaS
GaS
ZnSe
ZnSe
SnO2
SnO2
SrTiO3
SrTiO3
ZnO
ZnS
ZnS
SiO2
SiO2
B-P
MIGS
S
|
model = S
|
measured
12

(2.12)
where N is the doping concentration. Since
on Si is relatively large, a large doping

concentration is needed for low
. The contact resistivity is very sensitive to changes in N,

for example, when N is increased by a factor of 10,
is decreased by a factor of 10
3
to 10
4

(assuming a mid bandgap barrier) [27],[28].
For CMOS technology it is important to achieve low contact resistivity, and the ITRS
estimates
c
should be below 510
-9
cm
2
by 2021 [3]. The contact resistivity of <100> n-
Si is shown in Fig. 2.5. Both results for transfer matrix (TM) (see Section 6.3.1) and WKB
tunneling models are shown. The values were obtained using a diode simulator that is
described in Chapter 6. The
c
is lower than the standard literature references [9], [28], but
the difference arises because in Ref. [28] IFBL is not taken into account which gives larger
c
than is obtained here. Another difference is that although the calculations are based on
WKB in Ref. [28] they use analytical approximations to do the calculations. In [29] the
WKB approach without IFBL is used to obtain tunneling transport. Separate simulation
conducted here without IFBL was in good agreement with the results shown therein. In the
present approach the barrier with added IFBL (see Fig. 2.3), is used to calculate the
tunneling probability and is considered more accurate than existing literature data.
2.3.1 Contact resistivity measurements
Measurement of contact resistivity is challenging since the contact resistance is often very
low compared to the sheet resistance of the Si, for example if
c
= 110
-8
cm
2
a contact
that has area A = 1 m
2
will have only approximately 1 resistance (note that R
c
=
c
/A
only holds for in some cases, see [30] and Paper I for details). The sheet resistance of
highly doped Si is generally on the order of 10-100 /sq. Since the contact resistance is
smaller than the sheet resistance of Si it is challenging to design a test structure so that only
the contact resistance is measured and not parasitic resistance of the Si layer underneath
and close to the contact. The most common structures for extracting contact resistivity are
the transmission line tap resistor (TLTR) (Fig. 2.6(a)) [30], contact end resistor (CER) (Fig.
2.6(b)) [31], and cross-bridge Kelvin resistor (CBKR) (Fig. 2.6(c)) [32].

13

Fig 2.5. Contact resistivity calculated using WKB and transfer-matrix (TM) [12] tunneling models.
Both approaches have the same trend but exhibit increasingly large differences as N
D
is increased.
Following the discussion in [33], Fig. 2.7 shows the potential along a highly doped Si layer
with a metal contact, where a current is passed between the metal contact and a contact on
the left side (not shown). In essence the TLTR measures the potential at the front (the side
the current is coming from) of the contact, the CER the potential at the end of the contact
and the CBKR the average potential along the side of the contact. Each technique has its
advantages and issues, the front contact potential measurement by TLTR (see Fig. 2.6(d))
has to be extracted by measuring two or more pairs of contacts with varying length between
the contacts, so that the potential drop in the semiconductor can be extracted. It is therefore
an indirect method which can increase the measurement error. The CER can measure the
contact end potential directly, but since the potential decreases exponentially along the
contact, the end potential is very small. As Fig. 2.7 shows, when 2D parasitics are taken
into account, the potential is drastically changed from the 1D case. That also means the
CER will be extremely sensitive to process variations. In [33] it is argued that the CBKR is
10
18
10
19
10
20
10
21
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
N
D
(cm
-3
)
C

o
n

<
1
0
0
>

n
-
S
i

(
O
-
c
m
2
)

TM
WKB
0.3eV
0.5eV
0.4eV
SBH=0.2 eV
SBH=1 eV
14

Fig. 2.6. Schematics of contact measurement structures (a) TLTR, (b) CER, (c) CBKR, (d) shows
where the potential is being measured for each of the test structures. Note that for the TLTR structure
at least two devices with different d are needed for the extraction.
the best compromise between CER and TLTR. Like the CER the potential can be obtained
directly with the CBKR, but since the potential is averaged along the contact, it is larger,
and less sensitive to 2D effects.
The contact resistance changes in proportion to 1/l
2
, where l is the contact side length. In
[34] small contacts (l 20 nm) were used on heavily doped Si. The spreading resistance in
the Si layer is 1/l, and therefore if the contact is small enough, the contact resistance
dominates, and the resistivity can be extracted directly using:
c
= R
c
l
2
. In this manner,
15

complex elimination of systematic error is not necessary. The main issues with this
approach are, that the extremely small contact size requires advanced lithography, and
accurate estimation of the contact area requires TEM analysis.
Significant amount of work has been done on eliminating systematic error in the CBKR
[35-40]. In order to eliminate the systematic error, it is necessary to know the contact area,
the device layout and sheet resistance. However, it is difficult to evaluate the sensitivity of
the extraction to random error in any of the input variables. Therefore, in Paper I the error
propagation from random measurement error in the CBKR on the contact resistivity is
studied. The results show that for literature data where
c
< 10
-8
cm
2
values were reported,
great care should be taken, since the error in input values is multiplied by up to ~40x when
extracting
c
.

Fig. 2.7. Potential along a cross-section of a highly doped semiconductor layer with an M-S contact.
Current is forced from the left side and through the contact. Large differences are observed between
1D model and 2D one.
17

3. MOSFETs
The MOSFET (Fig. 3.1) fundamentals are described in detail in several reference books
[41], [42]. The description here will focus on the relevant aspects for this work, which
involves scaling, and the minimization of parasitic source/drain resistance. In this Chapter
the MOSFET fundamentals and main scaling issues of MOSFETs are considered in the next
Section. In order to continue scaling, fully depleted (FD) MOSFETs are discussed in
Section 3.2. Parasitic source/drain resistance is a major issue in FD MOSFETs, and SB-
MOSFETs are considered as a solution to this issue in Section 3.3.

Fig. 3.1. Short channel n-type MOSFET, with applied drain bias, showing how the depletion regions
in the source and drain affect the depletion region under the gate.
3.1 MOSFET fundamentals and scaling
For the purposes of CMOS technology the transistor should act a switch, with large current
in the on state (I
on
) and low current in the off state (I
off
). Considering an nMOS device with
the gate bias (V
g
) equal to the circuit operation bias (V
DD
) the output curve (I
d
-V
d
) is shown
in Fig. 3.2(a). The curve has two parts, the linear and saturation regions. The characteristics
in the linear region are given by (V
s
= 0):

18

(3.1)
where
is the oxide capacitance per area (unit [Fcm

-2
]), and m=1+C
d
/C
ox
(C
d
=
Si
/W
d
) is
the body-effect coefficient. At very low V
d
the device operates as a resistor, the gate bias
attracts electrons to the interface, forming a conductive inversion layer at the interface. The
factor
arises since the inversion layer at the drain is smaller than at the source,
since V
g
-V
s
> V
g
-V
d
. When V
d
= (V
g
-V
t
)/m the device reaches saturation and the drain
current is given by:

(3.2)
The current equations assume low field mobility, that is when the electric field in the
transport direction is low. For devices with gate length less than a few hundred nm, the field
along the channel () is large, and the low field mobility approximation is no longer valid.
At a certain lateral field
the carrier velocity saturates and the drain current is given by

[42]:

(3.3)
Therefore, at short L the drain becomes less sensitive to decrease in L. Ultimately, in
extremely scaled transistors, where the gate length is smaller than the mean free path
between scattering events, the current is limited by its ballistic current:
(3.4)
where <v
+
> is the mean velocity of carriers going from source to drain. Monte Carlo
simulations show scattering is relevant even in very small transistors [43], but the ballistic
current is nevertheless a useful upper limit to current transport in nanoscale devices.
If the drain of the MOSFET has applied bias V
DD
and the gate bias is increased from zero to
V
DD
(Fig. 3.2(b)) the MOSFET first passes through the subthreshold region and at the
threshold voltage V
t
it passes to the saturation region. The subthreshold current may be
written as:
3. MOSFETs
19

(3.5)
where I
0
is the current at V
g
=V
t
.
Optimum MOSFET performance requires balance between minimizing I
off
and maximizing
I
on
. A decrease in V
t
causes logarithmic increase in I
off
and linear increase in I
on
. Device
optimization may also decrease m, thus achieving a steeper subthreshold slope. Also, much
work has been done to increase the channel mobility [44]. A large performance
enhancement is achieved by device scaling, which is discussed next.

Fig. 3.2. (a)
(b)
curves for a n-type MOSFET.

Before discussing scaling, it is useful to define basic performance metrics for CMOS
technology, power, speed, and density. For switching on a transistor the energy it takes to
charge the gate is E=0.5CV
2
DD
, where C is total capacitance of the device, including
parasitic capacitance. At a certain clock frequency (f) the dynamic power consumption is
P
d
=0.5CV
2
f. The static power consumption is P
s
=V
DD
I
off
. The time the switching takes is
=CV/I
on
, and the density is given by d=1/A=1/(W(L+L
cont
)), where L
cont
is the length of the
contact region.
Reduction in gate length, both reduces the gate capacitance and increases the current. Also,
reduction in V
DD
both decreases power consumption and delay time. At the same time W
can be scaled and the density is increased. However, several issues arise when the device is
scaled. One of the most important is the short-channel effect (SCE) which causes increasing
difficulty in turning off the device.
20

As L is decreased, the depletion regions of the source and drain junctions cause increasing
band bending within the channel (Fig. 3.3). Defining
as the channel surface potential at

threshold voltage for long channel device, the barrier is lowered by the source and drain
fields. An approximate surface potential within the channel, in subthreshold region, is given
by [45], [46]:

(3.6)
where the characteristic length is approximately the length the source and drain electric
fields penetrate the channel [47], [46]:

(3.7)
where W
eff
is the effective depletion width. In long channel case W
eff
=W
d
, but considering
the S/D region affects the depletion width in a short channel MOSFET, the W
eff
is larger
than W
d
in short channel devices.

Fig. 3.3 Energy band calculated using Eq. 3.6, biased close to threshold voltage, for a short and long
channel MOSFET. Field penetration from source and drain causes V
t
lowering, which is further
enhanced as drain bias is increased.
3. MOSFETs
21

Although Eq. 3.6 is not exact it illustrates some essential characteristics of scaling. If L
the device will exhibit long channel behavior. When L is decreased, eventually the
threshold voltage becomes dependent on L since the source and drain will decrease the
barrier. For scaling one needs approximately L/ = 5-10 depending on the application [46].
When L is smaller than 5-10 a V
t
roll-off effect is observed which follows the relationship
[46]:

(3.8)
Some V
t
roll-off may be acceptable, but there is a serious variability issue when L is small,
since a small change in the gate length will cause large changes in threshold voltage and
therefore
.
Eq. 3.8 assumes low V
d
, in the short channel case as V
d
is increased the drain field further
pulls down the barrier. This drain induced barrier lowering (DIBL) can be included in the
threshold voltage roll off by [42], [46]:

(3.9)
where
is the built in voltage between the gate and S/D regions at the threshold voltage.
To scale L, must be scaled also, thus, W
eff
and t
ox
/
ox
should be decreased. Scaling of t
ox

has been the subject of extensive research. In short, the t
ox
scaling is fundamentally limited
by tunneling leakage currents through the oxide. This has caused the industry to increase
ox

by implementation of high-k oxides and metal gates [2], [48]. The W
eff
scaling is performed
by decreasing the depletion width W
d
and by introducing shallower junction depths x
j
.
However, decreasing W
d
requires higher bulk doping, causing reduced mobility, and
increasing, hot electron degradation and avalanche breakdown [49]. To bypass this problem,
so called halo implants have been used to implant a higher concentration of dopants close to
the source/drain regions. The effect is that the source/drain fields are screened by the high
implant dose. As x
j
is decreased, the doping concentration in the S/D regions has to be
increased, in order to keep the parasitic source/drain resistance within limits. However, as
scaling continues the concentration reaches a solid solubility limit which sets a minimum to
the Si resistivity. Alternate doping techniques such as plasma doping [50], gas phase doping
[51], and cluster implantation [52] combined with ultra-rapid annealing methods like pulsed
22

laser annealing [53], may allow further reduction of the junction depth.
Despite these techniques to continue scaling, the scaling of gate length in bulk MOSFETS
is reaching fundamental limitations. The increase of mobility by strain engineering has
contributed to further performance enhancement, since the increased ON currents have
allowed downscaling of device width further decreasing the device footprint [44]. These
issues with scaling have led to the introduction of fully depleted (FD) structures [54], which
will be discussed next.
3.2 Fully depleted MOSFETs
Fully depleted (FD) MOSFETs have been studied extensively in recent years to enable
continued scaling. For this purpose the MOSFET is usually fabricated on a thin Silicon-On-
Insulator (SOI) film with low doping so that the whole film is depleted (Fig. 3.4(b)).
Several versions of these devices have been proposed depending on how many sides a gate
is placed at namely: ultra-thin-body (UTB) (Fig. 3.4(b)), double-gate (DG), tri-gate (Fig.
3.4(c)), and gate-all-around [4]. The characteristic length of these devices is decreased
with an increasing number of gates. A device with n gates has approximately
n
=/n [4].
For the UTB device, smaller V
t
roll-off effect has been demonstrated, when compared to
bulk technology [55]. However, the drain field still has a strong capacitive coupling through
the buried oxide (BOX) to the channel, and the scaling length () theory is not correct [56].
Simulation study has shown the ratio between t
Si
and L should be L/t
Si
> 5 to keep the SCE
within limits [56]. However, when t
Si
< 3 nm the electron Si mobility is severely reduced
[57], due to increased surface optical phonon scattering and t
Si
thickness fluctuations [58].
The UTB technology may be used for near term technology generations, but eventually t
Si
<
3 nm would be needed to sustain scaling. A possible improvement to the UTB structure is
the use of a thin BOX and a bottom grounded plane. That way the drain field terminates in
the bottom ground plane and SCE is improved [59]. The use of thin body has been
criticized since it leads to larger transverse fields and therefore reduced mobility [60].
A significant improvement to the UTB device is the double-gate MOSFET. This is because
the bottom gate screens the drain field, which allows considerably relaxed t
Si
requirements.
A first order approximation from simulation results have given L > 2t
Si
is required to
maintain reasonable DIBL and SS [61]. Using the planar fabrication process, there is
3. MOSFETs
23

significant difficulties in placing the second gate underneath the channel. Instead, the
FinFET has been proposed, where a thin vertical body is etched on a SOI substrate, and the
etched sidewalls are used as the channel [5] (Fig. 3.4(c)).
Further extensions of the FinFET approach are tri-gate MOSFETs (Fig. 3.4(c), which adds a
gate on top of the fin (L > 1.5t
Si
[61]). Ultimately, scaling may lead to a nanowire gate-all-
around (GAA) device which will allow L > t
Si
[61]. The GAA device is difficult to fabricate,
since at some point in the process the Si nanowire has to be suspended to place the gate
under the transistor. A practical compromise is the FET in which the oxide under the gate
is etched partially, so that the gate covers most of the Si nanowire [62].

Fig. 3.4. MOSFET schematics: (a) bulk, (b) ultra-thin-body, (c) tri-gate
An important concern for the implementation of thin body FD structures is the control of
parasitic series source/drain resistance R
SD
. Just like scaling of x
j
in the bulk MOSFET, the
scaling of t
Si
requires an increase in S/D doping concentration. In Si-nanowires (Si-NW)
deactivation of dopants can also be a serious problem, which would further increase R
SD
. In
[63] a 50% deactivation was reported for a nanowires with a 15 nm diameter. The
deactivation was explained by an increase in ionization energy of dopants due to
confinement in the Si-NW [64]. Also, self aligned silicidation is challenging for thin body
devices. To solve these issues, the elevated S/D approach is commonly used, where
selective epitaxial growth of highly doped Si in the S/D region [65] is used to increase the
thickness of the S/D regions [66]. The resistance components are shown in Fig. 3.5, where
the R
SD
is composed of the extension from the epi to the channel (R
ext
), the spreading
24

resistance under the contact (R
sp
), and the contact resistance (R
sb
). The thickness of the
sidewall spacer needs to be optimized to obtain a balance between minimizing R
ext
and the
fringing capacitance [67]. The focus of this work has been on the reduction of R
SD
by an
alternative approach where the metal is placed at the channel edges, forming a Schottky
barrier MOSFET. This structure is introduced in the next Section.

Fig. 3.5. Parasitic resistance components of a FD MOSFET with raised S/D.
3.3 Schottky barrier MOSFETs

Fig. 3.6. (a) Schematic of the Schottky barrier MOSFET and band diagram for nMOS device in (b) off
state (
) and (c) on state (
).
3. MOSFETs
25

A schematic and band diagram of the SB-MOSFET is shown in Fig. 3.6. The device shown
is a UTB MOSFET with a thin BOX and grounded bottom plane. The thin BOX would
decrease short channel effects but is shown just to be consistent with the analytical model
discussed in the next Section. Devices with doped extensions will be discussed in Section
3.3.2.
3.3.1 Fundamentals of SB-MOSFETs
The current transport across a Schottky contact has been discussed in the last Chapter. Fig.
3.6 shows n-type SB-MOSFET in the off (Fig. 3.6(b)) and on (Fig. 3.6(c)) state. In the ON
regime of the SB-MOSFET (V
d
= V
g
= V
dd
) the reverse biased Schottky junction at the
source end is the largest contributor to the parasitic R
SD
in the SB-MOSFET. In Schottky
diodes the tunneling through the barrier is affected by the doping concentration and bias
across the diode. However, in the SB-MOSFET the electric field from the gate controls the
potential profile in the channel, and therefore the tunneling.
In order to analyze the basic behavior of SB-MOSFET in the ON regime a modified version
of a simple model proposed in [68] will be used that has the essential elements needed for
the discussion, but is not accurate enough for a quantitative study. The current transport
through a reverse biased Schottky contact at the source is:

(3.10)
where
is given by [69]:

(3.11)

(3.12)
where
is the 2D effective Richardson constant. the 2D is used here current transport is

direct between the metal and the 2D channel. In this simple model only one subband is
accounted for. In Eq. 3.10,
is an effective barrier height that takes into account barrier

lowering by tunneling (
) and image force barrier lowering (
):
26

(3.13)

(3.14)
(3.15)
The equation
uses the WKB approximation and assumes a triangular barrier. Therefore

the results obtained by this simple model are only approximate. Using this simple model,
the transport across a Schottky barrier can be obtained if the SBH and the electric field at
the interface are known. Also Eq. 3.10 assumes non-degenerate transport, however, in
nanoscale transistors, the transport is degenerate (see also Paper VII).
To estimate the electric field at the source, Eq. 3.6 is used as a starting point. Taking the
derivative, the electric field close to the source is:
. The
potential between source and channel is estimated by setting
, where
is
the gate bias at which there is flatband condition at the source. Next, taking the field at the
Schottky contact (x = 0) we have:

(3.16)
where has been added as a geometric factor that is affected by the underlap/overlap
between the gate and the metal S/D contact, and the variation in along the height of the
Schottky contact.
If the resistance of the SB contact is much larger than that of the intrinsic MOSFET, the
current characteristics are dominated by the contact and the current of the SB-MOSFET is
given by
. According to the ITRS the parasitic series resistance should not degrade
I
on
by more than 33% [3]. Therefore, for the SB-MOSFET technology to be viable, the
contact resistance must be decreased sufficiently to fulfill that criteria.
The current of an ideal ballistic MOSFET is given by Eq. 3.4 and is on the order of several
mA/m. In order to analyze if SB-MOSFET technology is viable it is possible to analyze
which
b
and are needed so that current drive is not limited by the Schottky contact or I
sb
>
3. MOSFETs
27

I
ball
.
Fig. 3.7 shows I
sb
-V
g
for the source Schottky contact of a SB-MOSFET with t
ox
= 1 nm, t
Si
=
8 nm,
ox
=3.9, and = 1. When V
g
< V
fb
an ideal 60 mV/dec slope is assumed. In a SB-
MOSFET where current is dominated by the source Schottky contact, the device exhibits a
classical thermionic subthreshold slope until a flatband condition is reached between the
channel and source (V
g
= V
fb
). At V
g
> V
fb
the increasing V
g
enhances the electric field at the
source contact and increases tunneling, therefore, another subthreshold slope is obtained
with a slope much larger than the ideal 60 mV/dec. Taking
the plot
shows that
b
0.2 eV has similar current as the ballistic current limit, which indicates
that is the maximum allowed barrier height for implementation in CMOS technology.

Fig. 3.7. I
sb
-V
g
representing the source Schottky contact of a SB-MOSFET with t
ox
=1 nm and t
Si
=8 nm.
Also is shown estimated ballistic current of an ideal MOSFET.
In Fig. 3.8 a SB-MOSFET with
b
= 0.3 eV and t
Si
= 8 nm is shown, with t
ox
= 0.5 nm, 1
nm, and 4 nm. As t
Si
is decreased the electric field at the contact increases and the current
drive is enhanced. Therefore, as MOSFET technology is scaled down, the increased electric
field at the source enhances the performance of SB-MOSFETs. The device would reach the
ballistic limit with extremely thin equivalent oxide thickness (EOT) of 0.5 nm where the
field at the contact was = 4.5 MV/cm. This field is on the same order of magnitude as the
breakdown field of oxides. For instance the breakdown field of SiO
2
is approximately 10
MV/cm [9] and 4 MV/cm for HfO
2
[70]. Therefore, there is a limit to how much the gate
-0.2 0 0.2 0.4 0.6 0.8 1
10
-6
10
-4
10
-2
10
0
10
2
10
4
V
g
[V]
I

[
A
/
m
]
0.2 eV
0.3 eV
0.4 eV
SBH=0.5 eV
I
ball
=3 mA/m
V
fb
SBH=0.1 eV
28

induced field can enhance tunneling in SB-MOSFETs. Careful simulations have shown
b

= 0.1-0.15 eV is the maximum allowed for implementation in CMOS technology [71] and
(Paper VII).

Fig. 3.8. I
sb
-V
g
representing the source Schottky contact of a SB-MOSFET with b = 0.3 eV and t
Si
= 8
nm. Also is shown estimated ballistic current of an ideal MOSFET, which increases with decreasing
t
ox
.
The choice of metal silicides is discussed later, but the minimum SBH of practical silicides
is ~0.2 eV for pMOS (PtSi) and ~0.3 eV for nMOS (ErSi), which is close to the required
limit for barrier heights, but especially for nMOS it is not likely the ITRS target for R
SD
can
be realized. Since
b
is too large, SB-MOSFETs with doped extensions to reduce the
effective barrier height are discussed in the next Section.
3.3.2 SB-MOSFETs with doped extensions
In order to minimize the effective barrier height, a shallow layer of dopants can be placed in
front of the SB contact. The dopants enhance the electric field at the interface and therefore
the current. In order to clarify the discussion, it is useful to define two ranges of devices
with doped extensions, the fully depleted contact (Fig. 3.9(a)), and partially depleted
contact (Fig. 3.9(b)). That is, the SB contact has depletion length:
-0.2 0 0.2 0.4 0.6 0.8 1
10
-6
10
-4
10
-2
10
0
10
2
10
4
V [V]
I

[
A
/
m
]
I
ball
=0.8 to 5 mA/m
t
ox
=4 nm
t
ox
=1 nm
t
ox
=0.5 nm
3. MOSFETs
29

(3.17)
where N
ext
is the doping concentration of the extension. If the doped extension has a length
(L
ext
), when L
ext
< W
s
the extension doping is fully depleted and when L
ext
> W
s
it is partially
depleted.
The reason it is important to distinguish between the two cases is that in the fully depleted
case (Fig. 3.9(a)), the electric field at the Schottky contact is affected by the field from the
gate. However, in the partially depleted case (Fig. 3.9(b)) the effect of the field from the
gate is decreased since the gate field is screened by the mobile carriers in the non-depleted
portion of the extension.

Fig. 3.9 (a) SB-MOSFET with a shallow fully depleted extension. (b) MOSFET with a thicker
partially depleted doped extension, which essentially functions as a doped-S/D device connected to
small highly doped M-S contacts.
30

To evaluate the W
s
, it is necessary to know the potential drop across the contact V, which
would require numerical simulations. Since the N
D
is usually large enough to be degenerate,
then
bi

b
and V is small, we can write:

(3.18)
Given a certain doping concentration N
ext
, when L
ext
is small, the electric field of the contact
increases as L
ext
is increased, when L
ext
> W
s
the becomes independent of L
ext
and becomes
an ohmic contact with contact resistivity (
c
) that depends only on N
ext
and
b
. In these
devices one can consider a Schottky contact resistance (R
sb
) and extension resistance (R
ext
)
(Fig. 3.10(b-c)). In order to maximize the electric field at the interface L
ext
> W
s
is needed,
but having L
ext
longer than that will only increase R
ext
needlessly. In this case the R
sb
=
c
/t
si

[m] and R
ext
=
s
L
ext
/t
si
[m]. In order to estimate the resistances involved in R
sb
and
R
ext
a simple example will be shown. Assume
bn
= 0.67 eV (barrier height of NiSi to n-
type Si) and N
ext
= 10
20
cm
-3
. Then
c
= 310
-8
cm
2
(from Fig. 2.5) and
s
= 10
-3
cm [9].
Assuming t
si
= 10 nm and L
ext
= 15 nm, we get R
sb
= 300 m and R
ext
= 15 m. Thus the
extension length is not of primary importance, except that in real devices the junction
abruptness has to be considered. Therefore, it is clear that minimizing R
sb
is the primary
concern. As discussed above, the elevated S/D solution (Fig. 3.10(d)) has been used to
increase the contact area, but that adds complexity to the process. However, if it is possible
to increase N
ext
towards 10
21
cm
-3
, the R
sb
would be decreased sufficiently for
implementation in CMOS technology (see again Fig. 2.5). A promising method to introduce
enough dopants at the interface to obtain low contact resistance is the use of dopant
segregation, which is discussed in the next Chapter.
3. MOSFETs
31

Fig. 3.10 Resistance components of (a) SB-MOSFET (b) SB-MOSFET with fully depleted extension (c)
SB-MOSFET with partially depleted extension, and (d) elevated S/D MOSFET.
33

4. Metal silicides and dopant
segregation
Metal silicides are the most promising approach for implementing SB-MOSFET due to
their low formation temperature, self aligned processing and atomically abrupt interface
[72]. In the next Section the choice of silicides used in this work is motivated, followed by
a discussion on dopant segregation (DS). Experimental results from this work are presented
for DS on NiSi ending with a discussion on the modeling of DS.
4.1 Choice of silicides
The silicide processes used in this work were mostly developed by Zhen Zhang and
coworkers [73]. A more detailed description of the silicidation processes are found therein.
In order to be compatible with processing requirements for nanoscale CMOS technology, a
silicide has to have low resistivity, allow self aligned processing and have low interface
roughness. In recent years, NiSi has become the primary silicide for CMOS technology. It
can be formed at relatively low temperatures (~500 C), the resistivity is low (10-15 cm),
and self aligned silicide (SALICIDE) process is easily achieved by selective removal of
unreacted Ni by H
2
SO
4
:H
2
O
2
mixture.
One issue with NiSi is extreme lateral encroachment in UTB structures [74]. If there is
excess Ni, the NiSi can grow several hundred nm under the gate due to Ni diffusion in NiSi
[74]. Several solutions have been proposed to remedy this problem. It is possible to first use
low temperature (T=150C suggested in [75]) to form Ni
x
Si, followed by removal of excess
Ni, and subsequent formation of NiSi at 500 C [76]. Also, the use of thin Ni to not fully
silicide the S/D, and NiPt alloying has been suggested to control the lateral encroachment
[75].
The use of PtSi has also been considered in this work. PtSi has larger resistivity (30-
40cm) than NiSi. It has a large barrier to conduction band
bn
0.85 eV which may
cause issues with obtaining low contact resistivity for nMOS. However, PtSi has low
barrier to valence band and has attracted substantial interest for p-type SB-MOSFET
34

[77-79].
The self aligned process for PtSi is more challenging than for NiSi, since very few etchants
can etch the excess Pt selectively. Aqua-regia etches Pt but has little selectivity between Pt
and PtSi. A solution to this problem has been to anneal the sample in O
2
, before the aqua-
regia etch, forming either SiO
x
or PtSiO
x
on the silicide surface, which has higher
selectivity than the PtSi [73], [80]. This solution was used in this work. Another method for
self aligned formation involves depositing Ge after PtSi formation, and annealing at low
temperature. The unreacted Pt forms PtGe that can be removed using H
2
SO
4
:H
2
O
2
[81].
Ni
1-x
Pt
x
Si alloying with low Pt content has shown increased stability of silicide at high
temperatures [82]. Analysis on Schottky diodes show
bn
is modified from 0.67 eV for pure
NiSi to 0.8 eV for Ni
0.9
Pt
0.1
Si [83]. The
bn
for PtSi is 0.86 eV and therefore a very low
concentration of Pt is needed to change the barrier height similar values as PtSi. Local
electron atom probe (LEAP) measurements analysis showed Pt atoms condense at the
silicide/Si interface [84], which likely explains the large barrier shift at low concentrations.
The use of Ni-Pt alloy has also been suggested to control the lateral silicide growth of NiSi
[75]. Other Ni alloys have also been demonstrated. Metal segregation of Y and Yb on
NiSi/Si diodes has shown a modulation of 0.1-0.15 eV towards conduction band [85]. Co-
sputtering of Ni alloys using (Yb, Er, Ti, Al) for silicide formation results in modification of
SBH compared to pure Ni [86]. Largest modulation is found for NiAl which has
bn
= 0.45
eV compared to 0.65 eV for pure NiSi.
By depositing extremely thin layers of Ni (t
Ni
< 4nm) it has been shown that epitaxial
NiSi
2-y
can be grown. PtSi does not grow epitaxially even for 1 nm deposited metal, but
epitaxial growth was observed for Ni(Pt)Si
2-y
(t
NiPt
< 2nm ) with 4% Pt [87]. A self limiting
process to obtain thin NiSi
2
is to deposit relatively thick metal followed by immediate
stripping of the metal by wet etching. An intermixed layer is left on the surface, and the
silicide is formed by RTA [88]. By modifying the metal sputtering conditions the thickness
of the silicide can be modified to some degree [89]. Since these epitaxial films are Si rich
their resistivity is relatively large, for example a 7.1 nm epitaxial NiSi
2
film had a sheet
resistance of 73 /sq [89], corresponding to resistivity of
s
= 52 cm. The epitaxial films
are interesting since they may allow fabrication of SB-MOSFETs with low variability and
high degree of thickness control. The main issue is the silicide resistivity, which is
4. Metal silicides and dopant segregation
35

considerably larger than for NiSi, but is still lower than that of highly doped Si.
4.2 Dopant segregation
As has been discussed, the reduction of contact resistance in SB-MOSFETs is critical for
the viability of SB-MOSFETs. An exciting development towards this purpose is the use of
dopant segregation (DS). Over three decades ago Muta [90] found that in PtSi formed on
As doped Si, the As in the consumed part of the Si was piled up at the silicide interface.
Wittmer and Seidel [91] implanted As into a shallow layer close to the surface of a Si wafer
and a grew thick enough PtSi or Pd
2
Si so that the silicon containing the As was consumed.
They found that the As segregated at the silicide/Si interface and suggested that their
method could be used for obtaining low contact resistances. Later Thornton [92] found that
B segregation during PtSi formation raised the measured
value. Although DS is not a

new discovery, it was only recently (2004) used in SB-MOSFETs [93], where CoSi
2
with
As DS was used to enhance the performance of n-type SB-MOSFET. Since then many
publications have examined the DS properties of different silicides and dopants (Table 4.1).
The dopant segregation can be performed in three ways. First is silicidation-induced dopant
segregation (SIDS), where dopants are implanted into Si prior to metal deposition and
silicidation. The second uses silicide as diffusion source (SADS), where the silicide is
formed first, then dopant is implanted into the silicide followed by drive-in anneal.
Secondary ion mass spectrometry (SIMS) profile using the SADS scheme is shown in Fig.
4.1 for PtSi with As DS, from [94]. The SIMS profile shows a large pileup of dopants after
the drive-in anneal. However, from only SIMS data it is not possible to obtain a complete
picture of how the segregated dopants change the SBH. The spatial resolution of SIMS is
limited by interface roughness, and etch nonuniformity. Also, the SIMS does not give
information on dopant activation. In Chapter 5 of this thesis FinFET and UTB devices
using PtSi with As DS are demonstrated. The third scheme uses implantation to metal (ITM)
prior to silicidation. The ITM has been studied less than the other two schemes and a study
of B segregation in PtSi showed significantly smaller B segregation for ITM when
compared to SADS [95].
Table 4.1 shows results for SBH measurements from literature data. The lowest achieved
SBH was extracted in each case. Note that many of the publications use substrates of
opposite polarity for CV characterization and therefore measure large SBH. An estimate of
36

the SBH can be obtained by
bn
+
bp
= E
g
. According to Table 4.1 there are many
demonstations of SBH below 0.15 eV, but as will be discussed in the next Chapter, there are
not many publications of SB-MOSFETs with low R
SD
.
Comparing SIDS and SADS approaches, the SIDS scheme has been shown to give larger
barrier modulation for As and B using both NiSi and PtSi [94]. However, the SIDS scheme
may have issues for implementation in CMOS technology. First, the silicidation
temperature is changed in heavily doped Si (NiSi formation is increased by 50 C on n
+
Si
[96]), which could cause issues when using two different dopants on the same wafer.
Second, implant damage may cause transient enhanced diffusion, which can lead to
excessive diffusion of dopants even at the relatively low temperatures needed for silicide
formation [94]. The use of SADS scheme has been shown to reduce the contact resistivity
of heavily doped NiPtSi contacts [97].

Fig. 4.1 SIMS profile showing segregation of As implanted into formed silicide (SADS) before and
after 500 C and 700 C anneals. The anneal causes a pile-up of dopants at the PtSi/Si interface
(from [94]).

37

Table 4.1 Reported SBH for dopant segregated Schottky contacts on Si. (eV)
Silicide Sub. Dopant Dose (cm
-2
) Method T (C)
bn
(eV)
bp
(eV) Ref.
CoSi
2
n As 1 10
15
SIDS N/A <0.1 [93]
(Pt)ErSi n 600 0.1 [98]
ErSi n As 1 10
15
ITM 400 <0.12 [99]
NiPtSi n S 3 10
14
SIDS 450 0.05 [100]
NiSi p Al 2 10
14
SIDS 500 0.12 [101]
NiSi p As 1 10
15
SADS 700 0.85 [94]
NiSi p As 1 10
15
SIDS 650 1.05 [94]
NiSi n B 1 10
15
SADS 500 0.95 [94]
NiSi n B 1 10
15
SIDS 500 1.01 [94]
NiSi n C 5 10
15
SIDS 550 1.00 [102]
NiSi p C/As 5 10
15
/10
15
SIDS/
SADS
500/700 1.02 [102]
NiSi n C/B 5 10
15
/10
15
SIDS/
SADS
500/550 0.98 [102]
NiSi p In 1 10
14
SIDS 450 0.16 [103]
NiSi p P 1 10
15
SADS 600 0.9 [94]
NiSi n S 2 10
14
SIDS 550 0.07 [104]
NiSi n Se 2 10
14
SIDS 500 0.083 [105]
NiSi:C n Se 2 10
14
SIDS 950/450 0.1 [106]
NiSi
2

(epi.)
n P 1 10
16
SIDS 600 0.1 [107]
NiSi
2-y

(epi.)
p As 1 10
15
SADS 750 0.93 [108]
NiSi
2-y

(epi.)
n B 1 10
15
SADS 500 0.99 [108]
PtSi p As 1 10
15
SADS 750 0.96 [94]
PtSi p As 1 10
15
SIDS 750 1.05 [94]
PtSi n B 1 10
15
SADS 700 1.00 [94]
PtSi n B 1 10
15
SIDS 600 1.01 [94]
PtSi n

In 1 10
15
SADS 600 1.05 [94]
PtSi p P 1 10
15
SADS 700 0.92 [94]
PtSi n S 1 10
14
SIDS 450 0.12 [109]
PtSi n Se 2 10
14
SIDS 500 0.120 [105]
PtSi n B 1 10
14
SIDS 460 1.01 [92]

4.3 Dopant segregation on NiSi
A large amount of data exists for SBH modulation on NiSi by dopant segregation.
Promising results have been shown, not only for the common Si dopants such as B, As, and
P, but also for C, S and Se [110] (Table 4.1). Those results indicate that species which are
not good dopants in bulk Si may be able to segregate at the interface and modulate the SBH.
In this work the species beryllium (Be), magnesium (Mg), germanium (Ge), tin (Sn),
bismuth (Bi), and tellurium (Te) were tested for DS on NiSi. The use of group II dopants
for DS was motivated by ab-inito simulations [111] especially pointing out Mg. The results
for Be segregation have been published in Paper II. C has been shown to modulate [110]
SBH which is surprising since it is a group IV material. For this purpose Ge and Sn were
also tested. It has been suggested that for obtaining small n-type barrier the interface dipole
38

may be enhanced by using dopants with larger covalent radius than Si [112]. Bi and Te both
fall into this category and are therefore of interest for dopant segregation.
The devices were fabricated on degenerately doped n-type or p-type (100) Si substrates
with lightly doped epitaxial layer. The epitaxial layer has a resistivity of 17-25 -cm for the
n-type and 11-15 -cm for the p-type. On the n-type substrates samples were prepared with
both non-implanted NiSi, and implanted dopants Be, Mg, Ge, Sn. On the p-type substrates
local oxidation of silicon (LOCOS) isolation was used to define diode circles; samples were
prepared with non-implanted NiSi, and with implanted Bi or Te. The implanted samples
had dose 10
15
cm
-2
and the ion energy was set to give peak concentration at 15 nm below
the surface. On n-type substrates a 250 nm PECVD oxide layer was deposited, followed by
patterning circular diode structures and BHF etch. Subsequently, 30 nm of Ni was deposited
by electron beam evaporation. Rapid thermal anneal was carried out at different
temperatures (T=425-850 C) for 30 sec. Removal of excess Ni was performed using
H
2
SO
4
:H
2
O
2
bath. Finally, a TiW/Al stack was deposited on the wafer backside to reduce
parasitic series resistance.
Sheet resistances as a function of silicide formation anneal temperature are shown in Fig.
4.2. The NiSi phase is approximately in the range 500-700 C. Sn causes agglomeration of
the silicide, and high resistance was measured for T > 500 C. Also the film is not stable
with Te for T > 600 C. SIMS analysis has only been done for Be implanted sample, and is
shown in Paper II. SIMS analysis are important to verify segregation and therefore these
results (except for Be) should be viewed as preliminary. Nevertheless, the measurements
are good indicators to the efficacy of the various dopant species.
The SBH can be measured by several methods such as, Current-Voltage (IV), IV
Temperature (IVT), Capacitance-Voltage (CV), and Photoelectric emission (PE) [113].
Measurement of low SBH has limitations for all of these methods, the reverse leakage
current for CV and PE is too large for accurate extraction. For IV, IVT, and PE the series
resistance of the lowly doped semiconductor becomes much larger than the contact
resistance [114], which causes errors. The validity of published data claiming low or
negative SBH have been debated for Se passivation of Ti-Si contacts [115-117], and for Cl
segregation on NiSi [118], [119]. To solve these measurement issues Dubois and Larrieu
[114] have improved the conventional IVT measurements by decreasing the series
39

resistance and developing a model to take into account image force and tunneling effects.

Fig. 4.2. Sheet resistance as a function of formation temperature.
Alternatively, Zhang, et al. [120] have used CV measurements using substrates doped to the
opposite polarity, thus forming a large barrier. The method implies that
bn
+
bp
= E
g

which is generally valid for clean SB interfaces, and is a reasonable approximation for DS
interfaces as long as the dopants are within the first few monolayer of the interface. This
approach was used in this experiment. From the CV measurements the built in voltage

and substrate concentration for n-type substrate are extracted by [113]:
(4.1)
Using the acquired values the barrier height is obtained using:
(4.2)
where
is the conduction band effective density of states. Similar equations apply for p-
type substrate. Fig. 4.3 shows measured data on p-type substrate, with and without Te DS.
There is a clear increase in the intercept point showing that
is increased by Te DS.
Table 4.2 shows the measured barrier heights for 600 C formation temperature, except for
40

Sn implanted sample where 500 C formation temperature was used. The results for
reference samples have barrier heights that approximately add up to the Si bandgap. The
group II materials modulate barriers in opposite directions. The Be results are discussed in
detail in Paper II. For Mg there is a small reduction of
bn
. Mg has been reported to act as a
donor, when in interstitial lattice position [121], which may explain the results. The group
IV materials Ge and Sn show no barrier modulation. Bi and Te have moderate barrier
modulation but not sufficiently large for implementation in SB-MOSFETs. The results are
plotted with literature data in Fig. 4.4. Very recently Te has been reported to lower R
SD
40%
in FinFETs when co-implanted with As [122].

Fig. 4.3. 1/C
2
-V characteristics of a NiSi diode formed at T = 600 C on a p-type substrate with and
without Te DS.
Table 4.2 Results for barrier modulation of various dopants implanted into Si prior to NiSi formation.
Formation temperature was T=600 C unless otherwise indicated.
Dopant
bn
(eV)
bp
(eV)
No I/I p-sub 0.43
No I/I n-sub 0.72
Bi 0.5
Te 0.58
Ge 0.72
Sn 0.71*
Mg 0.65
Be 0.84
*Formed at T=500 C

-2 -1 0 1 2 3
0
0.5
1
1.5
2
2.5
3
3.5
4
x 10
16
V
1
/
C
2

(
F
-
2
c
m
4
)

Te I/I (D=110
15
cm
-2
)
No implant
41

Fig. 4.4.
bp
vs. group number for SBH on NiSi. (literature data from Table 4.1)
4.4 Modeling of dopant segregation
The SIMS data on DS SB does show a large pileup of dopants at the interface, but the
limitations in spatial resolution make modeling challenging. Experimental data suggests the
dopants are at the Si side of the interface, and that they are electrically active. A
compilation of results of SBH measurements on NiSi/Si with various segregated dopants
from the literature is shown in Fig. 4.4. The dopants are sorted according to their group
number in the periodic table of elements. As one could expect for doped Si, acceptor
dopants change the barrier towards valence band and donors towards conduction band. This
is consistent with dopants being activated on the Si side of the interface. Carbon
segregation is a special case that will be discussed later.
A study by Lew and Helms [123] of the redistribution of As during PtSi growth claimed the
pile-up of As at the interface is due to low solubility of As in PtSi and rapid diffusion along
grain boundaries. Muta [90] studied PtSi growth on As doped Si substrates and found As to
pile up at the interface. In that study, samples with doping concentration of 610
15
cm
-3
to
3.510
19
cm
-3
were used, samples with medium doping (3.510
17
cm
-3
) exhibit Schottky
(nonlinear I-V) behavior when PtSi is formed at 300 C but ohmic behavior when formed at
600 C. This suggests that although the dopants are piled up when the silicide is formed at
low temperature [123], they need to be activated at higher temperature to contribute to the
reduction of contact resistance.
42

In order to model the electrical behavior of a DS SB, it is necessary to know how far the
dopants have diffused from the interface. Attempting to use bulk diffusivity, As has an
estimated diffusion rate 110
-22
cm
2
/s at 600 C [124]. Given a typical 30s RTA, the
diffusion length is
is much smaller than 1 atomic length. The bulk

diffusivities are measured at higher temperatures then are used for silicidation. For the low
silicidation temperature the diffusivity can be increased significantly by transient enhanced
diffusion (TED) [125].
As discussed in Section 2.2, the reason SBH are pinned within the bandgap of the
semiconductor is because there is an interface dipole originating in charge redistribution
between the metal and semiconductor. In a similar fashion, the modulation of SBH due to
DS is caused by charge transfer between the depleted doped region and the metal. Shannon
[126] investigated the modulation of SBH by thin doped layers. In his approach a thin layer
on the order of 10 nm was placed at the interface. Due to enhanced tunneling a modified
SBH is observed (Fig 4.5(b)). If the layer is thick enough (or highly doped enough) so that
it is only partially depleted the junction will exhibit ohmic behavior.
Dopant segregation is expected to work in the same way as Shannon diodes, the main
difference with respect to the work of Shannon is that the dopants may be confined within a
very narrow region (Fig 4.5(a)). Due to the small sizes involved, the dopant segregation
has been investigated by ab-initio modeling [84], [111], [112], [127-130]. In these works a
dipole lowering mechanism has been proposed, where the active dopants in the narrow
region at the interface form a dipole which modifies the SBH.
LEAP measurements show As confined within 1 nm at the interface [84], Ab-initio
simulations show system energy is minimized when B or As is placed in a Si substitutional
position in the first few monolayers at the interface. Due to the reduction of energy barrier,
it was proposed the solid solubility of bulk does not apply and a solubility of ~10
22
cm
-3
for
B at the interface of NiSi and PtSi at 600 C [84]. Assuming this enhanced solubility is
confined to one monolayer of Si, the maximum dose at the interface is ~310
14
cm
-2
, or
every 5
th
atom is substituted by B.

43

Fig. 4.5 Band diagram of a metal-semiconductor junction in a small region close to the interface,
showing (a) interface dipole, and (b) thin doped layer in Si (from paper II.)
In the dipole model the dopants are assumed to be confined within ~1 nm region at the
interface, and therefore the band bending happens over a narrow region where tunneling
barrier is assumed to be transparent (Fig 4.5(a)). In the following an attempt is made to
estimate if the dipole lowering theory appears valid using experimental data. A simple
model is used, having two parallel plates with equal and opposite charge to model the
dipole barrier lowering (see Fig. 4.5(a)). We obtain an effective barrier height that is given
by:
(4.3)
Where D is the dose, t is the distance of the dopants from the interface, and
i
is an interface
dielectric constant, which takes into account the effect of the metal dielectric constant when
this close to the interface, and is given by:
[131]. Using,
we
have
.
To investigate if this simple dipole model can explain measured data, we analyze the data in
[94] where the segregation of As was investigated for PtSi and NiSi at various temperatures.
First, considering PtSi/Si interface with As segregation done at T = 700 C, the SIMS
profile is shown in Fig 4.1. Integrating the doping concentration close to the interface in we
obtain D ~ 410
14
cm
-2
. Assuming t = 0.25 nm (thickness of one monolayer) a
~ 0.8 eV
is obtained which is in reasonable agreement with the measured
which was 0.65 eV.

Next consider NiSi/Si with As segregation which has D ~ 110
14
cm
-2
that gives
~ 0.2
44

eV, the measured
was 0.45 eV. Since the estimation of D and t are very rough, and also
the activation percentage is not known, these estimations should be taken with caution.
However, they do show that the As dopant dose at the interface and the experimentally
observed barrier modulation for As DS is, within the correct order of magnitude, consistent
with the dipole lowering model. In Paper II the DS behavior of Be was studied. The
conclusion for Be is that dipole lowering does not explain the measured results, in the case
of Be dopants are distributed over a region of several nm.
From the discussion above it is apparent that in order to understand the dopant segregation
in SB diodes, more modeling work is needed to quantify diffusion and segregation of
dopants. The ab-initio work has indicated the segregation should be modeled as an interface
parameter. In [132] the segregation of P at SiO
2
/Si interface was modeled as a layer with a
certain trap density that can trap/emit dopants from/to either side of the interface. That
model may be a good starting point for modeling the segregation at silicide/Si interfaces,
but high resolution depth profiling of dopants would be needed to verify and calibrate the
model.
Experimental data for carbon DS on NiSi [110] (Fig. 4.4) shows smaller
bp
and suggests
the dipole lowering is not only related to activated dopants in Si. In [112] ab-initio
simulations of NiSi
2
/Si interface testing several different dopants were conducted. There it
was suggested that a dopant in active lattice position on the Si side of the interface did not
only behave as a classical dopant in Si but that the actual charge per atom was affected by
an additional effect. They claim that the charge on each atom is modified by either
electronegativity or covalent radius, that is a dopant with large electronegativity (or small
covalent radius) should attract charge locally from its neighboring Si atoms. Although those
are interesting results, the main DS modulation is affected by how many dopants can be
activated in the interface layer, and the first order charge per atom is related to the number
of acceptor (or donors). The results for carbon DS are consistent with ab-initio simulations
of SiC/Al and SiC/Ti interfaces [133], [134] that showed a reduction in
bp
for a C
terminated interface, compared to a Si terminated one. The results were explained by a
difference in the interface dipole that the two materials form.
So far the existence of an interface dipole effect has been motivated by looking at literature
data on ab-initio modeling, the validation that As is confined within 1 nm at the interface by
45

LEAP measurements and a simple dipole model approach has been used to see that the
measured barrier lowering is within the correct order of magnitude consistent with dipole
lowering. However, since the dopant distribution and activation is often not known, the
validation of the dipole lowering model cannot be considered complete. Especially, there is
possibility for error in interpreting the available data on SBH measurements for DS SB
contacts. The measurements are useful indicators of barrier height, but since the modeling
for the SBH extraction methods is based on conventional SB contacts, there is possibility
for measurement error. If the dopants are within the first few monolayers at the interface,
the measured SBH is correct. However, if the dopants are distributed over a larger region,
on the order of 10 nm, the tunneling barrier cannot be assumed transparent, and the
measured SBH is an effective barrier that represents the peak energy level of the current
flux (Fig. 4.6). The problem with the measurement in the case of a doped contact is that a
low effective barrier does not necessarily mean the contact resistance is low. This is
demonstrated in the following example.

Fig. 4.6 Schematic of a moderately doped SB contact (excluding IFBL). The effective barrier height
corresponds to the peak of the the carrier flux.

In Fig. 4.7 we consider a SB diode with
bn
= 0.5 eV barrier with varying doping
concentration (N
D
). A simulation was conducted using the Schottky diode simulator
described in Section 6.3. Using the simulator, it is possible to both obtain contact resistivity
(
c
) and carry out a simulated IVT extraction of effective barrier height (
). Fig. 4.7(a)
shows the effective barrier height extracted using the IVT method by simulating at different
temperatures. Also is shown the energy level of the peak current flux (see Fig. 4.6). The two
curves are in reasonable agreement which verifies that for large doping concentrations, the
IVT method measures an effective barrier which corresponds to the energy level of the peak
current flux.
46

But what does the effective barrier represent? For N
D
= 110
19
cm
-3
the
0.1 eV which
is very low, but Fig. 4.7(b) shows at this doping concentration the
c
= 10
-5
cm
2
which is
much too large for S/D technology. In this particular case the depletion width is only 7 nm.
Therefore, a DS SB diode with dopant distribution of ~10 nm could exhibit low effective
barrier but not necessarily have a very low contact resistivity. This is a very important
observation for DS contacts since the distribution of the doping concentration is usually not
known with high accuracy. Therefore, some results for DS shown in Table 4.1 could very
well be ohmic contacts that have low effective barrier but relatively large contact resistivity.
An analysis of sulfur DS on NiSi by Chan et al. [135] concluded in that case the observed
SBH lowering is due to doping and not barrier lowering.
In Paper VII we conclude a 0.15 eV barrier is needed to outperform the doped S/D
technologies. However, that assumes an actual barrier of 0.15 eV, where the gate field
contributes to tunneling. An effective barrier of a highly doped Schottky contact will not
perform nearly as well since the gate field cannot significantly increase tunneling.
Therefore, the most promising results on SB diodes ultimately need to be validated by
implementation in SB-MOSFETs.

Fig. 4.7 Simulation of SB with
bn
=0.5 eV, showing (a) extracted
bn
vs. N
D
and (b)
c
vs. N
D
.
47

5. SB-MOSFETs: fabrication and
characterization
In this work SB-MOSFETs with PtSi as the S/D metal and As DS have been fabricated and
characterized. The main results have been published in Paper IV and have been compared
with simulations in Paper V. In this Chapter the fabrication and characterization of SB-
MOSFETs are discussed centering around the work on PtSi S/D. Finally, the state-of-the-art
in SB-MOSFETs is discussed. In order to fabricate short gate length devices a sidewall
transfer lithography (STL) process was developed, and is discussed in the next Section.
5.1 Sidewall transfer lithography
In order to fabricate nanoscale UTB and tri-gate MOSFETs devices a nanoscale patterning
technique is required. The sidewall transfer lithography (STL) technique (also called spacer
patterning), [136-138], has been proposed for wafer scale fabrication of nanowires. The
process flow for the STL is shown in Fig. 5.1. The process had been developed at KTH
[139], but relatively large line roughness inhibited scaling below 50 nm. In this work the
spacer technique has been improved to produce low roughness nanowires scalable down to
15 nm.
A detailed list of steps for the final STL process that was developed is shown in Table 5.1.
This table assumes a SOI wafer that has been thinned down to desired thickness, and has
alignment marks. Pattering is done with a I-line lithography stepper (using Shipley
Megaposit 700-1.2 resist). Dry etching is performed using an Applied Materials P5000 tool,
and in Table 5.1 the power, pressure and gas flows are given. In the following, the work
leading to this process is discussed.

48

Fig. 5.1 Optimized sidewall transfer lithography (STL) process flow

5. SB-MOSFETs: fabrication and characterization

49

Table 5.1 Sidewall transfer lithography process steps.
# Description

Time Comment
1 Deposit TEOS oxide (hard-mask)

LPCVD thk 25 nm

2 Deposit amorphous Si (-Si) (support layer)

LPCVD thk 150 nm
3 Deposit SiN (second hard-mask)

PECVD thk
25 nm

4 Pattern nanowire layer
5 Descum resist

80W, 90mTorr, O2 (20 sccm)

t=15 sec

6 Dry etch SiN/remove resist

80W, 50mTorr, CHF3/CF4/O2 (5/8/5 sccm) endpoint

7 Dry etch -Si

250W, 125mTorr CL2/HBr (10/40 sccm)

t=8 sec Breakthrough

200W, 125mTorr Cl2/HBr/He-O2 (10/30/10 sccm) endpoint Main etch
8 Wet etch SiN

H3PO4 T=125C

t=6min

9 PECVD deposit SiN (spacer layer)

Layer thickness will define the final nanowire thickness

10 Dry etch SiN

80W, 50mTorr, CHF3/CF4/O2 (5/8/5 sccm) endpoint Etch SiN
11 Open -Si layer


t=8 sec

12 Wet etch -Si

TMAH 25% T=60C

Watch for color change. Time approx. 90-120 sec

13 Pattern contact pads
14 Dry etch TEOS/strip resist

350W, 150mTorr CHF3/Ar (20/50 sccm)

t=15 sec

15 Dry etch -Si


t=8 sec Breakthrough

200W, 125mTorr Cl2/HBr/He-O2 (10/30/10 sccm)
depends on
SOI thk.
Main etch
16 Wet etch TEOS

HF 5%

t=30 sec

In order to reduce the line edge roughness, there were two changes made to the process
developed in [139]. One, the sacrificial layer was originally poly-SiGe, but as was shown in
Paper III of this thesis, the dry etching of poly-SiGe using Cl
2
/HBr chemistry results in a
significant increase of sidewall roughness compared to the photoresist rougness. Results for
single crystalline etched Si showed very low line edge roughness (LER), compared to the
poly-SiGe. In this work, amorphous Si (-Si) was instead used as the support material,
which has significantly reduced LER. Two, in addition to changing the sacrificial material,
a descum process (weak O
2
plasma) was used to etch a part of the photoresist, which results
50

in a sharper photoresist boundary (Fig. 5.2.). A significant improvement in LER and line-
width-roughness (LWR) was observed (Fig. 5.3.). The roughness was extracted using an
edge detection program (developed by Gunnar Malm at KTH), which gives the one
standard deviation (1-) LER and LWR values. For the old process LER = 6-12 nm and
LWR=2-4 nm, and the new -Si process, with descum, had LER = 2-3 nm and LWR <2 nm.

Fig. 5.2. A birds-eye view of a photoresist sidewall, using (a) no descum and (b) with descum. The use
of descum (short etch with a mild O
2
plasma) etch reduces the sidewall roughness.

Fig 5.3. (a) poly-SiGe support material, LER 6-12 nm and LWR 2-4 nm, (b) new -Si support
material, with descum, LER 2-3 nm and LWR <2 nm.
After the roughness had been decreased, there was an issue with scaling related to the etch
anisotropy of -Si. An Applied Materials Precision P5000 cluster tool was used, using
200 W RF power, 125 mTorr pressure, with HBr, Cl
2
, and 10% O
2
in He (10/30/10 sccm)
gases. When a photoresist mask was used the etch angle was 77-83. This angle causes the
spacer mask to become tilted (Fig. 5.4(a)), which creates two problems. One, the line width

51

is larger than the SiN deposition thickness, and two, the narrow spacer mask is more
exposed when anisotropic etching is used to etch the layer below. To fix this problem a SiN
hard-mask was used when etching the support layer, which makes the etch nearly
anisotropic (Fig. 5.4(b)). When using the hard-mask process, an issue with variability of
etch angle was observed. This was traced back to the standard procedure of using
photoresist masked wafers to season the chamber before etching sharp wafers. The
increased carbon concentration residing on the chamber walls after seasoning caused the
first wafers of a batch to have more residual carbon than the last wafers etched. To remedy
this, a blank Si wafer was used to season the chamber before etching the sharp wafers.

Fig. 5.4. Showing spacers defined using a support material defined by (a) photoresist mask, and (b)
SiN hard-mask.
Another issue with scaling down the mask is that when the mask is very narrow, the
subsequent hard-mask and Si etches have large aspect ratios. The dry etch recipes that are
used are not perfectly selective or anisotropic. Specifically the oxide hard-mask that is
etched after the SiN spacers are defined, uses a CF
4
/CHF
3
chemistry that has only 4:1
selectivity to SiN. When scaling below 30 nm the SiN mask was totally removed, due to
lack of selectivity and etch anisotropy. To solve this problem, the etch recipe was changed
from CF
4
/CHF
3
mixture to CHF
3
only, and the TEOS hard-mask was thinned to 25 nm,
which allowed scaling down to 15 nm line width (Fig. 5.5).

52

Fig. 5.5. Best result for STL process, a 15 nm poly-Si NW with low roughness.
5.2 Device fabrication
In this work tri-gate SB-MOSFETs with PtSi S/D and As DS were successfully
demonstrated for the first time. Both UTB and tri-gate devices were fabricated on the same
wafer. Starting with lightly doped (N
A
= 110
15
cm
-3
) SOI wafers, the process was as follows:
- Thinning of SOI to 35 nm
- Tri-gate and UTB channels formed by STL and mesa etch on same wafer
- 5 nm sacrificial oxide grown and etched to repair sidewall damage
- 2.2-nm gate oxide grown
- n
+
poly-Si gate formed by STL process
- Slim gate spacer SiO
2
/SiN (5/10 nm) formed
- PtSi formed (14nm Pt) at 600 C
- As 110
15
or 510
15
cm
-2
implanted
- Drive in anneal 700 C for 30 sec
- TiW/Al contact pad metallization
- Forming gas anneal 400 C for 30 min

The fabricated wafers also had p-type PtSi S/D devices without As implant. A TEM of the
UTB MOSFET is shown in Fig. 5.6. Top-view SEM of the tri-gate FET is shown in Fig. 5.7,
and TEM in Fig. 5.8.

53

Fig. 5.6. XTEM of UTB SB-MOSFET with PtSi S/D and As DS.

Fig. 5.7. Top-view SEM image of tri-gate SB-MOSFET (a)-(b) after gate formation and (c) finished
wafer.
54

Fig. 5.8. XTEM of the channel of a tri-gate SB-MOSFET .
5.3 Electrical characteristics
The I
d
-V
g
curve for the PtSi-S/D MOSFETs is shown in Fig. 5.10. The barrier modulation
by As segregation is significant and a rather poorly behaving pMOS is changed to an nMOS
with reasonable performance. Note that in Fig. 5.10 the pMOS is measured with positive
V
ds
as the nMOS for direct comparison.

Fig. 5.10. I
d
-V
g
for (a) UTB and (b) tri-gate MOSFETs with PtSi-S/D, either with or without As DS
(dose 510
15
cm
-2
) (from Paper IV).
The I
d
-V
d
curve for UTB devices with and without DS is shown in Fig. 5.11. The PtSi-S/D
without DS (Fig. 5.11(a)) has low ON current and the current is dominated by the Schottky
contact resistance. For the device without DS, nonlinear output characteristics are observed,

55

since as V
d
is increased the drain Schottky junction changes from reverse to forward bias.
The device with As DS (Fig 5.11(b)) has large ON current, where the current transport is
limited both by the Si channel and the source drain junction. The output characteristics have
clear linear and saturation regions. More data on these devices is found in Paper IV.

Fig. 5.11 I
d
-V
d
for a UTB SB-MOSFETs of L
G
=90 nm (a) without DS and (b) with As I/I (dose 510
15

cm
-2
) for DS.
The noise performance of the devices fabricated in this work, has been studied [140]. The
results showed that the channel noise was dominating and the low effective barrier height in
devices with DS did not introduce additional noise.
In SB-MOSFETs the parasitic series resistance (R
SD
) is an important figure-of-merit. In
doped S/D MOSFETs the doped extension usually extends under the gate of the MOSFET
so that the electrical channel length
is smaller than the measured gate length L. It is

often possible to measure several devices with different gate length at different gate biases
and using that
, where
is the sheet resistance of the

channel and
is the effective channel length. Since
decreases as V
g
is increased,
can be plotted as a function of L for several V

g
, the
is read of at the interception

of the lines [141]. For SB-MOSFETs this approach does not work since
also varies as
V
g
is changed. This is shown in Fig. 5.12 which shows an
vs. L plot for the UTB

devices used in Paper V. In Fig. 5.12(b) the intersections of the
between different V
g
-V
t

is shown. Since
varies significantly there is no common interception point. In these

devices there is also an underlap between gate and metal (see Fig. 5.6). In such a device the
56

varies not only by changing the tunneling barrier, but also the inversion charge outside
the gate depends on the fringing field. Instead, a first order approximation was made by
defining
as the resistance taken at L = 0 in Fig. 5.12(a), as shown in Fig. 5.13.

Fig. 5.12. (a) Linear extrapolation of R
tot
vs. L at various V
g
-V
t
for UTB SB-MOSFET with As DS
(dose 510
15
cm
-2
), and L=90 nm to 1.5 m . (b) zoom at the intersection of the curves, the intersection
does not give the correct R
SD
.

Fig. 5.13.
vs. V
g
-V
t
taken as the resistance in Fig. 5.12(a) when L=0.
Due to the complex combination of factors contributing to R
SD
, the analysis was aided by
numerical simulations. In Paper V the UTB devices described in Section 5.2 were simulated
using Sentaurus device simulation software. The simulations were used to give insight into
whether the DS devices behaved as if the DS had decreased
bn
(Fig. 3.10(a)) or as a highly
doped Schottky contact with large
bn
(Fig. 3.10(c)). The simulation setup is given in Paper
V. The conclusion of the simulations was that the measured data could not be modeled by
0.5 1 1.5 2
1000
1200
1400
1600
1800
2000
V
G
-V
T
[V]
R
S
D

[
O

m
]

57

only SB lowering or only as doped-S/D contact, but assuming a combination of barrier
lowering and shallow doped contact, a good agreement between measurements and
simulations was found.
The R
SD
shown in Fig. 5.13 is relatively large, about 1.2 km @ V
g
-V
t
=1.5 V. However,
the underlap between the gate and S/D silicide was 15 nm (Fig. 5.6), which adds to the
measured resistance. Using the best fit from simulations in Paper V, a MOSFET with no
underlap was simulated; in that case the R
SD
is decreased to 800 m.
5.4 State-of-the-art
A comparison of the literature data for SB-MOSFETs is not straightforward. One issue is
that many gate lengths, and S/D designs are published with different temperature budget.
Also, as discussed previously the extraction of R
SD
is difficult. A detailed comparison of I
on
-
I
off
values of SB-MOSFETs was compiled by Dubois et al. [142] (Fig. 5.14). For both
nMOS (Fig. 5.14(a)) and pMOS (Fig. 5.14(b)) there is a clear improvement in performance
for DS devices when compared to devices without DS. The best pMOS devices use PtSi
with B DS, and a low temperature process is sufficient to obtain good performance [95].
The efficacy of low temperature process in this case is likely due to having PtSi with low
SB to start with, since pMOS devices without DS perform reasonably well. The PtSi device
without DS shown in the last Section has lower ON current than has been demonstrated in
literature (Fig. 5.11(a)). The low ON current is likely caused by the underlap between
source and channel in these devices, which decreases tunneling. The nMOS devices without
DS perform quite poorly, with best results for ErSi devices [5]. Devices with DS at low
temperature also fail to achieve very high ON current, and the best devices use high
temperature anneal [143].
Fig. 5.14 shows the DS technique works, even using low temperature processing, but
especially in the case of nMOS there are no demonstrations which would outperform doped
S/D technologies. Since there are many demonstrations of sub 0.15 eV SBH measured on
SB diodes with DS (Table 4.1), it should be expected that more demonstrations of low R
SD

had been shown by now. Partially the reason may be that the devices in many of the
publications are not optimized for minimum underlap and other process parameters. Also, it
is likely that some of the experimental data for DS on diodes is from highly doped contacts
that have low effective barrier but not low contact resistivity (see Section 4.4).
58

Fig. 5.14. Performance of SB MOSFETs (a) pMOS (b) nMOS devices. Open symbols are SB-
MOSFETs without DS, and closed symbols with DS. High temperature data uses T>950 C. The star
marked data were achieved during European Commission projects NANOSIL and METAMOS. Also is
shown strained technology by contact etch stop layer (CESL). (Figures from [142]).
59

6. Modeling of transport in short
channel SB-MOSFETs
As the gate lengths of MOSFETs are decreased, the large lateral electric field in the channel
causes the carriers to cross the channel far from thermal equilibrium with the lattice. When
this happens, the modeling of carrier transport by drift-diffusion, approach becomes
increasingly inaccurate [144]. The Monte Carlo (MC) method is commonly used to solve
the Boltzmann Transport Equation (BTE) [144], for simulating short channel MOSFETs
[43], [145], [146].
Most MC simulators do not account for the quantization of the inversion layer of a
MOSFET. This may cause errors in small MOSFETs where there is a large subband
splitting, caused by gate bias, and thin Si body. A multi-subband Monte Carlo (MSMC)
method has been developed [147][148] that takes into account the subband splitting in the
inversion layer by solving the 1D Schrdinger equation in the confinement direction and
then solves the BTE for each subband.
The Monte Carlo method is excellent for simulating non-equilibrium transport [149].
However, since it is a semi-classical method, quantum effects are not inherently accounted
for and have to be added to the simulation. For implementing SB contacts in MC, the
tunneling through the barrier must be accounted for. The WKB and Airy function transfer
matrix methods has been used to account for quantum effects in MC simulators before
[150-152], also a quantum correction to the classical potential [153] has been used.
However, to this authors knowledge, SB contacts for the MSMC have not been
implemented before. In this thesis work a MSMC simulator, developed at the University of
Udine [148], has been modified to account for Schottky contacts.
6.1 The multi-subband Monte Carlo method
The MSMC method has been described in detail in [148], [149]. A short introduction is
given here. The flowchart for the simulation is shown in Fig. 6.1(a). A schematic of a
typical simulated structure is shown in Fig. 6.1(b). Starting with a guess for the potential
60

V(x,y) the simulation domain is split up into n sections and in each section the Schrdinger
equation is solved to obtain the subband energy levels (Fig. 6.1(c)). By combining the
sections, the subband profile along the channel is obtained for each subband. The scattering
rates are then calculated for different scattering mechanisms. The MC method is used move
particles through the device, to obtain the occupation function, which, combined with the

Fig. 6.1. (a) Flowchart of the MSMC simulator used in this thesis work [154]. (b) Schematic of the
MSMC structure [148]. (c) Band profiles and energy levels in one section (from [155]).
6. Modeling of transport in short channel SB-MOSFETs
61

wavefunctions, give the carrier concentration n(x,y). The carrier concentration is used to
solve Poisons equation to obtain a new estimate of V(x,y). This cycle is repeated until the
current has similar value for at least 5 iterations.
So far, the subband, and charge smoothening shown in Fig. 6.1(a) have not been mentioned.
In these steps the charge and subband profiles are convoluted with a Gaussian function. The
Gaussian function represents the electron wavepacket, and by this convolution, an effective
subband energy is obtained, that mimics quantum effects in the channel. For instance the
smoothening approach has been used to account for source to drain tunneling in ultra short
channel MOSFETs [154]. In this thesis work the subband smoothening approach has been
implemented for Schottky contact tunneling, which is discussed in the next Section.
6.2 Implementation of Schottky barriers
As discussed in Section 2.1 the current transport through a Schottky barrier should take into
account the thermionic emission above the barrier and the tunneling through the barrier,
while also accounting for image force barrier lowering (IFBL).
The IFBL has been implemented as shown in Eq. 2.5. The classical image force potential
has a singularity at the interface, quantum simulations using the local-density-
approximation have found the classical image potential is correct a short distance from the
interface [156], [157]. In this work the singularity was removed by cutting off the IFBL
function: IFBL(x) < -0.5 eV =-0.5 eV. The dielectric constant for IFBL can for some
semiconductors be lower than the static dielectric constant since the semiconductor does
not have enough time to become polarized during the fast transfer of the electron across the
barrier. For Si, it has been shown by photoelectric measurement that the static dielectric
constant of Si is correct for IFBL [158]. An energy band profile of a SB contact with
bn
=
0.5 eV, and N
D
= 110
19
cm
-3
is shown in Fig. 6.2. The dotted line shows profile after
applying IFBL.
In order to account for tunneling, a Gaussian smoothening model was used. This method
had been proposed [159], [160] to obtain an effective potential in the confinement direction
of a MOSFET. The smoothened energy
is obtained by:
}
= ' ) ' ( ) ' ( ) ( dx x x g x E x E
w i
smth
i

(6.1)
62

}
=
2
1
' ) ' (
) (
) (
x
x
w
dx x g
x g
x g

(6.2)
where x
1
and x
2
are the position of the source and drain SB and g(x) is given by:
2
0
2
2 /
0
2
1
) (
a x
e
a
x g

=
t

(6.3)
A weighted Gaussian (Eq. 6.2) was used instead of conventional Gaussian (Eq. 6.3) in
Paper VII, the reason is described therein. The solid line in Fig. 6.2 shows the smoothened
subband, where the peak of the barrier is significantly decreased from 0.5 eV to 0.25 eV.
Taking thermionic emission above the barrier a current flux is obtained, and the barrier
lowering mimics the tunneling through the barrier. In order to prove the validity of the
approach, extensive comparisons to conventional tunneling models have been carried out.
In paper VII the results of the MSMC simulations using the effective potential model are
compared to non-equilibrium Green functions (NEGF) [161] simulations and WKB
simulations. However, before the model was implemented in the MSMC simulator, a diode
simulator was programmed in order to compare the different tunneling models directly; the
results of that work are shown in the next Section.

Fig. 6.2. Band diagram showing band energy before, and after subband smoothening. The current
flux is taken above the smoothened barrier (from Paper VII).
63

6.3 Schottky diode simulator
The flowchart for the Schottky diode simulator is shown in Fig. 6.3. The simulator is 1D
and does not take into account scattering. Given
bn
, and N
D
, it solves self consistently the
Fermi-Dirac and Poisson equations to obtain the potential profile in the Si. After adding
IFBL to the potential, the tunneling probability T(E) is obtained (see next Section). Finally,
the current flux is obtained using Eq. 2.1.

Fig. 6.3. Flowchart for the Schottky diode simulator.
Three tunneling models are considered for the diode simulator, the WKB method (See Eq.
2.4 and 2.5), the transfer-matrix (TM) [12] method, and the subband smoothening approach.
The WKB method uses an approximation to the Schrdinger equation, that assumes a
slowly varying potential V(x) [11]. That assumption is not necessarily valid in Schottky
contacts with large doping concentrations, but due to its simplicity it is commonly used in
simulations. The TM method was used by Tsu and Esaki [12] to obtain the tunneling
probability in a multilayer structure. The Schrdinger equation is solved in each section of
64

the device. The tunneling probability is obtained by multiplying a series of 2x2 matrixes
that satisfy the condition of continuity of the wave function and its derivative.
To analyze the difference between WKB and TM, a simple sinusoidal barrier, with 10 nm
width, is simulated in Fig. 6.4(a). The tunneling mass was set to conduction band of Si (m
*

= 0.19m
0
). In Fig. 6.4(b) the tunneling probability is shown for WKB and TM. In this case
the tunneling probability is larger for WKB, especially the WKB method neglects reflection
above the barrier. One can therefore expect then that for barriers with relatively low
tunneling, that the WKB method overestimates the tunneling current.
In Fig. 6.5(a) the sinusoidal barrier is decreased to 1 nm, this is a semi-transparent barrier
with respect to tunneling, and the tunneling probability (Fig. 6.5(b)) is large below the
barrier. In this case, the TM method has an increased tunneling probability at low energy
compared to the WKB. Since the carrier concentration decreases exponentially as a
function of energy, the current flux will be dominated by carriers tunneling at low energy,
and therefore one can expect the WKB method underestimates the current when used in
ohmic contacts, where tunneling dominates the transport. This is consistent with Fig. 2.5
which shows that TM method gives lower contact resistivity than WKB for ohmic contacts.

Fig. 6.4. (a) Simulated tunneling barrier (b) T(E) calculated using WKB and TM approaches
The subband smoothening approach described in Section 6.2 was also implemented in the
simulator. Fig. 6.6 shows comparison between the calculated contact resistance using both
subband smoothening and TM approaches. The TM data is the same as used in Fig. 2.5. In
paper VII we found the Gaussian length of a
0
= 2.5 nm gave the best fit to NEGF
65

simulations. In Fig. 6.6 this same a
0
is used which shows good agreement between the two

Fig. 6.5. (a) Simulated tunneling barrier (b) T(E) calculated using WKB and TM approaches.
approaches for low SBH. For
bn
> 0.4 eV the agreement between TM and subband
smoothening methods is not good, but for the simulations done in this work the
bn
is
below 0.4 eV. The J-V characteristics of SB contacts doped N
D
= 10
18
cm
-3
are shown in Fig.
6.7. Reasonable agreement is found between the subband smoothening approach and the
TM tunneling results.

Fig. 6.6 Contact resistivity calculated using TM [12] tunneling models and the subband smoothening
approach. At
bn
0.4 eV the agreement between the two approaches is good. The TM data is the
same as in Fig. 2.5.
10
18
10
19
10
20
10
21
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
N
D
(cm
-3
)
C

o
n

<
1
0
0
>

n
-
S
i

(
O
-
c
m
2
)

TM
Sub. smooth
0.4eV
0.3eV
0.5eV
SBH=0.2 eV
66

Fig. 6.7. J-V characteristics of SB contact with N
D
=10
18
cm
-3
, using thermionic emission (TE) only,
TM model for tunneling, and subband smoothening approach. IFBL is taken into account for all cases.
6.4 Current transport in nanoscale SB-MOSFETs
The purpose of simulating SB-MOSFETs using the MSMC approach is to understand the
performance of SB-MOSFETs at small gate lengths. For conventional doped-S/D
MOSFETs the parasitic series resistance can generally be included externally simply as
lumped resistances (R
S
and R
D
) connected to the S/D regions. The Monte Carlo simulation
can then be performed with reduced internal biases which represent the potential drop in the
S/D regions. The primary effect of doped-S/D devices on the ON current of a nanoscale
MOSFET is that the inversion charge is decreased due to a decreased internal gate to source
bias. A secondary effect is the decreased V
DS
bias slightly increases backscattering to the
source, but this effect is small since the device is in saturation.
What makes SB-MOSFETs interesting for Monte Carlo study is that the SB at the S/D
regions directly influences the channel transport. That is, the SB-S/D causes an injection
bottleneck at the source (Fig. 6.8(a)). The reduced injection causes a sharper potential drop
close to the source end of the channel, compared to doped-S/D (Fig. 6.8(b)). In a short
channel MOSFET the carriers in the channel have a low probability of being backscattered
to the source once the band energy has dropped by kT [162]. If the potential at the virtual
source decreases by kT over a distance l
kT
a backscattering coefficient is defined as
-1 -0.8 -0.6 -0.4 -0.2 0
10
2
10
4
10
6
10
8
V (V)
J

(
A
/
c
m
2
)

TE
TM
Sub. smooth
|
bn
=0.2 eV
|
bn
=0.3 eV
|
bn
=0.1 eV
67

, where is the mean-free-path for carrier backscattering. The injection

velocity is v
inj
=v
th
(1-r)/(1+r) [162]. Since the l
kT
is shorter for SB-S/D the injection velocity
is larger than for doped-S/D.
Both the SB-S/D and doped S/D have decreased inversion charge which decreases the ON
current. For the SB-S/D, as the SBH is increased, the reduction in carrier injection is
counteracted somewhat by an enhanced v
inj
. The enhancement in v
inj
causes the device to
operate closer to its ballistic limit. However, considering the current (
), as SBH is
increased, the reduction in inversion charge is considerably larger than the enhancement of
v
inj
. These conclusions are discussed in more details in Paper VII, where a study of ITRS
2015 high performance node (L = 17 nm) was conducted, comparing doped-S/D and SB-
S/D approaches.

Fig. 6.8. Subband profile for short channel MOSFET (a) SB-S/D, taken after IFBL has been applied,
and (b) doped S/D. E
f-source
and E
f-drain
are the fermi levels at the source and drain, respectively.
69

7. Summary and future outlook
This thesis deals with the possibility of using SB-MOSFETs for future generations of
CMOS technology. There are several challenges to overcome in this technology, the first
being to obtainin sufficiently low SBH (or contact resistance) to outperform the
conventional doped S/D MOSFET. This work has dealt with several relevant issues that are
related to this challenge. The major results of this thesis are summarized below:
1. The measurement of low contact resistances usually requires systematic error correction
using graphs or simulations. In this case there are many input parameters and it is difficult
to know how the propagation of random measurement error affects the precision of the
extracted contact resistivity. In Paper I, a method to quantify the propagation of random
measurement errors for the cross-bridge Kelvin resistor is presented. In the case of
literature data where
c
values < 10
-8
cm
2
were reported, the error in input values is
multiplied up to ~40x when extracting
c
. Therefore, care should be taken when measuring
such low values, even when accounting for systematic error.
2. The use of dopant segregation is promising for realizing low resistance M-S contacts. In
this work unconventional species Be, Bi, and Te are tested for their modulation of SBH of
NiSi. In Paper II, a further study of Be segregation was conducted to deduce the mechanism
of barrier modulation. The barrier modulation caused by Be segregation was not explained
by interfacial dipole lowering, but the results were consistent with a thin (~4-5 nm)
activated dopant layer close to the interface.
3. In order to define the channel and gate of short channel tri-gate MOSFETs, a sidewall
transfer lithography process was optimized. In Paper III, the origin of sidewall roughness of
dry etched Si, poly-Si, and poly-SiGe was identified by studying sidewall roughness using
a sidewall AFM technique. Using amorphous Si support material in combination with resist
ashing, 15 nm lines were achieved with LER 2-3 nm and LWR < 2 nm.
4. In Paper IV, ultra-thin-body and tri-gate SB-MOSFETs were fabricated using PtSi S/D
and As DS. This combination of silicide and dopant is especially interesting to study since
70

As DS modifies SB-MOSFET from p-type to n-type. In Paper V, a simulation study was
conducted which showed that DS could be modeled by combination of barrier lowering and
doped Si extension.
5. For the first time, as shown in papers VI-VII, a Schottky contact model was implemented
in a multi-subband Monte Carlo simulator. These simulations were conducted in order to
better understand the behavior and SBH requirements for SB-MOSFETs in deca-nanometer
technologies. The model was used to compare doped-S/D to SB-S/D for the 2015 ITRS
high-performance technology node. The study concluded that
bn
0.15 eV is needed for
fulfilling the ITRS specifications.
The SB-S/D is a promising option for future CMOS devices. The decision to use SB-S/D
instead of doped-S/D will not only be decided by the R
SD
value, but will be based also on
which approach is best for integration in technology. The SB-S/D has several advantages
due to its simplified process flow, low temperature processing and abrupt junctions.
However, there are unresolved issues in this technology that require future work:
1. The understanding of DS is not complete. Both the diffusion and activation of dopants in
the silicide/Si system is not fully understood. Furthermore, since the dopant profile is not
known, it is not always clear if the barrier modulation by DS should be modeled by
tunneling transport or simply by modifying the SBH.
2. The number of publications claiming very low effective SBH on SB diodes with dopant
segregation far exceeds publications claiming low R
SD
values for SB-MOSFETS. While the
discrepancy is partially caused by non-optimized SB-MOSFETs, simulations have shown
that if the segregated dopants are not confined within the first few monolayer at the
interface, the low effective SBH does not necessarily mean the contact resistivity is low.
Further work measuring contact resistivity, for example using co-implantation in highly
doped contacts may aid in clarifying the efficacy of dopant segregation [97].
3. The control of silicide growth is crucial to achieve optimum underlap between gate and
silicide, to minimize variability, and for realizing extremely thin silicides. Recent results in
literature using single crystalline silicides are promising due to the high level of precision in
the silicide growth [87-89]. These silicides should be further studied for implementation in
SB-MOSFETs.
71

References
[1] G. E. Moore, Cramming more components onto integrated circuits, Electronics, vol. 38, pp.
114-117, 1965.
[2] K. Mistry et al., A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained
Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging, in
IEDM Tech. Dig., 2007, pp. 247-250.
[3] International Technology Roadmap for Semiconductors (ITRS), Austin, TX: SEMATECH,
2009. [Online]. Available: www.itrs.net.
[4] J. Colinge, Multi-gate SOI MOSFETs, Microelectron. Eng., vol. 84, no. 9-10, pp. 2071-
2076, Sep. 2007.
[5] D. Hisamoto et al., FinFET-a self-aligned double-gate MOSFET scalable to 20 nm, IEEE
Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, 2000.
[6] M. P. Lepselter and S. M. Sze, SB-IGFET: An insulated-gate field-effect transistor using
Schottky barrier contacts for source and drain, Proc. IEEE, vol. 56, no. 8, pp. 1400-1402,
Aug. 1968.
[7] J. M. Larson and J. P. Snyder, Overview and status of metal S/D Schottky-barrier MOSFET
technology, IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1048-1058, 2006.
[8] E. H. Rhoderick and R. H. Williams, Metal-semiconductor contacts, 2nd ed. Clarendon Press,
1988.
[9] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. New York: Wiley, 2007.
[10] R. Tung, Recent advances in Schottky barrier concepts, Mater. Sci. Eng., R, vol. 35, no. 1-
3, pp. 1-138, Nov. 2001.
[11] J. H. Davies, The Physics of Low-dimensional Semiconductors: An Introduction, 1st ed.
Cambridge: Cambridge University Press, 1997.
[12] R. Tsu and L. Esaki, Tunneling in a finite superlattice, Appl. Phys. Lett., vol. 22, no. 11, p.
562, Jun. 1973.
[13] C. R. Crowell, The Richardson constant for thermionic emission in Schottky barrier diodes,
Solid-State Electron., vol. 8, no. 4, pp. 395-399, Apr. 1965.
[14] N. F. Mott, The Theory of Crystal Rectifiers, Proc. R. Soc. London, Ser. A, vol. 171, no.
944, pp. 27-38, May 1939.
[15] R. T. Tung, Formation of an electric dipole at metal-semiconductor interfaces, Phys. Rev. B,
vol. 64, no. 20, p. 205310, 2001.
[16] M. Schlter, Chemical trends in metal-semiconductor barrier heights, Phys. Rev. B, vol. 17,
no. 12, pp. 5044-5047, 1978.
[17] J. Tersoff, Schottky barriers and semiconductor band structures, Phys. Rev. B, vol. 32, no.
10, pp. 6968-6971, 1985.
[18] V. Heine, Theory of Surface States, Phys. Rev., vol. 138, no. 6, Jun. 1965.
[19] W. Mnch, Role of virtual gap states and defects in metal-semiconductor contacts, Phys.
Rev. Lett., vol. 58, pp. 1260-1263, 1987.
[20] Y. C. Yeo, T. J. King, and C. Hu, Metal-dielectric band alignment and its implications for
metal gate complementary metal-oxide-semiconductor technology, J. Appl. Phys., vol. 92,
no. 12, pp. 7266-7271, 2002.
[21] R. T. Tung, Schottky-Barrier Formation at Single-Crystal Metal-Semiconductor Interfaces,
Phys. Rev. Lett., vol. 52, pp. 461-464, 1984.
[22] R. T. Tung, Chemical Bonding and Fermi Level Pinning at Metal-Semiconductor Interfaces,
Phys. Rev. Lett., vol. 84, no. 26, pp. 6078-6081, 2000.
[23] D. Connelly, C. Faulkner, P. A. Clifton, and D. E. Grupp, Fermi-level depinning for low-
barrier Schottky source/drain transistors, Appl. Phys. Lett., vol. 88, no. 1, 2006.
72

[24] A. M. Roy, J. Y. J. Lin, and K. C. Saraswat, Specific Contact Resistivity of Tunnel Barrier
Contacts Used for Fermi Level Depinning, IEEE Electron Device Lett., vol. 31, no. 10, pp.
1077-1079, Oct. 2010.
[25] J. Robertson and L. Lin, Fermi level pinning in Si, Ge and GaAs systems - MIGS or
defects?, in IEDM Tech. Dig., 2009, pp. 119-122.
[26] A. Toriumi, T. Tabata, C. Hyun Lee, T. Nishimura, K. Kita, and K. Nagashio, Opportunities
and challenges for Ge CMOS Control of interfacing field on Ge is a key (Invited Paper),
Microelectron. Eng., vol. 86, no. 7-9, pp. 1571-1576, Jul. 2009.
[27] C. Chang, Y. Fang, and S. Sze, Specific contact resistance of metal-semiconductor barriers,
Solid-State Electron., vol. 14, no. 7, pp. 541-550, Jul. 1971.
[28] K. K. Ng and R. Liu, On the calculation of specific contact resistivity on 100 Si, IEEE
Trans. Electron Devices, vol. 37, no. 6, pp. 1535-1537, Jun. 1990.
[29] K. Matsuzawa, K. Uchida, and A. Nishiyama, A unified simulation of Schottky and ohmic
contacts, IEEE Trans. Electron Devices, vol. 47, no. 1, pp. 103-108, 2000.
[30] H. H. Berger, Contact Resistance and Contact Resistivity, J. Electrochem. Soc., vol. 119,
no. 4, pp. 507-514, 1972.
[31] J. G. J. Chern and W. G. Oldham, Determining specific contact resistivity from contact end
resistance measurements, IEEE Electron Device Lett., vol. 5, no. 5, pp. 178-180, May 1984.
[32] S. J. Proctor, L. W. Linholm, and J. A. Mazer, Direct measurements of interfacial contact
resistance, end contact resistance, and interfacial contact layer uniformity, IEEE Trans.
Electron Devices, vol. 30, no. 11, pp. 1535-1542, 1983.
[33] W. M. Loh, S. E. Swirhun, T. A. Schreyer, R. M. Swanson, and K. C. Saraswat, Modeling
and measurement of contact resistances, IEEE Trans. Electron Devices, vol. 34, no. 3, pp.
512-524, Mar. 1987.
[34] K. Ohuchi et al., Extendibility of NiPt silicide to the 22-nm node CMOS technology, in
Proc. Int. Workshop Junction Technol.,, 2008, pp. 150-153.
[35] M. Finetti, A. Scorzoni, and G. Soncini, Lateral current crowding effects on contact
resistance measurements in four terminal resistor test patterns, IEEE Electron Device Lett.,
vol. 5, no. 12, pp. 524-526, 1984.
[36] A. Scorzoni, M. Finetti, K. Grahn, I. Suni, and P. Cappelletti, Current crowding and
misalignment effects as sources of error in contact resistivity measurements-Part I: Computer
simulation of conventional CER and CKR structures, IEEE Trans. Electron Devices, vol. 34,
no. 3, pp. 525-531, Mar. 1987.
[37] W. M. Loh, K. Saraswat, and R. W. Dutton, Analysis and scaling of Kelvin resistors for
extraction of specific contact resistivity, IEEE Electron Device Lett., vol. 6, no. 3, pp. 105-
108, 1985.
[38] T. A. Schreyer and K. C. Saraswat, A two-dimensional analytical model of the cross-bridge
Kelvin resistor, IEEE Electron Device Lett., vol. 7, no. 12, pp. 661-663, Dec. 1986.
[39] W. M. Loh, S. E. Swirhun, E. Crabbe, K. Saraswat, and R. M. Swanson, An accurate
method to extract specific contact resistivity using cross-bridge Kelvin resistors, IEEE
Electron Device Lett., vol. 6, no. 9, pp. 441-443, Sep. 1985.
[40] A. S. Holland, G. K. Reeves, and P. W. Leech, Universal Error Corrections for Finite
Semiconductor Resistivity in Cross-Kelvin Resistor Test Structures, IEEE Trans. Electron
Devices, vol. 51, no. 6, pp. 914-919, Jun. 2004.
[41] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, 1st ed. Cambridge:
Cambridge University Press, 1998.
[42] C. Hu, Modern Semiconductor Devices for Integrated Circuits, 1st ed. Prentice Hall, 2009.
[43] P. Palestri, D. Esseni, S. Eminente, C. Fiegna, E. Sangiorgi, and L. Selmi, Understanding
quasi-ballistic transport in nano-MOSFETs: part I-scattering in the channel and in the drain,
IEEE Trans. Electron Devices, vol. 52, no. 12, pp. 2727-2735, 2005.
[44] S. E. Thompson et al., A 90-nm Logic Technology Featuring Strained-Silicon, IEEE Trans.
on Electron Devices, vol. 51, no. 11, pp. 1790-1797, Nov. 2004.
[45] M. Lundstrom and J. Guo, Nanoscale Transistors, 1st ed. New York: Springer, 2006.
[46] R.-H. Yan, A. Ourmazd, and K. F. Lee, Scaling the Si MOSFET: from bulk to SOI to bulk,
References

73

Electron Devices, IEEE Transactions on, vol. 39, no. 7, pp. 1704-1710, 1992.
[47] Z.-H. Liu et al., Threshold voltage model for deep-submicrometer MOSFETs, IEEE Trans.
Electron Devices, vol. 40, no. 1, pp. 86-95, Jan. 1993.
[48] G. D. Wilk, R. M. Wallace, and J. M. Anthony, High- gate dielectrics: Current status and
materials properties considerations, J. Appl. Phys., vol. 89, no. 10, p. 5243, May 2001.
[49] C. F. Codella and S. Ogura, Halo doping effects in submicron DI-LDD device design, in
IEDM Tech. Dig., 1985, vol. 31, pp. 230-233.
[50] B. Mizuno, I. Nakayama, M. Takase, H. Nakaoka, and M. Kubota, Plasma doping for
silicon, Surf. Coat. Technol., vol. 85, no. 1-2, pp. 51-55, Nov. 1996.
[51] C. M. Ransom et al., Shallow n+ Junctions in Silicon by Arsenic Gas-Phase Doping, J.
Electrochem. Soc., vol. 141, no. 5, pp. 1378-1381, May 1994.
[52] K.-I. Goto et al., A high performance 50 nm PMOSFET using decaborane (B10H14) ion
implantation and 2-step activation annealing process, in IEDM Tech. Dig., 1997, pp. 471-
474.
[53] Y. F. Chong et al., Annealing of ultrashallow p
+
/n junction by 248 nm excimer laser and
rapid thermal processing with different preamorphization depths, Appl. Phys. Lett., vol. 76,
no. 22, p. 3197, May 2000.
[54] Intel Newsroom: Intel 22nm 3-D Tri-Gate Transistor Technology. [Online]. Available:
http://newsroom.intel.com/docs/DOC-2032. [Accessed: 19-Sep-2011].
[55] K. K. Young, Short-channel effect in fully depleted SOI MOSFETs, IEEE Trans. Electron
Devices, vol. 36, no. 2, pp. 399-402, Feb. 1989.
[56] L. Wei-Yuan and T. Yuan, On the scaling limit of ultrathin SOI MOSFETs, IEEE Trans.
Electron Devices, vol. 53, no. 5, pp. 1137-1141, May 2006.
[57] K. Uchida, H. Watanabe, A. Kinoshita, J. Koga, T. Numata, and S. Takagi, Experimental
study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI
thickness less than 5 nm, in IEDM Tech. Dig., pp. 47-50.
[58] D. Esseni, A. Abramo, L. Selmi, and E. Sangiorgi, Physically based modeling of low field
electron mobility in ultrathin single- and double-gate SOI n-MOSFETs, IEEE Trans.
Electron Devices, vol. 50, no. 12, pp. 2445-2455, Dec. 2003.
[59] T. Ernst, Fringing fields in sub-0.1 m fully depleted SOI MOSFETs: optimization of the
device architecture, Solid-State Electron., vol. 46, no. 3, pp. 373-378, Mar. 2002.
[60] V. P. Trivedi and J. G. Fossum, Nanoscale FD/SOI CMOS: thick or thin BOX?, IEEE
Electron Device Lett., vol. 26, no. 1, pp. 26-28, Jan. 2005.
[61] C. Lee, S. Yun, C. Yu, J. Park, and J. P. Colinge, Device design guidelines for nano-scale
MuGFETs, Solid-State Electron., vol. 51, no. 3, pp. 505-510, Mar. 2007.
[62] F.-L. Yang et al., 25 nm CMOS Omega FETs, IEDM Tech. Dig., pp. 255-258, 2002.
[63] M. T. Bjrk, H. Schmid, J. Knoch, H. Riel, and W. Riess, Donor deactivation in silicon
nanostructures., Nat. Nanotechnol., vol. 4, no. 2, pp. 103-7, Feb. 2009.
[64] M. Diarra, Y.-M. Niquet, C. Delerue, and G. Allan, Ionization energy of donor and acceptor
impurities in semiconductor nanowires: Importance of dielectric confinement, Phys. Rev. B,
vol. 75, no. 4, Jan. 2007.
[65] J. R. Pfiester, R. D. Sivan, H. M. Liaw, C. A. Seelbach, and C. D. Gunderson, A self-aligned
elevated source/drain MOSFET, IEEE Electron Device Lett., vol. 11, no. 9, pp. 365-367,
1990.
[66] B. S. Doyle et al., High performance fully-depleted tri-gate CMOS transistors, IEEE
Electron Device Lett., vol. 24, no. 4, pp. 263-265, Apr. 2003.
[67] S. Xiong and J. Bokor, Structural optimization of SUTBDG devices for low-power
applications, IEEE Trans. Electron Devices, vol. 52, no. 3, pp. 360-366, 2005.
[68] J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King, and C. Hu, Complementary
silicide source/drain thin-body MOSFETs for the 20 nm gate length regime, in IEDM Tech.
Dig., 2000, pp. 57-60.
[69] L. Calvet, Electrical Transport in Schottky Barrier MOSFETs, Yale University, 2001.
[70] B. H. Lee et al., Ultrathin hafnium oxide with low leakage and excellent reliability for
alternative gate dielectric application, IEDM Tech. Dig., pp. 133-136, 1999.
74

[71] S. Xiong, T.-J. King, and J. Bokor, A comparison study of symmetric ultrathin-body double-
gate devices with metal source/drain and doped source/drain, IEEE Trans. Electron Devices,
vol. 52, no. 8, pp. 1859-1867, 2005.
[72] S.-L. Zhang and M. stling, Metal Silicides in CMOS Technology: Past, Present, and
Future Trends, Crit. Rev. Solid State Mater. Sci., vol. 28, no. 1, pp. 1-129, Nov. 2003.
[73] Z. Zhang, Integration of silicide nanowires as Schottky barrier source/drain in FinFETs,
Royal Institute of Technology, 2008.
[74] J. Seger et al., Lateral encroachment of Ni-silicides in the source/drain regions on ultrathin
silicon-on-insulator, Appl. Phys. Lett., vol. 86, no. 25, p. 253507, Jun. 2005.
[75] J. Luo et al., On Different Process Schemes for MOSFETs With a Controllable NiSi-Based
Metallic Source/Drain, IEEE Trans. Electron Devices, vol. 58, no. 7, pp. 1898-1906, Jul.
2011.
[76] J. P. Lu et al., A novel nickel SALICIDE process technology for CMOS devices with sub-
40 nm physical gate length, in IEDM Tech. Dig., 2002, pp. 371-374.
[77] C. Wang, J. P. Snyder, and J. R. Tucker, Sub-40 nm PtSi Schottky source/drain metal--
oxide--semiconductor field-effect transistors, Appl. Phys. Lett., vol. 74, no. 8, pp. 1174-
1176, 1999.
[78] J. P. Snyder, C. R. Helms, and Y. Nishi, Experimental investigation of a PtSi source and
drain field emission transistor, Appl. Phys. Lett., vol. 67, no. 10, pp. 1420-1422, 1995.
[79] L. Calvet, Subthreshold and scaling of PtSi Schottky barrier MOSFETs, Superlattices
Microstruct., vol. 28, no. 5-6, pp. 501-506, Nov. 2000.
[80] Z. Zhang, S.-L. Zhang, M. Ostling, and J. Lu, Robust, scalable self-aligned platinum
silicide process, Appl. Phys. Lett., vol. 88, no. 14, p. 142114, Apr. 2006.
[81] N. Breil et al., Selective etching of Pt with respect to PtSi using a sacrificial low
temperature germanidation process, Appl. Phys. Lett., vol. 91, no. 23, p. 232112, Dec. 2007.
[82] D. Mangelinck, J. Y. Dai, J. S. Pan, and S. K. Lahiri, Enhancement of thermal stability of
NiSi films on (100)Si and (111)Si by Pt addition, Appl. Phys. Lett., vol. 75, no. 12, p. 1736,
Sep. 1999.
[83] R. T. P. Lee et al., Fully Silicided Ni1xPtxSi Metal Gate Electrode for p-MOSFETs,
Electrochem. Solid-State Lett., vol. 8, no. 7, p. G156, 2005.
[84] T. Marukame et al., Impact of platinum incorporation on thermal stability and interface
resistance in NiSi/Si junctions based on first-principles calculation, in IEDM Tech. Dig.,
2008, p. 547.
[85] Y. Nishi, Y. Tsuchiya, A. Kinoshita, T. Yamauchi, and J. Koga, Interfacial Segregation of
Metal at NiSi/Si Junction for Novel Dual Silicide Technology, in IEDM Tech. Dig., 2007,
pp. 135-138.
[86] R. T. P. Lee et al., Novel Nickel-Alloy Silicides for Source/Drain Contact Resistance
Reduction in N-Channel Multiple-Gate Transistors with Sub-35nm Gate Length, in IEDM
Tech. Dig., 2006, pp. 1-4.
[87] J. Luo et al., Surface-energy triggered phase formation and epitaxy in nanometer-thick Ni1-
xPtx silicide films, Appl. Phys. Lett., vol. 96, no. 3, p. 031911, Jan. 2010.
[88] Z. Zhang et al., Exploitation of a self-limiting process for reproducible formation of
ultrathin Ni1-xPtx silicide films, Appl. Phys. Lett., vol. 97, no. 25, p. 252108, Dec. 2010.
[89] X. Gao et al., Epitaxy of Ultrathin NiSi2 Films with Predetermined Thickness,
Electrochem. Solid-State Lett., vol. 14, no. 7, p. H268-H270, Jul. 2011.
[90] H. Muta, Electrical Properties of Platinum-Silicon Contact Annealed in an H2 Ambient,
Jpn. J. Appl. Phys., vol. 17, no. 6, pp. 1089-1098, 1978.
[91] M. Wittmer and T. E. Seidel, The redistribution of implanted dopants after metal-silicide
formation, J. Appl. Phys., vol. 49, no. 12, p. 5827, Dec. 1978.
[92] R. L. Thornton, Schottky-barrier elevation by ion implantation and implant segregation,
Electron. Lett, vol. 17, no. 14, pp. 485-486, Jul. 1981.
[93] A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, and J. Koga, Solution for high-
performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with
dopant segregation technique, in VLSI Tech. Dig., 2004, pp. 168-169.
References

75

[94] Z. Qiu, Z. Zhang, M. Ostling, and S.-L. Zhang, A Comparative Study of Two Different
Schemes to Dopant Segregation at NiSi/Si and PtSi/Si Interfaces for Schottky Barrier Height
Lowering, IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 396-403, 2008.
[95] G. Larrieu et al., Low Temperature Implementation of Dopant-Segregated Band-edge
Metallic S/D junctions in Thin-Body SOI p-MOSFETs, in IEDM Tech. Dig., 2007, pp. 147-
150.
[96] R. Doering and Y. Nishi, Handbook of Semiconductor Manufacturing Technology, 2nd ed.
CRC Press, 2007.
[97] Z. Zhang et al., Sharp Reduction of Contact Resistivities by Effective Schottky Barrier
Lowering With Silicides as Diffusion Sources, IEEE Electron Device Lett., vol. 31, no. 7,
pp. 731-733, Jul. 2010.
[98] X. Tang et al., Very low Schottky barrier to n-type silicon with PtEr-stack silicide, Solid-
State Electron., vol. 47, no. 11, pp. 2105-2111, Nov. 2003.
[99] N. Reckinger et al., Very low effective Schottky barrier height for erbium disilicide contacts
on n-Si through arsenic segregation, Appl. Phys. Lett., vol. 99, no. 1, p. 012110, Jul. 2011.
[100] E. Alptekin and M. C. Ozturk, NixPt1-xSi/n-Si contacts with sub-0.1eV effective Schottky
barrier heights obtained by sulfur segregation, Microelectron. Eng., Apr. 2010.
[101] M. Sinha, E. F. Chor, and Y. C. Yeo, Tuning the Schottky barrier height of nickel silicide on
p-silicon by aluminum segregation, Appl. Phys. Lett., vol. 92, no. 22, 2008.
[102] J. Luo, Z.-J. Qiu, D. W. Zhang, P.-E. Hellstrom, M. Ostling, and S.-L. Zhang, Effects of
Carbon on Schottky Barrier Heights of NiSi Modified by Dopant Segregation, IEEE
Electron Device Lett., vol. 30, no. 6, pp. 608-610, Jun. 2009.
[103] E. Alptekin and M. C. Ozturk, Tuning of the Nickel Silicide Schottky Barrier Height on p-
Type Silicon by Indium Implantation, IEEE Electron Device Lett., vol. 30, no. 12, pp. 1272-
1274, Dec. 2009.
[104] Q. T. Zhao, U. Breuer, E. Rije, S. Lenk, and S. Mantl, Tuning of NiSi/Si Schottky barrier
heights by sulfur segregation during Ni silicidation, Appl. Phys. Lett., vol. 86, no. 6, 2005.
[105] H. S. Wong, L. Chan, G. Samudra, and Y. C. Yeo, Low Schottky barrier height for silicides
on n-type Si (100) by interfacial selenium segregation during silicidation, Appl. Phys. Lett.,
vol. 93, no. 7, 2008.
[106] H.-S. Wong, F.-Y. Liu, K.-W. Ang, G. Samudra, and Y. C. Yeo, Novel Nickel Silicide
Contact Technology Using Selenium Segregation for SOI N-FETs With Silicon-Carbon
Source/Drain Stressors, IEEE Electron Device Lett., vol. 29, no. 8, pp. 841-844, 2008.
[107] W. Mizubayashi, S. Migita, Y. Morita, and H. Ota, Exact control of junction position and
Schottky barrier height in dopant-segregated epitaxial NiSi2 for high performance metal
source/drain MOSFETs, VLSI Tech. Dig., pp. 88-89, Jun. 2011.
[108] J. Luo et al., Thermal Stability and Dopant Segregation for Schottky Diodes With Ultrathin
Epitaxial NiSi2-y, IEEE Electron Device Lett., vol. 32, no. 8, pp. 1029-1031, Aug. 2011.
[109] E. Alptekin, M. C. Ozturk, and V. Misra, Tuning of the Platinum Silicide Schottky Barrier
Height on n-Type Silicon by Sulfur Segregation, IEEE Electron Device Lett., vol. 30, no. 4,
pp. 331-333, 2009.
[110] J. Luo, Z.-J. Qiu, Z. Zhang, M. stling, and S.-L. Zhang, Interaction of NiSi with dopants
for metallic source/drain applications, J. Vac. Sci. Technol., B, vol. 28, no. 1, p. C1|1-C1|11,
Jan. 2010.
[111] T. Yamauchi, Y. Nishi, Y. Tsuchiya, A. Kinoshita, J. Koga, and K. Kato, Novel doping
technology for a 1nm NiSi/Si junction with dipoles comforting Schottky (DCS) barrier, in
IEDM Tech. Dig., 2007, pp. 963-966.
[112] L. Geng, B. Magyari-Kope, and Y. Nishi, Image Charge and Dipole Combination Model for
the Schottky Barrier Tuning at the Dopant Segregated Metal/Semiconductor Interface, IEEE
Electron Device Lett., vol. 30, no. 9, pp. 963-965, Jul. 2009.
[113] D. K. Schroder, Semiconductor material and device characterization, 2nd ed. John Wiley &
Sons, 1998.
[114] E. Dubois and G. Larrieu, Measurement of low Schottky barrier heights applied to metallic
source/drain metal--oxide--semiconductor field effect transistors, J. Appl. Phys., vol. 96, no.
76

1, pp. 729-737, 2004.
[115] M. Tao, D. Udeshi, S. Agarwal, E. Maldonado, and W. P. Kirk, Negative Schottky barrier
between titanium and n-type Si(001) for low-resistance ohmic contacts, Solid-State
Electron., vol. 48, no. 2, pp. 335-338, Feb. 2004.
[116] J. Osvald, Comment on Negative Schottky barrier between titanium and n-type Si(001) for
low-resistance ohmic contacts, Solid-State Electron., vol. 48, no. 12, pp. 2347-2349, Dec.
2004.
[117] M. Tao and J. Zhu, Response to Comment on Negative Schottky barrier between titanium
and n-type Si(001) for low-resistance ohmic contacts [Solid State Electron. 2004;48:335-
8], Solid-State Electron., vol. 48, no. 12, pp. 2351-2352, Dec. 2004.
[118] W.-Y. Loh et al., Effective Modulation of Ni Silicide Schottky Barrier Height Using
Chlorine Ion Implantation and Segregation, IEEE Electron Device Lett., vol. 30, no. 11, pp.
1140-1142, Nov. 2009.
[119] D. Connelly and P. Clifton, Comments on Effective Modulation of Ni Silicide Schottky
Barrier Height Using Chlorine Ion Implantation and Segregation, IEEE Electron Device
Lett., vol. 31, no. 5, pp. 417-418, May 2010.
[120] Z. Zhang, Z. Qiu, R. Liu, M. Ostling, and S.-L. Zhang, Schottky-Barrier Height Tuning by
Means of Ion Implantation Into Preformed Silicide Films Followed by Drive-In Anneal,
IEEE Electron Device Lett., vol. 28, no. 7, pp. 565-568, 2007.
[121] R. Franks, Magnesium as a donor impurity in silicon, Solid State Commun., vol. 5, no. 6,
pp. 479-481, Jun. 1967.
[122] S.-M. Koh, Y. Ding, C. Guo, K.-C. Leong, G. S. Samudra, and Y.-C. Yeo, Novel tellurium
co-implantation and segregation for effective source/drain contact resistance reduction and
gate work function modulation in n-FinFETs, VLSI Tech. Dig., pp. 86-87, Jun. 2011.
[123] P. W. Lew and C. R. Helms, Effects of platinum silicide thickness and annealing
temperature on arsenic redistribution, J. Appl. Phys., vol. 56, no. 12, pp. 3418-3427, 1984.
[124] S. W. Jones, Diffusion in Silicon, 2000. [Online]. Available:
http://www.icknowledge.com/misc_technology/Diffusion.pdf.
[125] S. Solmi, M. Ferri, M. Bersani, D. Giubertoni, and V. Soncini, Transient enhanced diffusion
of arsenic in silicon, J. Appl. Phys., vol. 94, no. 8, p. 4950, Oct. 2003.
[126] J. Shannon, Control of Schottky barrier height using highly doped surface layers, Solid-
State Electron., vol. 19, no. 6, pp. 537-543, Jun. 1976.
[127] T. Sonehara et al., Contact resistance reduction of Pt-incorporated NiSi for continuous
CMOS scaling ~ Atomic level analysis of Pt/B/As distribution within silicide films ~, in
IEDM Tech. Dig., 2008, p. 921.
[128] G. Li, M.-K. Blanka, Z. Zhi-Yong, and N. Yoshio, Fermi Level Unpinning and Schottky
Barrier Modification by Ti, Sc and V Incorporation at NiSi2/Si Interface, Chin. Phys. Lett.,
vol. 26, no. 3, 2009.
[129] T. Yamauchi, A. Kinoshita, Y. Tsuchiya, J. Koga, and K. Kato, 1 nm NiSi/Si Junction
Design based on First-Principles Calculation for Ultimately Low Contact Resistance, in
IEDM Tech. Dig., 2006, p. 385.
[130] L. Geng, B. Magyari-Kope, Z. Zhang, and Y. Nishi, Ab Initio Modeling of Schottky-Barrier
Height Tuning by Yttrium at Nickel Silicide/Silicon Interface, IEEE Electron Device Lett.,
vol. 29, no. 7, pp. 746-749, 2008.
[131] W. Monch, On the physics of metal-semiconductor interfaces, Rep. Prog. Phys., vol. 53,
no. 3, pp. 221-278, 1990.
[132] F. Lau, L. Mader, C. Mazure, C. Werner, and M. Orlowski, A model for phosphorus
segregation at the silicon-silicon dioxide interface, Appl. Phys. A, vol. 49, no. 6, pp. 671-
675, Dec. 1989.
[133] J. Hoekstra and M. Kohyama, Ab initio calculations of the -SiC(001)/Al interface, Phys.
Rev. B, vol. 57, no. 4, pp. 2334-2341, 1998.
[134] M. Kohyama and J. Hoekstra, Ab initio calculations of the -SiC(001)/Ti interface, Phys.
Rev. B, vol. 61, no. 4, pp. 2672-2679, 2000.
[135] J. Chan et al., Extraction of correct Schottky barrier height of sulfur implanted NiSi/n-Si
References

77

junctions: Junction doping rather than barrier height lowering, Appl. Phys. Lett., vol. 99, no.
1, p. 012114, Jul. 2011.
[136] K. Asano, Y.-K. Choi, T.-J. King, and C. Hu, Patterning sub-30-nm MOSFET gate with i-
line lithography, IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 1004-1006, 2001.
[137] Y.-K. Choi, T.-J. King, and C. Hu, A spacer patterning technology for nanoscale CMOS,
IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 436-441, 2002.
[138] Y.-K. Choi et al., FinFET process refinements for improved mobility and gate work
function engineering, in IEDM Tech. Dig., 2002, pp. 259-262.
[139] J. Hallstedt et al., A robust spacer gate process for deca-nanometer high-frequency
MOSFETs, Microelectron. Eng., vol. 83, no. 3, pp. 434-439, Mar. 2006.
[140] B. G. Malm, M. Olyaei, and M. Ostling, Low-frequency noise in FinFETs with PtSi
Schottky-barrier source/drain contacts, in AIP Conference Proceedings - ICNF, 2011, pp.
135-138.
[141] J. G. J. Chern, P. Chang, R. F. Motta, and N. Godinho, A new method to determine
MOSFET channel length, IEEE Electron Device Lett., vol. 1, no. 9, pp. 170-173, Sep. 1980.
[142] E. Dubois et al., EU Network of Excellence, NANOSIL WP1, Deliverable D1.8:
Assessment and benchmarking of fabricated SB-MOSFET devices, 2011.
[143] M. Awano et al., Advanced DSS MOSFET technology for ultrahigh performance
applications, in VLSI Tech. Dig., 2008, pp. 24-25.
[144] M. Lundstrom, Fundamentals of Carrier Transport, 2nd ed. Cambridge: Cambridge
University Press, 2000.
[145] D. Querlioz et al., On the Ability of the Particle Monte Carlo Technique to Include
Quantum Effects in Nano-MOSFET Simulation, IEEE Trans. Electron Devices, vol. 54, no.
9, pp. 2232-2242, 2007.
[146] M. V. Fischetti, T. P. ORegan, and C. Sachs, Theoretical Study of Some Physical Aspects
of Electronic Transport in nMOSFETs at the 10-nm Gate-Length, IEEE Trans. Electron
Devices, vol. 54, no. 9, pp. 2116-2136, Sep. 2007.
[147] M. V. Fischetti and S. E. Laux, Monte Carlo study of electron transport in silicon inversion
layers, Phys. Rev. B, vol. 48, no. 4, pp. 2244-2274, 1993.
[148] L. Lucci, P. Palestri, D. Esseni, L. Bergagnini, and L. Selmi, Multisubband Monte Carlo
Study of Transport, Quantization, and Electron-Gas Degeneration in Ultrathin SOI n-
MOSFETs, IEEE Trans. Electron Devices, vol. 54, no. 5, pp. 1156-1164, May 2007.
[149] D. Esseni, P. Palestri, and L. Selmi, Nanoscale MOS Transistors: Semi-Classical Transport
and Applications, 1st ed. Cambridge: Cambridge University Press, 2011.
[150] B. Winstead and U. Ravaioli, Simulation of Schottky barrier MOSFETs with a coupled
quantum injection/Monte Carlo technique, IEEE Trans. Electron Devices, vol. 47, no. 6, pp.
1241-1246, 2000.
[151] L. Sun, X. Y. Liu, M. Liu, G. Du, and R. Q. Han, Monte Carlo simulation of Schottky
contact with direct tunnelling model, Semicond. Sci. Technol., vol. 18, no. 6, pp. 576-581,
2003.
[152] E. Pascual, R. Rengel, and M. J. Martin, Current drive in n-type Schottky Barrier
MOSFETs: a Monte Carlo study, in Spanish Conference on Electron Devices CDE, 2009,
pp. 108-111.
[153] W. Wang, H. Tsuchiya, and M. Ogawa, Enhancement of Carrier Ballistic Transport in
Schottky S/D MOSFETs, ECS Trans., vol. 19, no. 1, pp. 345-350, 2009.
[154] P. Palestri, L. Lucci, S. D. Tos, D. Esseni, and L. Selmi, An improved empirical approach to
introduce quantization effects in the transport direction in multi-subband Monte Carlo
simulations, Semicond. Sci. Technol., vol. 25, no. 5, May 2010.
[155] COP user manual. University of Udine.
[156] P. A. Serena, J. M. Soler, and N. Garcia, Self-consistent image potential in a metal surface,
Phys. Rev. B, vol. 34, no. 10, pp. 6767-6769, 1986.
[157] M. V. Fischetti, S. E. Laux, and E. Crabb, Understanding hot-electron transport in silicon
devices: Is there a shortcut?, J. Appl. Phys., vol. 78, no. 2, pp. 1058-1087, 1995.
[158] S. M. Sze, C. R. Crowell, and D. Kahng, Photoelectric Determination of the Image Force
78

Dielectric Constant For Hot Electrons in Schottky Barriers, J. Appl. Phys., vol. 35, no. 8, p.
2534, Aug. 1964.
[159] D. Ferry, Effective potentials and the onset of quantization in ultrasmall MOSFETs,
Superlattices Microstruct., vol. 28, no. 5-6, pp. 419-423, Nov. 2000.
[160] D. K. Ferry, R. Akis, and D. Vasileska, Quantum effects in MOSFETs: use of an effective
potential in 3D Monte Carlo simulation of ultra-short channel devices, in IEDM Tech. Dig.,
2002, pp. 287-290.
[161] J. Guo and M. S. Lundstrom, A computational study of thin-body, double-gate, Schottky
barrier MOSFETs, IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 1897-1902, 2002.
[162] M. Lundstrom and Z. Ren, Essential physics of carrier transport in nanoscale MOSFETs,
IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 133-141, Jan. 2002.

Fabrication, Characterization, and Modeling of Metallic Source/drain Mosfets

Încărcat de

Informații document

Titlu original

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

Fabrication, Characterization, and Modeling of Metallic Source/drain Mosfets

Încărcat de

Drepturi de autor:

Formate disponibile

Fabrication, characterization, and

modeling of metallic source/drain

Two dimensional Richardson constant

Conduction band energy

Valence band energy

Metal Fermi level

Semiconductor Fermi level

Length of the contact region

Effective channel length

Underlap between source metal and gate

Valley degeneracy for Richardson constant

Effective mass for Richardson constant

Effective density of states for conduction band

Donor doping concentration

Dynamic power dissipation

Static power dissipation

Series source/drain resistance

Channel resistance [/sq.]

Contact resistance in a MOSFET

MOSFET total resistance [-m]

Pinning factor using electronegativity

Pinning factor using work function

Silicon layer thickness

Gate insulator oxide thickness

Effective depletion width

Depletion width of the Schottky contact when used in SB-MOSFETs

Decrease in effective barrier height due to tunneling

Decrease in effective barrier height due to image force lowering

Optical dielectric constant

Schottky barrier height

Schottky barrier height to conduction band

Schottky barrier height to valence band

Charge neutrality level

Effective Schottky barrier height

Barrier predicted by Schottky-Mott theory

Long channel surface potential

is the effective Richardson mass, and

+ IFBL) is shown for a SB

is the metal work-function and

is the electron affinity of the semiconductor.

changes the barrier height changes

), that which is defined as the

, where A is a conversion factor [15], the quantity

is defined. A reasonable agreement to experimental results is

is the charge neutrality level of the semiconductor. If

=1, the relation given

is often small [16] and in

is changed, this effect is called Fermi-level

is 0.32 eV from the valence band [17] and the factor

of Si is pinned strongly and it is easier to obtain small p-type

) has been found to be

is decreased, and the Fermi-level pinning increased. Also, since E

, the Fermi level pinning decreases as E

is the number of interfacial bonds,

is the bond distance, and is the sum of

and C is fitted to the data. For B-P, Eq. 2.10 is plotted

, where D and F are fitted to the data. Using the

from model vs. the measured

is obtained [20],[23], a small SBH can be

values of 16 semiconductors from [15].

and doping concentration, when

on Si is relatively large, a large doping

. The contact resistivity is very sensitive to changes in N,