1048 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO.

5, MAY 2006
Overview and Status of Metal S/D Schottky-Barrier
MOSFET Technology
John M. Larson, Member, IEEE, and John P. Snyder, Member, IEEE
AbstractIn this paper, the metal source/drain (S/D) Schottky-
barrier (SB) MOSFET technology is reviewed. The technology
offers several benets that enable scaling to sub-30-nm gate
lengths including extremely low parasitic S/D resistance (1% of
the total device resistance), atomically abrupt junctions that en-
able the physical scaling of the device to sub-10-nm gate lengths,
superior control of OFF-state leakage current due to the in-
trinsic Schottky potential barrier, and elimination of parasitic
bipolar action. These and other benets accrue using a low-
thermal-budget CMOS manufacturing process requiring two
fewer masks than conventional bulk CMOS. The SB-CMOS man-
ufacturing process enables integration of critical new materials
such as high-k gate insulators and strained silicon substrates. SB
MOSFET technology state of the art is also reviewed, and shown
to be focused on barrier-height-lowering techniques that use in-
terfacial layers between the metal S/Ds and the channel region.
SB-PMOS devices tend to have superior performance compared to
NMOS, but NMOS performance has recently improved by using
ytterbium silicide or by using hybrid structures that incorporate
interfacial layers to lower the SB height.
Index TermsCMOSFETs, erbium silicide, metal source/drain
(S/D), platinum silicide, Schottky barriers (SBs), short-channel
MOSFET, transistors.
I. INTRODUCTION
T
HE INTERNATIONAL Technology Roadmap for Semi-
conductors (ITRS) states that the semiconductor in-
dustry has entered the era of material-limited device
scaling [1]. The building-block materials of the conventional
MOSFET devicesilicon, silicon dioxide, doped silicon, and
polysiliconhave been extended to their performance limita-
tions [1]. New materials, such as high-k gate insulators (to
replace SiO
2
gate insulators), strained-silicon substrates (to
replace Si substrates), metal gates (to replace polysilicon gates),
and metal source/drains (S/Ds) (to replace doped silicon S/Ds),
are therefore under development. This review provides a tech-
nology overview and status summary for metal S/D Schottky-
barrier (SB) MOSFET technology.
Metal S/D SB MOSFET devices replace S/D impurity dop-
ing with metal, typically silicide. There are numerous moti-
vations for replacing doping with metal in the S/D regions,
including low parasitic S/D resistance, low-temperature pro-
cessing for S/D formation, elimination of parasitic bipolar ac-
tion, and inherent physical scalability to sub-10-nm gate-length
Manuscript received June 30, 2005; revised November 21, 2005. The review
of this paper was arranged by Editor J. Welser.
The authors are with Spinnaker Semiconductor, Bloomington, MN 55425
USA (e-mail: john.larson@spinnakersemi.com).
Digital Object Identier 10.1109/TED.2006.871842
dimensions, which is due to the low resistance of metal and
the atomically abrupt junctions formed at the silicidesilicon
interface. An SBjunction forms at the interface of the metal S/D
and the semiconductor substrate. For this reason, a metal S/D
MOSFET device is commonly referred to as an SB MOSFET
(SB-MOS, SB-PMOS, SB-NMOS, or SB-CMOS).
Nishi rst proposed the idea of completely replacing doped
S/Ds with metal in 1966 when he submitted a Japanese patent
on the idea, which was later issued in 1970 [2]. In 1968,
Lepselter and Sze published the rst paper on the topic, fo-
cusing on a PMOS bulk device employing PtSi for the S/D
regions [3]. The PMOS device fabricated by Lepselter and Sze
was plagued by poor performance with room-temperature drive
current ten times lower than that of a conventional MOSFET.
The next publication appeared in 1981, when Koeneke showed
how the lateral gap between the edge of the S/D electrodes
and the gate electrodes strongly affects the drive current of
the device, with a smaller gap resulting in signicantly higher
performance [4], [5].
Later in the 1980s, a variety of SB-MOS device struc-
tures were studied, including the rst SB-NMOS device by
Mochizuki and Wise [6], devices employing interfacial dop-
ing layers between the metal S/D and the channel [5], [7],
[8] and asymmetric devices in which the source is metal
and the drain is doped silicon [9], [10]. Sugino et al. and
Swirhun et al. realized that SB-MOS can essentially eliminate
parasitic bipolar action, and demonstrated a CMOS structure
having an SB-PMOS device and conventional NMOS device,
which was immune to latchup [7], [11], [12]. The pre-1994
SB-MOS literature established proof of concept but at the same
time suffered from low performance due to device architecture
and process-technology issues.
Since 1994, when Tucker et al. [13], [14] and Snyder
[15] realized the advantages for device scaling of SB-MOS
technology, state-of-the-art SB-CMOS process technology has
signicantly advanced. This review will provide a technol-
ogy overview of the device physical architecture, fabrication
process, the basic principles of operation and the current state
of the art.
II. SB-MOS: DEVICE ARCHITECTURE
A cross section TEM of a short-channel SB-PMOS device
is shown in Fig. 1(a), while a schematic representation of an
SB-MOS device is shown in Fig. 1(b). The principal innovation
of SB-CMOS technology is in the engineering of the source
and drain electrodes. In its simplest form, the SB-MOS device
0018-9383/$20.00 2006 IEEE
LARSON AND SNYDER: OVERVIEW OF METAL S/D SB MOSFET TECHNOLOGY 1049
Fig. 1. (a) High-resolution cross-section TEM of a 22-nm SB-PMOS device
[21]. The S/D electrodes are formed completely of platinum silicide, while
a conventional MOS gate stack is used on a silicon semiconductor substrate.
(b) Schematic of an SB-MOS device illustrating several key parameters.
architecture entirely replaces conventional impurity-doped S/D
electrodes with metal, the metal typically being a metal silicide.
For the purposes of introduction, the embodiment of the device
illustrated by Fig. 1 will be considered.
A. SB-MOS: Metal S/D Features
Fig. 1(a) shows that the atomically abrupt metal silicide
source and drain electrodes extend laterally proximal to the
gate electrode, and may be overlapped with the gate. As shown
in Fig. 1(b), a few important physical parameters dene the
device. As with a doped S/D MOSFET device, the parameters
include the gate length (L
g
), effective channel length (L
ch
),
and the S/D junction depth (t
SD
). The sidewall thickness (t
SW
)
and the S/D overlap parameter (L
SD,OL
) are especially critical
in the design of an SB-MOS device. The location of the
peak concentration of a laterally uniform vertically nonuniform
retrograde channel implant (D
pd
) is also very important.
For an SB-MOS device, the S/D-to-substrate junction is
fundamentally different than that of a conventional MOSFET
device. At the S/D junction, doped S/D conventional MOSFET
devices form a p-n diode junction, whereas metal S/D SB-
MOS devices form an atomically abrupt SB junction having an
SB height
b
. An SB junction leads to fundamentally different
mechanisms for controlling current, which will be summarized
later in this review.
SB-CMOS circuits require complementary-performing SB-
NMOS and SB-PMOS devices. This is accomplished by either
using a mid-gap silicide or using complementary silicides. Mid-
gap silicides have an SBheight of approximately half the silicon
bandgap, while complementary silicides provide two different
complementary barrier heights. SB-MOS devices fabricated
using mid-gap silicides provide extremely poor saturation drive
current [16] and high subthreshold leakage current due to high
gate-induced drain leakage and junction leakage.
An optimized complementary silicide structure requires a
silicide for NMOS having a low barrier to electrons on
N-type silicon (
b,e
) and for PMOS, a low barrier to holes
on P-type silicon (
b,h
). Silicides such as platinum silicide
(PtSi) for SB-PMOS and a rare-earth silicide for SB-NMOS
such as erbium silicide (ErSi
x
) or ytterbium silicide (YbSi
x
)
provide the lowest known barrier heights to P- and N-type
silicon, respectively, with
b,h
for PtSi of 0.15-0.27eV [17],
[18] and
b,e
for the rare-earth silicides ErSi
x
and YbSi
x
of
0.27-0.36eV [19], [20]. One area of signicant interest is

b
engineering, which has been achieved by using a hybrid
structure that has an interfacial layer placed between the metal
and the semiconductor channel resulting in a reduced effective
barrier height. These hybrid devices, denoted as Schottky-
like devices, will be reviewed in more detail below.
One of the difcult challenges cited by the ITRS [1] is
parasitic S/D resistance. The ITRS predicts that starting in
2008, there is no known solution for the parasitic S/D resistance
challenge [1]. The metal silicide S/D architecture provides an
elegant solution to this problem, since metal-to-metal contacts
provide very low contact resistivity and the metal silicide
provides low sheet resistance. For example, we have measured
the contact resistivity of aluminum metallization on PtSi to be
1.6 10
9
cm
2
, and a 60-nm-thick PtSi sheet resistance to
be 6 /sq.
B. SB-MOS: Other Elements
Any semiconductor substrate can be used for SB-CMOS,
such as silicon, strained silicon, or silicon germanium. A con-
ventional MOS gate stack is used, including a gate insulator
with an effective oxide thickness (EOT), and a gate electrode
having a gate length L
g
. The device is fully compatible with
any gate insulator technology such as SiO
2
, nitrided oxides,
or high-k dielectrics and with standard polysilicon gates or
metal gates.
To control subthreshold leakage current, channel doping
concentration is reduced due to the built-in SB, which provides
a potential barrier that acts as a quasi-pocket or halo implant. In
addition to having a lower doping concentration in the channel,
a simpler doping prole can be used, such as a retrograde
implant that comprises a laterally uniform and vertically
nonuniform doping prole [21]. Halo or pocket implants are
eliminated from the structure and manufacturing process. De-
pending on the channel length, the retrograde channel im-
plant may have a peak dopant concentration of approximately
10
18
10
19
cm
3
located at a depth D
pd
of approximately
25100 nm below the gate insulator [21]. In the region 010 nm
below the gate insulator, where a majority of the mobile charge
ows from source to drain, the SB-MOS dopant concentra-
tion is 10
16
10
17
cm
3
, or approximately 90%99% lower
compared to a doped S/D device. Reduced channel doping
provides improved effective carrier mobility. Alternatively,
silicon-on-insulator (SOI) substrates or multigate structures
1050 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
may be used to assist in controlling subthreshold leakage
[22], [23].
A thin sidewall spacer helps minimize S/D-to-gate underlap
so that the SB junctions to the channel region are in close
proximity to the gate electrode. The thickness of the sidewall
spacer (t
SW
) should be less than about 10 nm. The S/D overlap
parameter L
SD,OL
is the lateral distance from the S/D edge
to the edge of the gate electrode. When a lateral gap exists
between the S/D edge and the gate edge, the S/D are said to
have gate underlap (L
SD,OL
< 0). If no lateral gap is formed
and the S/D-to-channel junction is located beneath the gate
electrode, the S/D are said to have gate overlap (L
SD,OL
> 0).
The optimum value for L
SD,OL
is determined by minimizing
the capacitance due to junction proximity to the gate [24],
minimizing the parasitic junction resistance induced by un-
derlap, and minimizing the gate-induced drain-leakage current
(I
GIDL
). Although the above description of SB-MOS device
architecture focuses on a bulk substrate version, many other
SB-MOS architectures have been demonstrated, including SOI
[16], [17], [22], [25][33], FinFET [23], and Schottky-like
devices with interfacial layers [23], [30], [31], and [34][36].
III. SB-MOS: PROCESS FLOW
The manufacturing process for SB-CMOS is simpler than
conventional bulk CMOS, requiring fewer process and pho-
tolithography steps. The process is fully compatible with ex-
isting silicon CMOS factories and does not require novel
process equipment. The manufacturing process begins with a
standard isolation process such as STI or LOCOS. Standard
well implants and channel implants are provided next. Then,
a dual-doped polysilicon or metal-gate process is provided.
Standard lithography and etch technologies are used to form
the gate ne lines. A thin (< 10 nm) sidewall spacer is formed
on the gate and an anisotropic sidewall spacer etch exposes
the active regions. Pocket or halo implants are not needed
to control short-channel effects. The built-in SB at the metal
source and drain channel interface, which is augmented by
laterally uniform channel implants, effectively controls short-
channel effects. S/D extension and deep contact implants are
also eliminated.
When complementary silicides are used, a dual-silicide
exclusion-mask process is used to form the S/D regions of
the NMOS and PMOS devices. The silicide exclusion mask is
typically composed of an oxide hard mask. For example, after
deposition of an oxide layer, the oxide hard mask is patterned
and etched so that the S/D regions of the PMOS devices are
exposed and a self-aligned PtSi process used to form PtSi S/Ds
of the PMOS devices. Then, the S/D regions of the NMOS
devices are similarly exposed and a self-aligned ErSi process
used to form the ErSi S/D regions of the NMOS devices. The
platinum and erbium are provided by standard physical vapor
deposition (PVD) process equipment. The junction depth and
lateral silicide growth is determined by the amount of material
deposited. Because the effective gate length L
e
is determined
by the extent of lateral silicide growth, it is important that the
uniformity of deposited material be at least 5%across the wafer,
which is achievable in modern PVD production tools. For these
particular silicides, the maximum anneal temperature required
for the silicide reaction is less than 600

C. Finally, back-end
metallization is provided using conventional techniques.
There are many variations of this basic ow and device ar-
chitecture, most of which engineer the S/D structure differently
by introducing an interfacial layer of doping or a thin insulator
between the metal S/D and the channel region to lower the
effective SB height. Examples of process steps used to provide
these interfacial layers include the implant-to-silicide process
[37], dopant segregation [35], [36], and thin interfacial insulator
layers [38]. These and other techniques will be discussed in
more detail when the state of the art is reviewed below. If
the SB height is sufciently lowered, then halo implants, SOI
substrates, or FinFET structures will be needed to control short-
channel effects.
The dual-silicide exclusion-mask process requires some ad-
justment from a conventional bulk CMOS ow. In one version
of this process, a silicide exclusion mask is provided and
patterned such that the PMOS active regions are exposed.
After cleaning, an HF clean removes the native oxide, and
the wafers are immediately loaded for platinum deposition.
A standard sputter-deposition tool can be used for platinum
deposition to thicknesses of 1050 nm. A 500-

C 1-h furnace
anneal forms the PtSi. Then, the unreacted Platinum not in
contact with silicon is removed by an aqua regia wet strip.
The process is then repeated for the ErSi self-aligned silicide
module. Following the formation of a second silicide exclusion-
mask layer and Erbium deposition, ErSi
x
is formed by either
a furnace anneal at approximately 400

C for about 1 h or a
higher temperature (500

C) shorter anneal time (510 min)
RTA process. Sulfuric peroxide is used to remove the unreacted
erbium and then the second oxide hard mask is removed. This
dual-silicide exclusion-mask process requires only two masks
compared to four for a typical doped S/D CMOS process.
There are signicant process advantages with SB-CMOS
technology. For example, following the formation of the gate
stack, the maximum process temperature is less than 600

C.
S/D extension and deep ion-implantation steps are eliminated
as are the high-temperature 1000-

C spike or ash anneals

required to activate the S/D dopants. These steps are replaced
with the dual-silicide exclusion-mask process described above,
which has a maximum temperature less than 600

C. This is
a very important advantage as it enables integration of other
new critical material systems into CMOS process ows, such
as high-k gate insulators, metal gates, and strained silicon.
The properties of these new materials tend to degrade upon
high-temperature annealing typical of doped S/D technology,
but are more stable when using a thermal budget less than
600

C [34]. Furthermore, because ion-implantation steps for
S/D formation are eliminated, strained substrates are not dam-
aged by high-dose or high-energy implants, thereby minimizing
substrate damage and degradation of charge carrier-mobility
improvement in the strained channel region. The process equip-
ment required for ion implantation of the S/D and spike/ash
annealing is also eliminated and replaced with relatively simple
sputter-deposition and anneal tools. Finally, statistical variation
endemic to doped S/D architectures is virtually eliminated by
the use of well-controlled metal silicides. Random statistical
LARSON AND SNYDER: OVERVIEW OF METAL S/D SB MOSFET TECHNOLOGY 1051
Fig. 2. Qualitative surface (S) and subsurface (SS) band diagrams. (a) SB-PMOS device. (b) Conventional impurity-doped S/D PMOS device.
variations in the positioning of the S/D contacts to the channel
region due to dopant diffusion effects are eliminated.
IV. SB-MOS: PRINCIPLES OF OPERATION
Although metal S/D SB-CMOS technology is similar to
doped S/D conventional CMOS technology in many respects,
there are differences in the fundamental principles of operation.
These differences are traceable to the different nature of the
junction between the S/D regions and the semiconductor sub-
strate, which is an SB diode contact for SB-MOS technology.
The basic operating principles of an SB-PMOS device with
a nite SB for hole emission to the valence band are illustrated
in Fig. 2 and are compared to a conventional PMOS device.
Surface and subsurface band diagrams are shown in the OFF
state and a surface band diagram is shown in the ON state.
Fig. 2(a) shows that the SB-PMOS device Fermi levels for the
source and drain silicide are attached to the silicon band gap
close to the valence band in the OFF and ON states in the
top and bottom band diagrams, respectively. The resulting SB is
0.23 eV to holes and 0.87 eV to electrons if PtSi is used
for the metal region. If barrier-height engineering is used to
lower the effective barrier height, the band structure will be
modied due to the presence of high P+ dopant concentration
near the source or thin interfacial layers between the source and
the channel regions. Fig. 2(b) shows that the band diagrams for
SB-PMOS and conventional PMOS devices are quite similar
except at the source and drain regions, where the metal silicide
Fermi level is replaced by the silicon bands in conventional
PMOS and the SB-PMOS bands have a built-in Schottky po-
tential barrier
b
at the S/D junction to the channel. The band
diagrams for an SB-NMOS device are the mirror image of those
shown in Fig. 2.
For the SB-PMOS device, the emitted current density at the
source (J
s
) is the sum of the current emission over the barrier
(the thermal emission J
th
) and current emission through the
barrier (thermionic eld emission and eld-emission current).
For the sake of this review, thermionic eld emission and eld-
emission current will be lumped into one component of current,
denoted as the eld-emission current J
fe
. The thermal-emission
current can be determined by classical thermal-emission
theory [39]:
J
th
= A

T
2
e

b
kT

e
qV
kT
1

(1)
where A

is the Richardson constant, T is temperature, and

V is the applied bias. The tunneling eld-emission current is
a much more complicated calculation and will be discussed
further below.
When a low electric eld (E-eld) is present at the source
electrode, there is virtually no eld-emission current and the
total current J
s
equals J
th
. However, as the E-eld increases
at the source, J
fe
increases rapidly, while J
th
remains approx-
imately constant. When the gate is biased in the ON state,
and a large E-eld is present at the source tip below the
gate electrode (e.g., 300 MV/cm), J
s
is dominated by eld-
emission current. For this reason, an SB-MOS transistor is often
referred to as a eld-emission device in the ON state. With this
background, both the ON- and OFF-state operational regimes
will be discussed in greater detail.
A. Subthreshold Leakage Current (I
OFF
)
As with any MOSFET technology, SB-MOS subthresh-
old leakage current is typically dominated by three compo-
nents (not including gate insulator leakage): 1) gate-induced
drain-leakage current (I
GIDL
); 2) junction leakage (I
j
); and
3) S/D thermal-emission leakage current (I
th
):
I
OFF
= I
GIDL
+I
j
+I
th
. (2)
1052 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
Fig. 2(a) illustrates the band diagram in the OFF state for
an SB-PMOS device, with the drain biased at V
ds
= V
dd
and
V
gs
= 0. For PMOS, I
GIDL
is caused by the tunneling of
electrons through the relatively large but thin barrier at the drain
side in the OFF state, which is a result of the close proximity of
the drain to the gate. For SB-PMOS, the SB to electrons (
b,e
)
is the difference between the silicon band gap (E
g
) and the
barrier height to holes (
b,h
)

b,e
E
g

b,h
. (3)
The amount of electron (PMOS) or hole (NMOS) tunneling
current causing I
GIDL
is strongly sensitive to the barrier height

b,e
or
b,h
, respectively. Semiconductor substrates with lower
band gaps E
g
such as germanium will suffer from signicantly
increased I
GIDL
[40]. I
GIDL
is also highly sensitive to the
barrier width, which is controlled by the E-eld (E
D
) and
potential prole at the drain. Parameters such as L
SD,OL
, EOT,
and V
d
determine E
D
and the potential prole, which in turn
determines the barrier thickness, the tunneling current through
the barrier, and I
GIDL
.
Previously fabricated SB-PMOS devices [21] of various gate
lengths were used to investigate I
GIDL
. Briey, a blanket As
implant was provided to the active area to reduce subthreshold
leakage current. The gate stack consisted of 100-nm-thick
in situ phosphorus-doped amorphous silicon on an 18- gate
oxide. The use of an n-type gate material produces a 1.1-V
threshold voltage shift, which is accounted for by applying
an additional 1.1 V to the gate. The gate oxide is relatively
thick for the gate lengths produced, which means an added
gate voltage must be applied in order to achieve a reasonable
electric eld in the oxide (E
ox
). The additional gate voltage
was determined by using a detailed MOS capacitor-simulation
software that accounted for the n-type polysilicon gate, the
relatively thick gate oxide of 18 , polysilicon depletion and
inversion-layer quantization effects, and which resulted in an
E
ox
appropriate for the device gate length such as 67 MV/cm.
Gate lithography was performed using a 248-nm stepper with a
double-exposure phase-shift mask approach [41]. A sub-10-nm
sidewall spacer was provided by a thermally grown oxide.
Finally, PtSi S/D electrodes were formed using an evaporation
process to deposit the platinum and a furnace anneal of 550

C
for 60 min. Fig. 3 illustrates measured subthreshold data for
various bias conditions, gate lengths, and channel doping. The
I
GIDL
is 0.01300 pA/m, depending on the doping and
bias conditions, and is relatively independent of gate length.
Junction leakage current (I
j
) for an SB-MOS device is
caused by the reverse-biased Schottky diode at the drain elec-
trode. For example, for a PMOS device with PtSi drain contacts
on an N-type well, at V
d
= 1.0 V, the PtSi/N-type well
contact is a reverse-biased SB diode. Fig. 4 shows the Schottky
diode curves for PtSi and ErSi
x
on lightly doped (10
15
cm
3
)
N- and P-type substrates, respectively. The PtSi and ErSi
x
SB diodes provide I
j
of 2.6 and 38.6 fA/m
2
, respectively.
For a typical layout of a 65-nm node transistor, the length
of the drain is approximately 195 nm, which results in an I
j
of 0.4 and 6 fA/m at |V
d
= 1.0 V|, for PtSi and ErSi
x
,
respectively.
Fig. 3. Examples of SB-PMOS I
GIDL
leakage current for various gate-length
devices (25 nm, 60 nm, 80 nm, and 1 m) for a drain bias of 1.0 V. V

g
is V
g
minus 1.1 V. I
GIDL
is estimated by extrapolating the slope of the I
d
V
g
curve
from the subthreshold data. The portion of the I
d
V
g
curve that is nearly at
is due to the junction leakage current. The inset shows the effect of the channel
implant and V
d
on I
GIDL
(indicated range covers all four gate lengths).
Fig. 4. Diode curves for ErSi
x
and PtSi diodes formed on a P- and N-type
substrates, respectively.
However, when the substrate is more heavily doped, the
reverse leakage current of PtSi and ErSi
x
diodes increases. For
a modestly doped device, with a peak doping concentration
of 10
18
cm
3
at a depth of 50 nm, and 50-nm-deep S/D
junctions, the SB diode reverse leakage increased to 500 and
2 pA/m
2
at |V
d
| = 1.0 V, resulting in an I
j
of 100 and
0.4 pA/m for PtSi and ErSi
x
, respectively. The PtSi junction
leakage could be signicantly reduced by optimizing the dopant
prole and PtSi depth, or by using an SOI structure.
The most signicant contribution to subthreshold leakage
current for SB-CMOS technology is source-to-drain thermal-
emission leakage current (I
th
). This is clearly shown by Fig. 3
for the 25-, 60-, and 80-nm SB-PMOS devices. Due to the
presence of
b
, SB-MOS devices have an intrinsic advantage
in controlling I
th
because
b
plays the roll of a pocket or halo
LARSON AND SNYDER: OVERVIEW OF METAL S/D SB MOSFET TECHNOLOGY 1053
Fig. 5. I
d
V
g
transistor curves of a 25-nm SB-PMOS transistor having no
channel implant. The applied gate voltage V
g
is the indicated gate voltage V

g
minus 1.1 V.
implant, without having to add any dopants to the channel
region. Unimplanted 25-nm-gate-length SB-PMOS devices il-
lustrate the effectiveness of the SB control of thermal-emission
leakage current. Devices were fabricated using the same
process as those shown in Fig. 3, but no channel implant
was provided. Fig. 5 provides I
d
V
g
curves for this unim-
planted 25-nm-gate-length device, which shows that I
ON
is
629 A/m, I
OFF
is 6140 nA/m, and the ONOFF current
ratio is 102. An ONOFF ratio of 100 is remarkable considering
the device gate length and the fact that the channel is only
lightly doped (10
15
cm
3
).
For practical applications of SB-MOS technology, much
lower subthreshold leakage current is required. This is achieved
by augmenting the SB with a modest channel implant hav-
ing a vertically nonuniform but laterally uniform doping pro-
le, such as that used for the devices shown in Fig. 3. The
25-nm device in Fig. 3, which is identical to the device in
Fig. 5 except for the modest channel implant, has an I
ON
of
460 A/m and I
OFF
of 168 nA/m, for an ONOFF current
ratio of 2700. Compared to the undoped device, I
OFF
decreased
by 97% while I
ON
only decreased by 27%. This illustrates the
good control of thermal-emission leakage current provided by
a relatively low-concentration simple channel doping prole
and process.
The surface doping concentration near the gate insulator was
estimated to be 2 10
16
cm
3
from simulation of the implant
process. It is important to note that no high-dose halo or pocket
implant was used for these devices. As a result, we estimate that
the doping concentration within 10 nm of the gate insulator is
90%99% lower for SB-MOS devices having
b
of 0.25 eV,
compared to conventional doped S/D devices having a halo
channel implant. Lower channel doping provides a number
of benets, including signicantly reduced junction and gate
capacitance, thereby enhancing the frequency response of
the device, which improves device performance [21]. Fully
depleted SOI technology provides another means to improve
the source-to-drain thermal-emission leakage current [22].
B. ON-State Drive Current (I
ON
)
When a strong electric eld is present at the source elec-
trode, virtually all of the source-emitted current is due to eld
emission of carriers that tunnel through the SB. As the channel
charge increases, the E-eld at the source tip reduces due
to charge screening effects, which reduces the eld-emitted
current, until equilibrium is achieved. The physics and mod-
els required to understand the ON-state drive current of an
SB-MOS device are fundamentally different than those used
in a doped S/D conventional MOSFET device. Furthermore,
at this time, simple analytical expressions describing the
currentvoltage relationships of an SB-MOS device over a
broad range of bias conditions and device physical parameters
are not available. In order to predict the ON-state performance
of an SB-MOS device, one must model the eld-emission
current from the source by computational means.
At least four approaches have been reported for estimating
the eld-emission tunneling current J
fe
through the source-
side sharp triangular Schottky potential barrier, which is shown
in the ON-state band diagram in Fig. 2(a). These approaches
include: 1) analytical expressions for J
fe
combined with t-
ting parameters; 2) numerical integration techniques using the
WenzelKramersBrillouin (WKB) approximation for model-
ing tunneling probabilities; 3) numerical integration techniques
using the exact Airy function for modeling tunneling prob-
abilities, assuming a sharp triangular potential barrier; and
4) numerical integration techniques using the exact Airy func-
tion for modeling tunneling probabilities, assuming an arbitrary
barrier shape. The simplest of these analytical expressions
was used by Hattori and co-workers [42], [43] and Padovani
and Stratton [44]. However, J
fe
calculated by more accurate
techniques can be several orders of magnitude different then the
analytical expressions, especially at high electric elds [15].
More accurate calculations of J
fe
, such as those listed in
cases 2)4), involve detailed analysis of the carrier velocity
distribution, density of states, Fermi function, and tunneling
probability for carriers that tunnel from the metal into the
semiconductor through the sharp triangular SB at the source
tip. Regarding the calculation of the tunneling probability, one
approach uses the WKB approximation, which is a relatively
simple expression for the tunneling probability that can be
numerically integrated over a range of carrier energies [45].
Unfortunately, this approach may suffer in accuracy for the
conditions of SB-MOS technology [15], [46].
The most accurate technique for calculating the critical tun-
neling probability over a broad range of device structures and
bias conditions uses Airy functions together with assumptions
about the nature of the potential distribution near the SB con-
tact. Specically, either a sharp triangular barrier [case 3)] or
an arbitrary barrier [case 4)] are assumed [47]. An example of
J
fe
versus E-eld for several barrier heights and a broad range
of electric elds is provided by Winstead and Ravaioli [47] and
shows that J
fe
varies by four to ve orders of magnitude for
E-elds ranging from 5 10
4
to 5 10
6
V/cm, the range of
electric elds typically observed at the source of an SB-MOS
device. This result explains the sensitivity of the ON-state
SB-MOS performance to the E-eld generated at the source
1054 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
of the device. Furthermore, the strong sensitivity of J
fe
to the
barrier height
b
is clearly shown by Winstead and Ravaioli
[47]. For an electric eld of 3 10
6
V/cm, J
fe
decreases
by a factor of 20 as the barrier height
b
increases from
0.13 to 0.39 eV. Generally, in order to maximize the eld-
emission current in the ON-state, the barrier height
b
should be
low (sub-0.3-eV) and the E-eld at the source tip should be high
(greater than 10
6
V/cm). Finally, Winstead further demonstrates
that a full-band Monte Carlo device simulator coupled to an
Airy-function tunneling model reproduces the measured data
with reasonable accuracy [47].
We provide in Fig. 6 additional dc transistor data for
25-, 60-, and 80-nm-gate-length bulk SB-PMOS devices with
a nite barrier height of 0.27 eV and no interfacial layer
between the PtSi S/D contacts to the channel region. They
were fabricated using the same process as previously described
above. The ON-state V

g
was set to provide an appropriate E
ox
for each gate-length device, based on detailed MOS capacitor
simulations described above. For example, applying a V

g
of
1.8 V to an N
+
polysilicon gate on a 1.8-nm gate oxide results
in an E
ox
of 7 MV/cm, which is the same E
ox
achieved by ap-
plying 1.1 V to a metal gate on a 0.9-nm EOT gate insulator,
the metal gate having a work function similar to P
+
polysil-
icon. Table I summarizes the I
ON
and I
OFF
performance of
these devices and compares them to ITRS specications [48]
[50]. These SB-PMOS devices provide total OFF-state leakage
current of 168, 11.9, and 6 nA/m, ON-state current of 460,
311, and 300 A/m, and I
ON
/I
OFF
ratio of 2700, 26 000,
and 50 000 for the 25-, 60-, and 80-nm devices, respectively.
An upward-sloping sublinear turn-on characteristic is com-
monly observed in SB-MOS I
d
V
d
curves [21]. It is not known
yet how this characteristic will affect the digital frequency
response of SB-CMOS technology. It is an artifact of the current
emission process, which depends on high E-elds at the source,
and is not indicative of a high parasitic resistance external to the
channel region. In fact, for the devices shown in Fig. 6, the total
external parasitic resistance is 1% of the total device resistance.
Further, as noted by others, the effect of the sublinear charac-
teristic on ac response may be offset by reduced transit times
due to source-side hot carriers having high initial velocities
caused by the strong electric eld at the metal source [51], [52].
The devices also have a two-slope subthreshold I
d
V
g
charac-
teristic, as shown by Fig. 6. The initial slope is due to thermal
emission while the second slope is due to the eld-emission
tunneling mechanism. The changing subthreshold slope is not
a signature of the short-channel effect, but instead is caused by
the different SB-MOS current control mechanisms [46].
C. Parasitic Bipolar Gain Eliminated
Latchup and other reliability problems such as soft errors
or single-event upsets are highly sensitive to the source-side
bipolar emitter efciency. For a doped S/D device, the source
junction is a good emitter, while a rectifying SB junc-
tion is generally a poor minority-carrier injector [12]. The
commonemitter current gain of an SB junction has been
shown previously to be three to six orders of magnitude lower
than that of a conventional source junction, virtually eliminat-
Fig. 6. SB-PMOS I
d
V
g
and transconductance curves for gate lengths of
(a) 80; (b) 60; and (c) 25 nm. The devices have a channel implant, 1.8-nm
gate oxide, and N
+
polysilicon gates, causing a 1.1-V shift in the thresh-
old voltage. The applied gate voltage V
g
is the indicated gate voltage V

g
minus 1.1 V.
ing the parasitic bipolar effect [53]. Reducing and eliminating
parasitic bipolar action leads directly to a natural and uncondi-
tional immunity to latchup and single transistor latch regardless
of substrate type and doping, V
dd
, and layout. Further, other
deleterious effects traceable to the parasitic bipolar effect will
be eliminated or signicantly reduced, such as multicell and
LARSON AND SNYDER: OVERVIEW OF METAL S/D SB MOSFET TECHNOLOGY 1055
TABLE I
COMPARISON OF ITRS PMOS HIGH-PERFORMANCE LOGIC
SPECIFICATIONS WITH THE PERFORMANCE DEMONSTRATED FOR
SB-PMOS TECHNOLOGY. THE GATE VOLTAGE OF THE SB-PMOS DEVICES
FROM THIS PAPER IS SCALED SUCH THAT THE ELECTRIC FIELD IN THE
OXIDE (E
ox
) IS APPROXIMATELY EQUIVALENT TO THAT PROVIDED
BY THE ITRS SPECIFICATIONS. THE 25-nm DEVICE BIAS
CONDITIONS PROVIDES A 7.0-MV/cm E
ox
WHILE THE
60- AND 80-nm DEVICES HAVE A 6.7-MV/cm E
ox
single-cell soft-error rates. Unconditional latchup immunity
and substantially reduced soft-error rates improve circuit re-
liability for both memory and logic applications, especially
as device geometries scale into the sub-50-nm and sub-
1.2-V V
dd
regimes. This is a signicant technology advantage
for highly scaled CMOS, which is becoming increasingly sen-
sitive to parasitic bipolar action and soft errors for both memory
and logic devices [54], [55].
V. SB-MOS: STATE OF THE ART
The SB-MOS device-fabrication literature covers a number
of topics including, for example, the proof-of-concept demon-
stration of various SB-MOS device architectures, SB height
engineering, and integration of new silicides, such as ErSi
x
and
YbSi
x
, into MOSFET device-fabrication process ows. Table II
provides examples of the state-of-the-art for SB-MOS literature
for devices having gate lengths less than 250 nm. In 1999,
Wang et al. demonstrated a bulk 27-nm-channel-length PtSi
SB-PMOS device, with a drive current of 350 A/m, which
initially set the standard for drive-current performance for
highly scaled SB-MOS technology [56]. In 2000, Kedzierski
and co-workers demonstrated sub-25-nm SOI SB-PMOS and
SB-NMOS devices [16], [22], and [57]. OFF-state performance
of the PtSi SB-PMOS and ErSi
x
SB-NMOS devices was sig-
nicantly improved by using an SOI substrate. For example,
I
ON
of 270 and 190 A/m were reported for PMOS and
NMOS, respectively. I
OFF
was 0.54 and 19 nA/m, resulting
in I
ON
/I
OFF
current ratios of 5 10
5
and 10
4
for PMOS and
NMOS, respectively.
In 2004, we reported SB-PMOS high-performance 280-GHz
cutoff frequency (f
T
) data for sub-30-nm devices [21]. This
was the best f
T
reported for any silicon MOS transistors, in-
cluding conventional NMOS. We have reported here additional
dc data for 25-, 60-, and 80-nm-gate-length devices, which, to
our knowledge, represents the state of the art for dc I
ON
, I
OFF
,
and G
m
SB-PMOS performance.
A majority of the SB-MOS short-channel literature has
employed a silicide S/D architecture on either bulk or SOI
substrate without using interfacial layers. One exception is the
FinFET device presented by Tsui and Lin [23]. Tsui reports
a metal S/D device that has an interfacial layer placed be-
tween the metal S/D and the channel region provided by an
implant-to-silicide technique. Tsui reports a drive current of
250 A/m and an ONOFF current ratio of 10
9
, although a
10
9
ONOFF current ratio may be difcult to achieve with a
reasonable threshold voltage and drive current.
Kinoshita et al. disclosed a high-performance 50-nm-gate-
length SB-NMOS device using an approximately 10-nm-thick
interfacial dopant layer between the source and drain [35], [36].
The interfacial dopant layer is formed by a dopant-segregation
effect. The device had a 25- gate oxide and was operated with
a V
dd
of 2.0 V. The drive current of the device is reported to be
1670 A/m at an OFF-state leakage current of 100 nA/m,
which is approximately 20% greater than conventional NMOS
devices fabricated by the same process. Although this qual-
ies as a Schottky-like device versus a pure SB-NMOS de-
vice with no interfacial layer, the SB-NMOS performance of
this Schottky-like device sets the performance standard for
SB-NMOS technology, even though a relatively high V
dd
is
used. A rst-ever sub-100-nm Schottky-like SB-CMOS ring
oscillator was fabricated. Agate delay of approximately 30 ps is
extracted from the reported data. Scaling the EOT of this device
will signicantly improve the ring-oscillator performance.
Other research groups have used interfacial layers, includ-
ing Nishisaka et al. and Matsumoto et al. who formed a
doped S/D extension between the metal and channel re-
gion [30], [31]. However, this extension was laterally 80-nm
long, meaning the device is not a Schottky-like device. Ultrathin
interfacial insulator layers have also been used for the purpose
of passivating the interface between the metal and semiconduc-
tor, which reduces the effective barrier height [38], [58], and
[59]. However, to date, no data have been provided in which
a thin interfacial insulating layer is successfully integrated into
an SB-MOS device, perhaps due to integration challenges.
In 2004, Zhu et al. reported using several silicides for the
SB-NMOS S/D formation, including ErSi
x
, DySi
x
, and YbSi
x
,
with YbSi
x
reported to have a barrier height of 0.27 eV [19].
This is better than the typically reported 0.28-eV barrier for
ErSi
x
, and Zhu further reported that ytterbium provided a
smoother YbSi/Si interface and was not as sensitive to oxygen
as erbium, providing improved manufacturability. YbSi pro-
vided a 240% improvement in SB-NMOS I
ON
performance
and the I
ON
I
OFF
ratio improved by two to three orders of
magnitude for a 4-m-gate-length device. Ytterbium silicide
may be a preferred material system for implementing an all-
metal SB-NMOS technology.
There is some debate about the optimal SB height needed
for competitive SB-CMOS technology. Some have claimed a
zero or even negative barrier height is required for acceptable
performance [60], while other results suggest that very high
1056 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
TABLE II
SUMMARY OF SUB-250-nm-GATE-LENGTH SB-NMOS AND SB-PMOS LITERATURE. THE COLUMN LABELED TECHNOLOGY HAS A
COMMA-SEPARATED LIST FOR EACH ROW WITH THE FORMAT TYPE, STR, SIL, SDENG. TYPE IS THE DEVICE TYPE (N = NMOS, P = PMOS). STR IS
THE DEVICE STRUCTURE (B = BULK, S = SOI, F = FinFET). SIL IS THE SILICIDE TYPE FOR THE SOURCE AND DRAIN (SELF EXPLANATORY).
SDENG IS THE S/D ENGINEERING TYPE (1 = STANDARD, 2 = INTERFACIAL LAYER)
performance can be achieved with devices having a sub-0.3-eV
barrier height [21]. The recent focus on barrier-height low-
ering techniques is driven by the belief that very low barri-
ers are needed to make SB-MOS performance acceptable for
commercial application, and that the leading silicide material
candidates for SB-NMOS tend to have higher barrier heights of
0.270.36 eV. Recently, this issue was addressed by simulation
studies that suggest a nite positive barrier of 0.060.1 eV
is needed for SB-PMOS and SB-NMOS to make SB-CMOS
technology speed performance competitive with doped S/D
technology [24], [61]. Experimental SB-CMOS circuit demon-
strations in silicon will be needed to resolve the optimal SB
height for SB-CMOS technology.
VI. CONCLUSION
The principle feature of SB-CMOS technology is metal
S/Ds. Metal S/Ds are inherently lower resistance and atomi-
cally abrupt, providing a long-term scalability advantage. The
metal S/D junction to the channel forms a SB, which pro-
vides improved I
OFF
leakage control. It further enables lower
doping in the channel region, which results in higher channel
mobility. Fewer implants, reduced implant doses, and dramat-
ically lower S/D temperature of formation (< 600

C) cause
less damage to mobility-enhancing materials in the channel
region such as strained Si, thereby further improving mobil-
ity. SB junctions also eliminate parasitic bipolar action and
latchup, and are much less sensitive to radiation effects that
induce soft errors. There are no shallow S/D formation im-
plants and high-temperature activation anneals, which provide
several benets including a simpler, lower mask count lower
cost manufacturing process, and lower temperature S/D for-
mation process. A low-thermal-budget process enables integra-
tion of performance-enhancing materials such as high-k gate
dielectrics, metal gates, and strained silicon, all of which lead
to other substantial advantages such as reduced gate leakage,
lower power, and higher effective carrier mobility. Together,
these features and benets make SB-CMOS technology a wor-
thy candidate for scaling to sub-25-nm gate lengths.
The development of SB-MOS technology has advanced sig-
nicantly in the past ten years. High-performance SB-PMOS
devices with a PtSi S/D architecture and 25-, 60-, and 80-nm-
gate-length have been demonstrated. The ON current and
OFF currents of these devices do not yet meet the ITRS
requirements, but extremely high cutoff frequency (f
T
) has
been measured to be 280 GHz. SB-NMOS devices fab-
ricated using thin dopant-segregation junctions provide the
highest reported SB-NMOS performance, and were shown
to have superior performance to otherwise identical conven-
tional NMOS devices. For pure metal S/D SB-NMOS de-
vices, YbSi
x
has been identied as an alternative to ErSi
x
for
SB-NMOS technology, providing a slightly lower barrier height
LARSON AND SNYDER: OVERVIEW OF METAL S/D SB MOSFET TECHNOLOGY 1057
(0.27 eV), better lm quality, and improved manufacturability.
Sub-100-nm-gate-length SB-CMOS ring oscillators have been
demonstrated using the dopant-segregation technique with
Schottky-like contacts.
Finally, to date, the reported fabricated devices tend to have
nonideal physical parameters such as high EOT and gates with
improper work function. This makes it difcult to compare
the performance of SB-MOS devices to conventional PMOS
and NMOS technology. Demonstration of a sub-50-nm-gate-
length SB-CMOS circuit having a proper EOT integrated with
optimized SB-NMOS and SB-PMOS silicide process tech-
nologies is critical, and will be a signicant step forward for
SB-CMOS state of the art and will help resolve the debate about
the optimal SB height required for competitive SB-CMOS
technology.
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John M. Larson (M02) received the B.A. degree
in mathematics and physics from St. Olaf College,
Northeld, MN, in 1995, and the Ph.D. degree in
mechanical engineering with an emphasis in plasma
technology from the University of Minnesota, Min-
neapolis, in 2000.
Since 2000, he has been with Spinnaker Semi-
conductor, Bloomington, MN, as a Principal Scien-
tist, where he has focused on the development of
SB-CMOS process technology. His areas of interest
include integration of SB-CMOS technology in com-
mercial production facilities, including the integration of platinum and erbium
silicides. He is the holder of three patents in these elds.
John P. Snyder (S93M95) received the B.S.
degree in aerospace engineering from the Massa-
chusetts Institute of Technology, Boston, in 1988,
and the M.S. and Ph.D. degrees in electrical engi-
neering from Stanford University, Stanford, CA, in
1989, and 1996, respectively.
After working at National Semiconductor as a
Process Integration Engineer from 1996 to 1998, he
founded Spinnaker Semiconductor in Bloomington,
MN, for the purpose of commercializing Schottky-
barrier (SB)-CMOS technology. He currently serves
as Chairman and CTO at Spinnaker. His research interests are in the develop-
ment of a low-cost commercially manufacturable SB-CMOS technology, and in
the development of compact models required for the development of products
based on SB-CMOS technology. He is the holder of six patents in these areas.