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1824
The Thumb instruction set
The University
of Manchester
❏ Outline:
❏ Outline:
❏ Thumb is:
31 30 29 28 27 7 6 5 4 0
NZCV unused I F T mode
❏ Thumb-ARM similarities:
❍ load-store architecture
– with data processing, data transfer and control flow instructions
❍ support for 8-bit byte, 16-bit half-word and 32-bit data types
– half-words are aligned on 2-byte boundaries
– words are aligned on 4-byte boundaries
❍ 32-bit unsegmented memory
❏ Thumb-ARM differences:
❏ Outline:
15 12 11 8 7 0
1 1 0 1 cond 8-bit offset (1) B<cond> <label>
15 12 11 0
11100 11-bit offset (2) B <label>
15 12 11 10 0
1 1 1 1H 11-bit offset (3) BL <label>
15 12 11 7 6 5 3 2 0
0 1 0 0 0 1 1 1 0H 000 (4) BX Rm
❏ Subroutine calls
15 8 7 0
1 1 0 1 1 1 1 1 8-bit immediate
15 10 9 8 6 5 3 2 0
0 0 0 1 1 0 A Rm Rn Rd (1) ADD|SUB Rd,Rn,Rm
15 10 9 8 6 5 3 2 0
0 0 0 1 1 1 A imm3 Rn Rd (2) ADD|SUB Rd,Rn,#imm3
15 12 11 10 8 7 0
0 0 1 op Rd/Rn imm8 (3) MOV|CMP|ADD|SUB Rd/Rn,#imm8
15 13 12 11 10 6 5 3 2 0
0 0 0 op #sh (4) LSL|LSR|ASR Rd,Rn,#shift
15 10 9 6 5 3 2 0
0 1 0 0 0 0 op Rm/Rs Rd/Rn (5) <Op> Rd/Rn,Rm/Rs
15 10 9 8 7 6 5 3 2 0
0 1 0 0 0 1 op D M Rm Rd/Rn (6) ADD|CMP|MOV Rd/Rn,Rm
15 12 11 10 8 7 0
1 0 1 0 R Rd imm8 (7) ADD Rd,SP|PC,#imm8
15 8 7 6 0
10110000A imm7 (8) ADD|SUB SP,SP,#imm7
❍ In case (6):
– MOV does not affect the flags
(it can be distinguished using the mnemonic CPY after v6)
© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 15
MANCHEstER
1824
Thumb data processing instructions
The University
of Manchester
❏ Notes:
15 13 12 11 10 6 5 3 2 0
011BL off5 Rn Rd (1) LDR|STR{B} Rd,[Rn,#off5]
15 13 12 11 10 6 5 3 2 0
1000L off5 Rn Rd (2) LDRH|STRH Rd,[Rn,#off5]
15 12 11 9 8 6 5 3 2 0
0 1 0 1 op Rm Rn Rd (3) LDR|STR{S}{H|B} Rd,[Rn,Rm]
15 11 10 8 7 0
0 1 0 0 1 Rd off8 (4) LDR Rd,[PC,#off8]
15 12 11 10 8 7 0
1 0 0 1 L Rd off8 (5) LDR|STR Rd,[SP,#off8]
data transfers
15 12 11 10 8 7 0
1 1 0 0 L Rn reg. list (1) LDMIA|STMIA Rn!,
15 10 9 8 7 0
1 0 1 1 1 1 LR reg. list (2) POP|PUSH {<reg list>{,R}}
❏ BKPT (Breakpoint)
© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 20
MANCHEstER
1824
Newer Thumb instructions (from v6)
The University
of Manchester
❍ CPY
– Mnemonic allowing register moves without affecting flags
❍ SXTB/SXTH/UXTB/UXTH
– Sign extension (no shifts)
❍ REV/REV16/REVSH
– Byte swaps
❍ SETEND
❍ CPSIE/CPSID
– Interrupt enable/disables (no mode changes)
BX LR
❍ the routine can then be called from both ARM and Thumb
code
© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 22
MANCHEstER
1824
ARM/Thumb interworking
The University
of Manchester
❏ Outline:
instruction mapping
15 12 11 10 8 7 0
0 0 1 op Rd/Rn imm8 ADD Rd, #imm8
‘always’
condition
ma jor opcode,
minor opcode destination
format 3: MOV/ zero immediate
denoting ADD and source
CMP/ADD/SUB shift value
& set CC register
with immediate
31 28 27 26 25 24 21 20 19 16 15 12 11 8 7 0
1 1 1 0 0 0 1 0 1 0 0 1 0 Rd 0 Rd 0 0 0 0 imm8
❏ Outline:
assembly programs
❏ Explore further the ARM software development tools