CHAPTER 13 OUTPUT STAGES AND POWER AMPLIFIERS

Chapter Outline
13.1 Classification of Output Stages
13.2 Class A Output Stage
13.3 Class B Output Stage
13.4 Class AB Output Stage
13.5 Biasing the Class AB Circuit
13.6 CMOS Class AB Output Stages
NTUEE Electronics III 13-1
p g
13.1 CLASSIFICATIONS OF OUTPUT STAGES
Output Stages
Class A output stage:
Bias current is greater than the magnitude of the signal current
Conduction angle is 360
Class B output stage:
Biased at zero dc current
Conduction angle is 180
Another transistor conducts during the alternate half-cycle
Class AB output stage:
A i t di t l b t A dB
NTUEE Electronics III 13-2
An intermediate class between A and B
Biased at a nonzero dc current much smaller than the peak current of the signal
Conduction angle is greater than 180 but much smaller than 360
Two transistors are used and currents are combined at the load
Class C output stage:
Conduction angle is smaller than 180
The current is passed through a parallel LC network to obtain the output signal
Class A, B and AB are used as output stage of op amps
Class AB amplifiers are preferred for audio power amplifier
Class C amplifiers are usually used at higher frequencies
Collector current waveforms for the transistors operating in different classes
The classification also applies for output stages with MOSFETs
NTUEE Electronics III 13-3
13.2 CLASS A OUTPUT STAGE
Transfer Characteristics
Q
1
biased with a constant current I supplied by Q
2
Si l W f
1 BE I O
v v v =
sat CE CC O
V V v
1 max
=
L O
IR v =
min sat CE CC O
V V v
2 min
+ =
L
sat CE CC
R
V V
I
| |
2
+
>
or
NTUEE Electronics III 13-4
Signal Waveforms
The output swing from V
CC
to V
CC
for I =V
CC
/R
L
The instantaneous power dissipation in Q
1
: P
D1
=v
CE1
i
C1
Power Dissipation
Power dissipation for R
L
=V
CC
/I:
The maximum instantaneous power dissipation in Q
1
is V
CC
I
This is equal to the power dissipation in Q
1
with no input signal
applied (quiescent power dissipation)
The transistor Q
1
much be able to withstand a continuous power
dissipation of V
CC
I
Power dissipation for unloaded case:
Maximum power dissipation occurs when v
O
=V
CC
Themaximumpower dissipationinQ
1
is2V
CC
I
NTUEE Electronics III 13-5
The maximum power dissipation in Q
1
is 2V
CC
I
Power dissipation for an output short circuit:
A positive input may lead to an infinite load current
The output stages are usually equipped with short-circuit protection to guard against such a situation
Power dissipation in Q
2
:
Q
2
conducts a constant current I
Maximum voltage across the collector and the emitter is 2V
CC
Maximum instantaneous power dissipation in Q
2
is 2V
CC
I
A more significant quantity for design purposes is the average power dissipation of V
CC
I
Power Conversion Efficiency
The power conversion efficiency is defined as q P
L
(load power) /P
S
(supply power)
The load power (P
L
) with an sinusoid output with a peak value of is
The total average supply power is P
S
=2V
CC
I
The conversion efficiency is given by
Maximumefficiency(25%) isobtainedwhen
o
V

L
o
L
o
L
R
V
R
V
P
2 2
2
1 ) 2 / (

= =
|
|
.
|

\
|
|
|
.
|

\
|
= =
CC
o
L
o
CC L
o
V
V
IR
V
V IR
V

4
1
4
1
2
q
IR V V = =

NTUEE Electronics III 13-6

Maximum efficiency (25%) is obtained when
Class A output stage is rarely used in high-power applications
The efficiency achieved in practice is usually in the range of 10% to 20%
L CC o
IR V V = =
13.3 CLASS B OUTPUT STAGE
Circuit Operation
Both transistors are cut off when v
I
is zero v
O
is zero
One of the transistor turns on as v
I
exceeds 0.5 V v
O
follows v
I
The circuit operates in a push-pull fashion
The class B stage is biased at zero current and conducts only when
the input signal is present
Transfer Characteristic
There exists a range of input centered around zero
where both Q
N
and Q
P
are off
Thetransfer characteristicshowsadeadband
NTUEE Electronics III 13-7
The transfer characteristic shows a dead band
which results in the crossover distortion at the output
Power Conversion Efficiency
The average load power by neglecting the cross-over distortion is
The current drawn from each supply consists of half-sine waves of peak amplitude
The average power drawn from each of the two power supply is
The total supply power is
Th ffi i i i b
L
o
L
R
V
P
2
2
1

=
CC
L
o
S S
V
R
V
P P

t
1
= =
+
L o
R V /

CC
L
o
S
V
R
V
P

t
2
=
NTUEE Electronics III 13-8
The efficiency is given by
Maximum efficiency is obtained when the output swing is maximized (~ V
CC
):
The maximum average power available from a class B stage is
L
o
L
R
V
P
2
2
1

=
CC
o
V
V

4
t
q =
% 5 . 78
4
= =
t
q
Power Dissipation
The quiescent power dissipation of the class B stage is zero (unlike class A)
The average power dissipation of the class B stage is given by P
D
=P
S
P
L
Q
N
and Q
P
must be capable of safely dissipating half of P
D
P
D
depends on the output swing and the worst-case power dissipation is given by
The maximum power dissipation of Q
N
and Q
P
occurs at q =50%:
L
CC
D CC P o
R
V
P V V
D
2
max
2 2
max
t t
= =

L
o
CC
L
o
D
R
V
V
R
V
P
2
2
1 2

=
t
CC
V
P P
2
1
= =
NTUEE Electronics III 13-9
L
DP DN
R
P P
max max
t
= =
Reducing Crossover Distortion
The distortion can be reduced by employing a high-gain op amp and overall negative feedback
The 0.7V dead band is reduced by a factor of the dc gain of the op amp
The slew rate limitation of the op amp may cause the alternate turning on and off to be noticable
Single-Supply Operation
The class B stage can be operated from a single supply
The load is capacitivelu coupled
The derivations are directly applicable with supply of 2V
CC
NTUEE Electronics III 13-10
13.4 CLASS AB OUTPUT STAGE
Circuit Operation
Cross-over distortion can be eliminated by biasing Q
N
and Q
P
at a small nonzero current
The bias current i
N
=i
P
=I
Q
=I
s
exp(V
BB
/2V
T
)
When v
I
goes positive by a certain amount:
The load current is supplied by Q
N
which acts as the output emitter follower
Q
P
will be conducting a current that decreases as v
O
increases (negligible for large v
O
)
BEN BB I O
v V v v + = 2 /
BB BEP BEN
V v v = +
0 ln 2 ln ln
2 2 2
= = = +
Q L N N Q P N
S
Q
T
S
P
T
S
N
T
I i i i I i i
I
I
V
I
i
V
I
i
V
NTUEE Electronics III 13-11
Q
P
acts as the output emitter follower when v
I
goes negative
The power properties are almost identical to those derived for the class B stage
Output Resistance
The output resistance is estimated by assuming the source supply v
I
ideal
The output resistance remains approximately constant in the region around v
I
=0
The output resistance decreases at larger load currents
P N
T
P
T
N
T
eP eN out
i i
V
i
V
i
V
r r R
+
= = = || ||
NTUEE Electronics III 13-12
13.5 BIASING THE CLASS AB CIRCUIT
Biasing Using Diodes
The bias voltage V
BB
is generated by passing a constant current I
BIAS
through a pair of diodes
The diodes need not to be large devices
Quiescent current I
Q
in Q
N
and Q
P
will be I
Q
=nI
BIAS
where n is the ratio of the areas of the emitter
junction of the BJ T and the junction area of the diodes
I
BN
increases from I
Q
/|
N
to I
L
/|
N
for a positive v
O
I
BIAS
has to be greater than the I
BN
for maximum I
L
case
The ratio n cannot be a large number as n =I
Q
/I
BIAS
This biasing arrangement provides thermal stabilization of the quiescent current in the output stage
Collect current increases with temperature for a fixed V
BE
NTUEE Electronics III 13-13
p
BE
Heat from power dissipation increases with current
Positive feedback may cause thermal runaway
V
BB
decreases at the same rate of V
BEN
+V
EBP
Thermal runaway is alleviated with close thermal contact
Biasing Using the Voltage Multiplier
The class AB stage can be biased by V
BE
multiplier
The value of V
BE1
is determined by the portion of I
BIAS
that flows through the collector of Q
1
The quiescent current can be adjusted by the resistance value
) / 1 (
/
1 2 1
1 1
R R V V
R V I
BE BB
BE R
+ =
=
R BIAS C
I I I =
1
R BIAS
C
T
S
C
T BE
I I
I
V
I
I
V V

= =
1 1
1
ln ln
NTUEE Electronics III 13-14
13.6 CMOS CLASS AB OUTPUT STAGES
The Classical Configuration
Circuit operation
For thecaseQ
1
andQ
2
arematchedandQ
P
andQ
N
arematched:
|
|
.
|

\
|
'
+
'
+ + = + =
2 1
2 1
) / (
1
) / (
1
2 | |
L W k L W k
I V V V V V
p n
BIAS tp tn SG GS GG
|
|
.
|

\
|
'
+
'
+ + = + =
p p n n
Q tp tn SGP GSN GG
L W k L W k
I V V V V V
) / (
1
) / (
1
2 | |
2
2
1
) / ( / 1
) / ( / 1
) / ( / 1
) / ( / 1
|
|
.
|

\
|
'
'
+
'
'
=
p p
p
n n
n
BIAS Q
L W k
L W k
L W k
L W k
I I
NTUEE Electronics III 13-15
For the case Q
1
and Q
2
are matched and Q
P
and Q
N
are matched:
A drawback of the CMOS class AB circuit is the restricted range of output voltage swing
where
v
OVN
is the overdrive voltage of Q
N
when it is supplying i
Lmax
and
|v
OVP
| is the overdrive voltage of Q
P
when sinking the maximum negative value of i
L
1
) / (
) / (
L W
L W
I I
n
BIAS Q
=
OVN tn BIAS OV DD O
v V V V v = |
max
| | | | |
min OVP tp I OV SS O
v V V V v + + + =
An Alternative Circuit Using Common-Source Transistors
The allowable output range can be increased by replacing the source followers with a pair of
complementary transistors in the common-source configuration
Q
P
supplies the load current when v
O
is positive, allowing an output as high as V
DD
|v
OVP
|
Q
N
sinks the load current when v
O
is negative, allowing an output as low as V
SS
+v
OVN
The disadvantage is its high output resistance R
out
=r
on
||r
op
Negative feedback (error amplifiers) is employed to reduce the output resistance
NTUEE Electronics III 13-16
Output Resistance
The output resistance is derived by two half circuits:
The analysis techniques for feedback (shunt-series feedback) is utilized:
and
The open-loop output resistance:
The output resistance with feedback:
The output resistance excluding R
L
:
Overall output resistance:
outp outn out
R R R || =
1 = | ) || (
L op mp
i
o
R r g
v
v
A =
op L o
r R R || =
)] || ( 1 /[ ) || ( ) 1 /(
op L m op L o of
r R g r R A R R | + = + =
mp mp
op L of outp
g g
r R R R

1 1
|| ) / 1 / 1 /( 1 ~ = =
) ( / 1
mn mp out
g g R + ~
NTUEE Electronics III 13-17
The Voltage Transfer Characteristics
For the case where Q
N
and Q
P
are matched:
Drain currents: and
Load current:
Output voltage:
Gainerror:
2
2
1
OV Q
kV I =
2
1
|
|
.
|

\
|
+ =
OV
I O
Q DN
V
v v
I i
2
1
|
|
.
|

\
|
=
OV
I O
Q DP
V
v v
I i
DN DP L
i i i =
|
|
.
|

\
|
~
|
|
.
|

\
|
+ =
L Q
OV
I
L Q
OV
I O
R I
V
v
R I
V
v v
4
1
4
1 /
OV OV
V V
v v = =
NTUEE Electronics III 13-18
Gain error:
L m L Q
I O
R g R I
v v
2 4
= =