Fig.

1: Block Diagram of a Phase-Locked Loop

Fig. 2: Block Diagram of a Phase-Locked Loop
design id
PROBLEM DESCRIPTION
A phase-locked loop has a center frequency of 10
5
rad/s, a gain of voltage controlled oscillator (VCO) is 10
3
rad/V-s,
and a gain of phase-comparator is 1 V/rad. Determine the loop bandwidth in the rst order loop conguration. Determine
the single-pole, loop-lter pole location to give the closed-loop poles located on 45

radials from the origin. Design a loop

lter with a zero that gives a cross over frequency for the loop gain of 100 rad/s. The loop phase shift at the loop cross-over
frequency should be 135

. Also estimate the capture range of PLL.

SOLUTION
Theory
The blocks of a PLL comprise a phase detector, a loop lter, an Amplier and a voltage controlled oscillator. These form
a loop. The voltage-controlled oscillators frequency becomes same as frequency of input signal when this loop is locked for
that particular input. Phase detector is basically a phase comparator that produce a dc or low frequency signal proportional to
the phase difference between the incoming signal and the VCO output signal. This signal is ltered by loop lter and later
amplied before pushing at the input of VCO. If frequency of input signal shifts slightly, there would come a phase difference
between the output signal of VCO and the input signal. This phase difference will increase and would intern change the control
voltage of VCO such that VCO frequency is adjusted to that of input signal. In such situation, PLL is locked.
The range of input signal frequencies over which PLL can maintain lock is called the lock range. And, capture range of
the PLL is the range of frequency around the center frequency or free-running frequency of VCO onto which PLL would be
locked from an unlocked condition. The pull-in time is the time required for the loop to capture the signal. These parameters
depend on the gain and bandwidth of the loop. Loop lter lters out the components resulting from interference (noise) signals
or out-of-band signals far away from the center frequency of VCO. For better performance, the bandwidth of loop lter is
kept as narrow as possible. But, this would reduce the capture range and increase the pull-in time. Therefore, the loop phase
margin becomes poorer.
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The freuquency of VCO output is time-differentiation of its phase.

osc
(t) =
d
osc
(t)
dt
and, VCO is designed such that

osc
=
0
+K
O
V
o
where
0
is the free running frequency of VCO when output voltage is zero.
The gain of phase comparator is K
D
rad/s and that of VCO is K
o
rad/V-s. Transfer function of loop lter is denoted by
F(s). So, the closed-loop transfer function of PLL is give by the following expression.
V
o

i
=
sK
D
F(s)A
s +K
D
F(s)AK
o
The relationship between output voltage and input frequency is in terms of above expression is

i
=
d
i
dt

i
(s) = s
i
(s)
V
o

i
=
1
s
V
o

i
=
K
D
F(s)A
s +K
D
F(s)AK
o
=
1
K
o
K
v
s +K
v
where F(s) is assumed to unity and K
v
= K
o
K
D
A is called the loop bandwidth.
Therefore, the PLL is a rst-order, low-pass transfer characteristic. This is the frequency modulation on the incoming carrier
to the loop voltage output.
Computations
Given that K
o
= 10
3
rad/V-s and K
D
= 1 V/rad. Assuming there is no other gain in the loop (or A = 1). The loop
bandwidth is
K
v
= K
o
K
D
A = 10
3
Hz
Loop lter is a low pass, single-pole system
F(s) =

1
1 +
s
1

V
o

i
=
K
D
F(s)A
s +K
D
F(s)AK
o
=
1
K
o
K
v
s +K
v
F(s)
=
1
K
o
K
v

1
1+
s

s +K
v

1
1+
s

1
=
1
K
o
K
v
s(1 +
s
1
) +K
v
=
1
K
o

1
1 +
s
Kv
+
s
2
Kv1

s =
1
2
1
Kv1

1
K
v

1
K
2
v
4
1
K
v

1
2

1
4K
v

In standard form, the above expression is written as

V
o

i
=
1
K
o
1
s
2

2
n
+
2
n
s + 1
where
n
=

K
v

1
and =
1
2

1
Kv
The loop bandwidth is determined by K
v
and, thus, the mangnitude
1
of the additional pole introduced by the loop
lter should be made as low as possible without causing unacceptable peaking in the frequency response. The excessive
peaking would cause the distortion in demodulated FM output and also causes the loop to ring or experience a poorly
damped oscillatory response, when a transient disturbs the loop. A good compromise is using a maximally at low-pass
pole conguration in which the poles are placed on radials angled 45

from the negative real axis. For this response, the

damping factor should be equal to
1

2
=
1
2

1
K
v

1
= 2K
v
Therefore, loop lter pole location to give the closed loop poles located on 45

radials from the origin is 2 10

3
rad/s.
2
The circuit of single-pole and single-zero loop lter is given in gure 2. Its transfer function is given by
F(s) =
1 +
s
2
1 +
s
1
where

2
=
1
C
2
R
2
and

1
=
1
C
2
(R
1
+R
2
)
Given that cross-over frequency
2
= 100 rad/s (zero-frequency). Then,
1
= 10 rad/s.

1
= 1 +
R
1
R
2
= 10
R
1
= 9R
2
Suppose, R
1
= 90 k, R
2
would be 10 k and C
2
= 1 F.
DESIGN OUTCOME
TABLE I: Circuit Components
No. Component Value
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ASSUMPTIONS
1)
Contact: AMiglani2014@gmail.com
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