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Sood Pructices V 4,0
SPZZ PSL / InterIock Iimitutions
Document version 1.0
Creation 14/05/2007
Last update 14/05/2007
Author Pierre-Yves LEGRIS
Josselin DOHOLLO
Category SCE / FBD Editor
Language English
File name GP22_Interlock_PSL_Limitations.doc


CONTENTS

1. SCOPE............................................................................................................................................ 2
2. INTRODUCTION......................................................................................................................... 2
3. RULES............................................................................................................................................ 2
3.1. MAXIMA.................................................................................................................................. 2
3.2. DESCRIPTION AND EXAMPLES.................................................................................................. 3
4. CONCLUSION.............................................................................................................................. 3


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1. Scope
The purpose of this good practice is to define the limitations of PSL automations.
2. Introduction
The MiCOM C264 can be configured to create logical schemes through Isagraf, PSL and
interlock equations.

Definitions:
FBD: one automation scheme based on logic operators, timers, RS gates, having one or
several input/outputs. each FBD is edited with the SCE / FBD Editor
PSL: Set of all the automation schemes (named FBD) based on logics, integrated in a
MiCOM C264 and edited with SCE/ FBD editor
Interlock equation: specific logic scheme with one output, directly associated to a BAY
control and integrating some logical operators (OR, AND, NOT, XOR)

The purpose of the PSL and interlock equations is to execute simple logical schemes upon
change of one of its logical input, i.e. on an event basis. PSL also accommodate timer
operator in order to process slightly more complex schemes. The use of Isagraf is for more
complex schemes, typically sequential, executed on a periodical basis (from 50 ms and
above depending on the computer load).
3. Rules
In term of PSL the programming shall be organised in simple blocks. A block is made of
one or several OR, AND, NOT, XOR, NAND and NOR operators, and has one output. The
blocks are then chained by timers (minimum 50 ms) or RS gates inside one PSL or FBD.
3.1. Maxima
There is a maximum of 768 blocks per MiCOM C264. One FBD has a minimum of one block
(more if the FBD contains timers or RS gates).
A timer counts as a block.
An interlocking equation counts as a block as well and there is a maximum of 512
interlocking equations.
RS Gates do not count in the total number of blocks; each of RS input is associated to a
blocks output.
There are also 256 logical operations available (i.e. [A & B] OR [C & D] by developing [A
OR C] & [B OR C] & [A OR D] & [B OR D] and gives 7 logical operations).

A block shall have a maximum of 3 levels, as explained in the figure 1, able to be:
- executed instantaneously (few ms, depending on the computer load),
- analysed easily for tuning purpose,
- constrained in term of number of inputs and gates.

The engineering tool enables to have more than 3 levels however the debug and sizing of
the PSL becomes unpractical and is thus not described hereafter.


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AND
AND
/OR
AND
/OR
Output
Inputs
Level 1
M inputs per gate
AND
AND
etc.
AND
/OR
etc.
AND
/OR
AND
AND
AND
Level 2
N inputs per gate
Level 3
P inputs per gate
M inputs per gate
N inputs per gate
P inputs

Figure 1: A block shall have a maximum of 3 levels
3.2. Description and examples
The first level of a block shall be made of AND, NOT or NOR gates only, in order to
increase the PSL capabilities. OR, NAND and XOR shall be handled by a specific block.
One block can get up to 256 inputs and up to 4 outputs.
3.2.1. 1 gate per level
For a given block, there is a maximum of 256 inputs. This corresponds to the extreme case
where each level has a single gate, i.e. 3 gates in total, M = 256, N = P = 1 (M, N and P are
defined in the diagram).
3.2.2. More than 1 gate at 1st level
When a level of a block has more than one gate the worst case corresponds to a level 3
made of OR/NOR/XOR gates only and a level 3 made of one AND/NAND gate. In this case
the configuration shall not exceed:
- Either M = 10 inputs at level 1, N = 2 inputs at level 2 and P = 3 inputs at level 3.
This corresponds to 60 external inputs and 10 gates.
- Or M = N = P = 3. This corresponds to 27 inputs and 13 gates.

These limits might be exceeded depending on the occupation of a given level (i.e. existence
or not of the maximum number of inputs per gate) and type of gates.
4. Conclusion
- PSL Max_nb =768 ---------- Interlock equations: max_nb = 512
---------- FBD: max_nb= (768 interlock_equations_nb)
- Each input might be present in a maximum of 256 blocks.
- The MiCOM C264 can manage up to 5600 binary values, that are part of PSL or
not.