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18623F12AnalogIntegratedCircuitDesign
CadenceLayoutTutorial
Objective
The objective of this document is to familiarize you with using Cadence Virtuoso to draw your
circuit layouts. Through this tutorial, you will learn how to generate the layout of components
from Cadence Virtuoso Layout XL and complete the routing using metal wires. Also you will
learn how to use Assura to do the Design Rule Check (DRC) to verify that the layout meets the
design rules, and the Layout Versus Schematic (LVS) check to ensure that the layout matches
your schematic.









Author
Renzhi Liu
Cheng-Yuan Wen
Report bugs and errors to: renzhil@andrew.cmu.edu




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Generating Layout from Schematic

The following figure shows the schematic of a common source (CS) amplifier in the Spectre
simulation environment:


Note: Before go to Layout XL, please make sure that the schematic does not consist of any
voltage and current sources, and instead it should contain pins. Also all the device should have
exact sizes (no variables).
Select LaunchLayout XL.




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Check Create New and click on OK.

Do not change the Cell Name. Make sure that View layout and click on OK.


It will open up a new empty window titled Virtuoso Layout Suite XL Editing. In this window,
go to ConnectivityGenerateAll From Source





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This will open up another window:

Here you can decide what will be generated.
Go to I/O Pins in the above window.

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Here you can decide the metal layer for every pin. Click Options under Pin Label. Change the
height to 0.05.

After setting these options, click on OK. It will create the transistors and pins in the Virtuoso
Window.

Press Shift + f to reveal all mask layers within each layout cell.

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In the Virtuoso XL Layout Editing window, go to OptionsDisplay and the following window
will pop up. In the Grid Controls area, you can setup the minimal space between grid dots. In the
Snap Modes, you can specify whether or not the geometries are allowed to have angles other than
orthogonal ones. You can play with these options, but we will keep them unchanged for now in this
tutorial.






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Go to OptionsEditor and the following window will pop up. You can also setup the Gravity
Controls by checking Gravity On option. This is to setup if an object will be attracted by a closed
one when you are moving it. Sometimes this is convenient when you are aligning objects but we still
keep the settings unchanged for now.

Select the PMOS cell and press q. The properties of the PMOS will pop up. You can change the
Attribute or Parameter of an instance from here.

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Go to Parameter and scroll down. Set the following area:

Use DFM RulesDFM: Using Design_For_ Manufacturing rules rather than minimum size or
space rules.

Here you can also play with Gate Connection and Bodytie Type. The default values here are
both None, which means no gate connection and body tie would be generate automatically.
These are more preferable options when you do analog layout, since they provide more freedom.
You can also try other options to see what happen.


Editing Objects
Click on Edit in the Virtuoso XL Layout Editing window, you can see a lot of actions to edit
your devices. You can always select the action (by either select here or by corresponding
shortcut) first then click on the device or click on the device first then select the action. Both
ways will work. For example, select EditCopy and click on the PMOS cell then you can have
the PMOS cell copied anywhere you want.




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All the layers to form the layout can be controlled in the Layers section. You should select the layer
before drawing an object. Besides, click on AV will make all layers visible in the layout while NV
will let all layers not selected become invisible. Selectable is controlled by AS and NS.

Each layer has its own purpose. Purpose dra is used in layout. In this layout we will be using
only the dra layer.

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Placement and Routing

1. Move all devices and pins close to each other (use Edit-Move (shortcut: M) or directly drag
them)

2. Create the gate connection for both PMOS and NMOS (CreateVia (O), select the desired via
type under Via Definition, here choose M1_PO)

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3. Create body tie for NMOS (Create-Via (O), select Via Definition as M1_PSUB)

4. Create body tie for PMOS (Create-Via (O), select Via Definition as M1_NWELL), also draw
a larger NWELL which include body tie and PMOS (Create-Shape-Rectangle (R)).

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5. Connect the drain of the PMOS to the drain of the NMOS (select Metal 1 in LSW window and
use CreateShapeRectangle (R) or CreateShapePath (P))

6. Connect the source and body of both PMOS and NMOS.

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7. Put all the pins to their right positions.

Now the layout of the CS amplifier is done.

Some Useful Commands
Keyboard arrows (up, down, left, right): Move about the layout view screen
f: Fit entire layout onto screen
F2: Save design
Esc: Cancel previous command
Shift + f: Reveal all mask layers within each layout cell
(Use Ctrl + f to hide these layers)
q: Properties
p: Create path (Convenient for making interconnections between I/O pins of layout cell; need to
select mask layer first from LSW window)
r: Create rectangle of mask layer (Select .dg mask layer first from LSW)
Ctrl + p: Create pin (Select pin mask layer first from LSW)
i: Instantiate layout cell
Select more than one mask layer simultaneously Hold down Shift and click on each layer (Use Ctrl
to deselect a particular layer)
u: Undo
c: Copy
del: Delete
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m: Move
s: Stretch (Point to edge of mask layer first using mouse cursor)
k: Ruler (Erase ruler Shift + k)
Ctrl + a Select All
Ctrl + d De-select All
Ctrl + z Zoom in by a factor of 2
Shift + Z Zoom out by a factor of 2
Z or Right click - Zoom to box (select on layout window)

Running DRC with ASSURA

To make sure the design can be reliably manufactured by the foundry, the layout has to meet all
constraints determined by the foundry. The procedure of checking if the layout meets all
requirements is called Design Rule Check (DRC). In this section, we will use ASSURA to check the
layout with the design rules of this GPDK.

First, in Virtuoso XL Layout Editing window, go to Assura-Technology, in the pop up window,
type in /afs/ece/ class/ece623/F12/gpdk045_v_3_5/assura_tech.lib and click on OK.





Go to AssuraRun DRC A Run Assura DRC window will pop up. Change the Technology
dropdown to gpdk045_av. Then click on OK.

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A small window will pop up and ask if you want to view the results of DRC. Click on Yes.

An Error Layer Window pops up and lists all errors against design rules. The list of errors area
explains how the layout violates design rules and you can use the circled arrows to check each error
highlighted in the layout. The explanation only briefly describes why the layout does not meet the
design rule requirement. You can further look up the gpdk045_drc.pdf posted on blackboard for
more details.

The first error says the minimum area for active area should be larger than 0.035um
2
. If you highlight
this error and click on the right arrow, the layout window will zoom into the marked area and tell you
where the error occurs. As you can see, this error comes from the body tie we created for both PMOS
and NMOS, and it happened twice in the layout.

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There are usually several ways to solve this error (the simplest way is to use integrated body tie).
Here we can just increase the number of body tie via. Select the via and press q, the properties of
the via will pop up. Scroll down, under Cut section, increase Rows and Columns to 2.

After doing this, the error of minimum area for active can be solved. However, this might create
some other minimum space violation. You can simply correct these errors just by moving via.
The second error is about minimum Metal1 area. It also happens twice in the layout, and it
comes from the M1_PO via we created for gate. You can just add more Metal1 on the via.
In the end, the layout would look like this.

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Run DRC again, now you will see a small window pops up says No DRC errors found!


Running LVS with ASSURA
Sometimes the layout is more complicated than that in this example and it is difficult to know if
devices are correctly connected in the layout. In this case, running Layout Versus Schematic
(LVS) to check if the layout matches with the schematic is demanding.
Go to AssuraRun LVS and the following window will pop up. Change the Technology
dropdown to "gpdk045_av". Then click on OK.




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After running, one information window will pop up. Click on Yes.

You will see the Schematic and Layout Match message in the Cell List area.

If unfortunately the layout doesnt match your schematic (which is often the case), in the
Summary field, you will see a list of unmatched devices. (Sch || Lay) means (the number of
nets/cells, etc recognized in the schematic || the number of nets/cells, etc recognized in the
layout). You can click on the mismatched entry and use OptionsShow mismatch Details to
fix errors.