QDCA For Reversible Logic Gate

Communications in Information Science and Management Engineering CISME
CISME Vol. 2 Iss. 4 2012 PP. 8-18 www.jcisme.org

C
2011-2012 World Academic Publishing

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Quantum-dot Cellular Automata (QCA) Design of
Multi-Function Reversible Logic Gate
N. A. Shah
1
, F. A. Khanday
1*
and J. Iqbal
1
1
Department of Electronics and Instrumentation Technology, University of Kashmir, Srinagar 190006, India
*Corresponding Author E-mail: farooqsnn20@yahoo.co.in

Abstract- This paper presents implementation of multi-function
reversible Gate using Quantum-dot Cellular Automata (QCA),
which fulfils desirable circuit features of small size, high device
density, and low power dissipation of contemporary emerging
circuit design technologies. The design methodology followed is
such that the resultant circuits not only occupy smaller area, but
also enjoy superior performance factors in respect of noise,
circuit stability, and low power dissipation. The multi-function
reversible gate can be configured to work as universal gate, Fan-
out and comparator functions. And all have been designed in
QCA and presented in this paper as well. The operation of QCA
circuits is simulated using QCADesigner bistable vector
simulation.
Keywords- Nanotechnology; Quantum-dot Cellular Automata;
Nanoelectronics; Reversible Computing; Circuit Design; Circuit
Simulation
I. INTRODUCTION
The emerging technologies pertaining to circuit design lay
great emphasis on small size, high device density, and low
power dissipation to achieve objective of portability of
systems [1]. Among up-and-coming technologies, Quantum-
dot Cellular Automata (QCA) [2,3] promises aforementioned
features. The implementation of circuits using QCA is based
on Coulombic interactions. In QCA, inverter (INV) and
majority voter (MV) gates as well as other devices such as
binary wire and INV chain have been proposed as primitives
for the combinational circuit design [5]. It has been shown in
[6, 7] that for QCA, the functions with at most three input
variables (such as MV) forms the basis for efficient
combinational design. As a combined methodology for
computation and communication [8, 9, 10], different designs
of logic circuits have been proposed for implementation in
QCA [8, 11-17].
The use of emerging technologies in implementing new
computational paradigms [18] must necessarily have the
features of small feature size, high device density, and low
power dissipation. One of these paradigms is reversible
computing, accomplished by establishing a one-to-one onto
mapping between the input states and output states of the
circuit [19]. This bijective property was initially investigated
by Landauer who showed that
2 ln KT
joules of energy are
generated for each bit of information lost due to non reversible
computation [20]. But, if computation is performed in a
reversible manner, it must show that
2 ln KT
energy
dissipation would not necessarily occur. Due to the bijective
property, testing of reversible logic is generally simpler than
the conventional irreversible logic [21]. Moreover, reversible
logic gates are information lossless, i.e. the information output
of a reversible circuit is maximized. Therefore, according to
[22], the probability of fault detection is maximized too.
Reversible logic is inherently easier to test, because the one-
to-one onto property improves controllability as well as the
observability of the circuit.
Traditional logic functions (such as AND, OR) are not
reversible, because more than one input state is mapped to a
common output state. In this case, given the output state, it is
not possible to determine initial input states. Inverter (INV) is
a simple example of a reversible logic gate. The most studied
reversible logic gates are the Toffoli [23] and the Fredkin [26].
Besides Toffoli and Fredkin gates, various other reversible
gates have also been proposed [23-33]. Recently a new
multifunction reversible gate has been proposed and can be
used to implement various logic functions [34].
A wide range of gates as primitives [23-33] for reversible
logic computation have been proposed. In most cases, an
elegant mathematical analysis (such as those based on the
conservative property) of these gates has been provided to
describe a technology independent characterization by which
reversible computing (mostly at logic level) can be
accomplished. However, little work has been reported on the
capabilities of emerging technologies to perform reversible
computation. Based on this fact, our endeavor in this paper is
to present efficient QCA implementation of multi-function
reversible gate [34]. The various logic functions that could be
implemented out of the multi-function reversible gate have
also been presented.
II. MULTI-FUNCTION REVERSIBLE GATE
Figs. 1(a)-1(c) respectively show the block diagrams of
two, three, and four input reversible gates. The input-output
relations of various reversible gates that have been reported in
the literature [23-33] are given in Table I.

(a)

(b)

(c)
Fig. 1 Block diagram representation of two, three and four input
reversible
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TABLE I
INPUT OUTPUT RELATION OF REVERSIBLE GATES
S. No. Gate
Input
Vector
Output
Vector
Output
P
Q
R S
1.
2*2 Feynman
Gate [25]
B A I ,

Q P O ,

A A B
X X
2.
3*3 Double
Feynman Gate
[26].
C B A I , ,

R Q P O , ,

A A B A C
X
3.
3*3 Toffoli Gate
[23]
C B A I , ,

R Q P O , ,

A B AB C
X
4.
3*3 Fredkin
Gate [24]
C B A I , ,

R Q P O , ,

A A B AC A C AB
X
5.
3*3 New Gate
[ 27]
C B A I , ,

R Q P O , ,

A AB C A C B
X
6.
3*3 Peres Gate
[28]
C B A I , ,

R Q P O , ,

A A B
R=ABC
AB C
X
7.
3*3 NFT Gate
[26]
C B A I , ,

R Q P O , ,

A B B C AC BC AC
X
8.
4 * 4 BVF
Gate[29]
D C B A I , , ,

S R Q P O , , , A A B C C D
9.
4*4 HNG Gate
[30]
D C B A I , , ,

S R Q P O , , , A B A B C
A B C AB D
10.
4*4 HNFG
Gate[31]
D C B A I , , ,

S R Q P O , , , A A C
B B D
11.
4*4 SCL
Gate[32]
D C B A I , , ,

S R Q P O , , , A B C
A B C D
12.
4*4 TSG
Gate[30]
D C B A I , , ,

S R Q P O , , , A A C B A C B D

A C B D AB C

13.
4*4 MTSG
Gate[33]
D C B A I , , ,

S R Q P O , , , A A B A B C A B C AB D

14.
Multifunction
Reversible
(BVMF)
Gate[34]
D C B A I , , ,

S R Q P O , , , A B C

A B AB D AB D

III. QCA IMPLEMENTATION OF MULTI-FUNCTION REVERSIBLE
GATE
A QCA cell can be viewed as a set of four charge
containers or dots, positioned at corners of a square [5]. The
cell contains two extra mobile electrons which can quantum
mechanically tunnel between dots, but not cells. The electrons
are forced to the corner positions by Coulombic repulsion.
The two possible polarization states represent logic 0
(polarization P = 1) and logic 1 (polarization P = +1), as
shown in Fig.2. Unlike conventional logic circuits in which
information is transferred by electrical current, QCA operates
by the Coulombic interaction that connects the state of one
cell to the state of its neighbors. This results in a technology of
which information transfer (interconnection) is the same as
information transformation (logic manipulation). One of the
basic logic gates in QCA is the majority voter (MV) [5]. The
majority voter with logic function MV (A, B, C) = AB + AC +
BC, which can be realized by only five QCA cells, as shown
in Fig. 3a. Logic AND and OR functions can be implemented
from the majority voter by setting one input (the so-called
programming or control input) permanently to a 0 or 1 value.
The inverter is the other basic gate in QCA and is shown in
Fig.3b. The binary wire (as interconnect fabric) is shown in
Fig.3c. Besides, an XOR gate given in Fig.3d forms an
important gate in the QCA design of reversible gates.

Fig. 2 QCA cells showing how binary information is encoded in the two fully
polarized diagonals of the cell

(a)

(b)
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(c)

(d)
Fig. 3 QCA implementation of (a) Majority Voter (b) Inverter (c) Binary wire
and (d) XOR gate
In VLSI systems, timing is controlled through a reference
signal (i.e. the clock); however, timing in QCA is
accomplished by clocking in four distinct and periodic phases
[15] (as shown in Fig.4). A QCA circuit is partitioned into
serial (one-dimensional) zones, and each zone is maintained in
a phase. The use of a quasi-adiabatic switching technique for
QCA circuits requires a four-phased clocking signal, which is
commonly supplied by CMOS wires buried under the QCA
circuitry for modulating the electric field. The four phases are
Relax, Switch, Hold and Release. During the Relax phase,
there is no interdot barrier and a cell remains unpolarized.
During the Switch phase, the interdot barrier is slowly raised
and a cell attains a definitive polarity under the influence of its
neighbors. This is the phase in which the actual computation
takes place. In the hold phase, barriers are high and a cell
retains its polarity. Finally in the Relax phase, barriers are
lowered and a cell loses its polarity. Timing zones of a QCA
circuit or system are arranged by following the periodic
execution of these four clock phases. Zones in the Hold phase
are followed by zones in the Switch, Release and Relax phases,
one after another. There is effectively a latch between two
clocking zones. A signal is latched when one clocking zone
goes into Hold phase and acts as input to the subsequent zone.
This clocking mechanism provides inherent pipelining [35, 36]
and allows multi-bit information transfer for QCA through
signal latching. Because a zone in the Hold phase is followed
by a zone in the Switch phase (and preceded by a zone in the
Relax phase), the computation in QCA is strictly one-
dimensional (i.e. unidirectional and consistent with signal
propagation). Designs are partitioned along one dimension
(say the X-axis), thus effectively creating columns of clocking
zones. The clocking signal is applied through an underlying
CMOS circuitry that generates the required electric field to
modulate the tunnelling barrier of all cells in the zones.

(a)

(b)
Fig. 4 Four-phased signal for clocking zones in QCA, adiabatic switching
(a) 4 Phase Clocking (b) Switching of a Binary Wire
Various reversible gates have been presented in the
literature but a few of them have been designed in QCA [37].
Considering the applicability of multi-function reversible gate
given in row fourteen of Table I, it was designed using
QCADesigner tool as shown in Fig. 5. In the environment of
the QCADesigner tool, the overall QCA cell dimensions are
defined to be 1818nm; the dot diameter is defined to be 5 nm
and the inter-cell distance to be 2 nm. The number of cells,
gates used, area covered, cell area to overall area and Delay
from input to output (in Clock Zones) of the mult-function
reversible gate is given in Table II. The simulation results of
the design, acquired by the QCADesigner bistable vector
simulation engine, are given in Fig. 6.

Fig. 5 QCA implementation of multi-function reversible gate [34]
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TABLE II
PERFORMANCE PARAMETERS OF QCA BASED MULTI-FUNCTION
REVERSIBLE GATE
S. No. Parameters
Value
1. No. of Cells Used 69
2. No. of Gates Used 6
3. Cell Area (m
2
) 0.119556 (m)
2

4. Cell to Overall Area 1/4.22
5.
Delay from Input to Output
(in Clock Zones)
8
IV. APPLICATIONS OF MULTI-FUNCTION REVERSIBLE GATE
As mentioned earlier, multi-function reversible gate can be
used for the following applications:
a) Universal Gate
i) AND and OR
ii) OR and NAND
iii) AND and NOR/1 to 4 DEMUX
iv) NOR and NAND
b) Fan-out
i) Fan-out
ii) Fan-out and Complement
c) Comparator
The above functions can be obtained from the multi-
function reversible gate by adjusting the inputs to different
logic levels as given in Table III. The QCA designs of these
functions are shown in Fig. 7. The simulation results of the
design, acquired by the QCADesigner bistable vector
simulation engine, are given in Fig. 8.

Fig. 6 Simulation results of multi-function reversible gate [34].
TABLE III
INPUT OUTPUT RELATION OF REVERSIBLE GATES
S. No. Gate
Input
Vector
Output
Vector
Output
P
Q R S
1. AND and OR
0 , 0 , , B A I

S R Q P O , , ,

A B A B AB AB
2. OR and NAND
1 , 0 , , B A I

S R Q P O , , ,

A B A B A B AB

3.
AND and NOR/
1 to 4 DEMUX
0 , 1 , , B A I

S R Q P O , , ,

A B A B AB AB
4. NOR and NAND 1 , 1 , , B A I

S R Q P O , , ,

A B

A B A B AB

5. Fan-out
D C I , , 0 , 0

S R Q P O , , ,

C D D D
6.
Fan-out and
Complement
D C I , , 1 , 0
D C I , , 0 , 1
D C I , , 1 , 1

S R Q P O , , ,

C
C
C
D
D
D
D
D
D
D
D
D
7. Comparator
0 , 1 , , B A I

S R Q P O , , ,

0
A B A B

A B

1
A B

C

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(a)

(b)

(c)

(d)
C

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(e)

(f)

(g)

(h)
C

- 14 -

(i)

Fig. 7 QCA implementation of logic functions obtained from multi-function reversible gate, (a) AND and OR, (b) OR and NAND, (c) AND and NOR (d) NOR
and NAND (e) Fan-out (f) Fan-out and Complement 1, (g) Fan-out and Complement 2, (h) Fan-out and Complement 3 and (i) Comparator

(a)
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(b)

(c)

(d)
C

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(e)

(f)

(g)
C

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(h)

(i)
Fig. 8 Simulation Results of logic functions obtained from multi-function reversible gate, (a) AND and OR, (b) OR and NAND, (c) AND and NOR (d) NOR and
NAND (e) Fan-out (f) Fan-out and Complement 1, (g) Fan-out and Complement 2, (h) Fan-out and Complement 3 and (i) Comparator
V. CONCLUSION
In this paper, multi-function reversible gate was
implemented using QCA. The gate is very useful for the future
computing techniques like ultra low power digital circuits and
quantum computers. The use of gate in the design and
development of combinational and sequential circuits would
prove to be beneficial in respect of power saving, reduction of
garbage outputs and less amount of delay. Besides, being
reversible will enjoy low energy dissipation, simple testability
and increased fault detection features. Further, the multi-
function feature of the gate has also been demonstrated in this
paper.
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CISME Vol. 2 Iss. 4 2012 PP. 8-18 www.jcisme.org

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