COM203P Introduction to Computer Organization Practice

Project Work

Problem Statement

Design single core 64-bit processor with the following specifications.

32-numbers of 64-bit registers.
Three internal bus based processors, where bus A and bus B as input ports to the ALU and bus C
is connected to output of ALU.
Design 64-bit logic and unsigned arithmetic circuit.
Design Single precision floating point unit.
Design 64-bit Logic unit.
Design Load and Store unit.
Processor has 64-bit data line and 22-bit address line.
Instruction format size is 32-bit.
Instruction register size is 32-bit and Program counter size is 22-bit.

2
2.1

Design Approach
Logic and Arithmetic Circuit Design

Design the logic and arithmetic circuits as follows:

2.2

Addition

Design 64-bit Carry Lookahead Adder circuit using KGP blocks and Recursive doubling algorithm. Now
use the same module for the design of the addition, addition with carry, subtraction and subtraction with
barrow modules.

2.3

Multiplication

Design the 64-bit Wallace Tree multiplier (or Array multiplier) using carry-save-adders.

2.4

Floating Point Arithmetic Unit

Design Single precision floating addition, subtraction and multiplication circuit, where adder can be designed using carry lookahead adder and multiplier can be either Wallace tree multiplier or Array multiplier.

3
3.1

Instruction format and Encoding

Instruction Format

The design instruction should of 32-bit size. Load and Store Instruction will have the format as shown in
Figure 1. The rest of the logic and arithmetic instructions will have the format as shown in Figure 2.

Figure 1: Instruction format for Load and Store Instructions

Figure 2: Instruction format for Arithmetic and Logic Instructions

3.2

Operation code Encoding

Encode the instruction opcode as follows:

Operation Description
Code
00000
Addition
00001
Addition with carry
00010
Subtraction
00011
Subtraction with Barrow
00100
Multiplication
00101
Floating Point Addition (Single Precision)
00110
Floating Point Subtraction (Single Precision)
00111
Floating Point Multiplication (Single Precision)
01000
Logical bit wise AND
01001
Logical bit wise OR
01010
Logical bit wise XOR
01011
Logical bit wise NAND
01100
Logical bit wise NOR
01101
Logical bit wise XNOR
01110
Logical NOT
01111
Negation (twos complement value)
10000
Load
11000
Store

Processor Architecture

The designed processor architecture is as shown in the Figure 3.

Usage
ADDRdst , Rsrc2 , Rsrc1
ADCRdst , Rsrc2 , Rsrc1
SU BRdst , Rsrc2 , Rsrc1
SBBRdst , Rsrc2 , Rsrc1
M U LRdst , Rsrc2 , Rsrc1
F ADDRdst , Rsrc2 , Rsrc1
F SU BRdst , Rsrc2 , Rsrc1
F M U LRdst , Rsrc2 , Rsrc1
AN DRdst , Rsrc2 , Rsrc1
ORRdst , Rsrc2 , Rsrc1
XORRdst , Rsrc2 , Rsrc1
N ADDRdst , Rsrc2 , Rsrc1
N ORRdst , Rsrc2 , Rsrc1
XN ORRdst , Rsrc2 , Rsrc1
N OT Rdst , Rsrc1
N EGRdst , Rsrc1
LOADRdst , Address(22 bit)
ST ORERdst , Address(22 bit)

Figure 3: Processor Architecture