Launch-on-Shift-Capture Transition Tests

Intaik Park and Edward J. McCluskey

Center for Reliable Computing, Stanford University, Stanford, USA

Abstract

places timing requirements on the routing of scan-enable

signal.

The two most popular transition tests are launch-on-shift

(LOS) test and launch-on-capture (LOC) test. The LOS
and LOC tests differ in their launch mechanisms, creating
their own pros and cons. In this paper, new hybrids of
LOS and LOC tests that launch transitions using both
launch mechanisms are introduced. The new transition
tests improved fault coverage without significant test
length penalty. This paper presents the concepts and
pattern generation methods of these new transition tests
as well as experimental results that demonstrate the
benefits of these tests.

Figure 1. The concept and waveforms of LOS

1. Introduction
The transition test [Waicukauski 87] is one of the most
widely used techniques to ensure the correct temporal
behavior of the manufactured integrated circuits (ICs). It
consists of a pair of vectors (V1,V2). The first vector, V1,
initializes a logic value at a fault site (a node in a network).
Then, the second vector, V2, launches a transition of logic
values (01 or 10) at the fault site and propagates the
transition to an observable point (a scan flip-flop or a
primary output).
Transition tests are categorized by how they launch
transitions: launch-on-shift (LOS), launch-on-capture
(LOC), and enhanced-scan transition tests. LOS and LOC
tests do not require any additional hardware while the
enhanced-scan transition test requires special types of
scan flip-flops to apply the test vectors [Dasgupta 81].
The enhanced-scan transition is not considered in this
paper; the focus is only on the first two types of transition
tests.
The launch-on-shift (LOS) test launches a transition of a
logic value by the last clock pulse of the scan shift
operation [Eichelberger 91, Savir 92], followed by a
system clock pulse that captures the transition. Figure 1
illustrates the concept of LOS testing along with the
waveforms of clock signal (clk) and scan-enable signal
(SE).
The time period between the launch clock pulse (cp1) and
the capture clock pulses (cp2) determines the test
application frequency. Note that the scan-enable signal
must fully transition during this time period, and this

Figure 2. The concept and waveforms of LOC

Several methods exist to mitigate the timing requirements

on the scan-enable signal of LOS testing. Level Sensitive
Scan Design (LSSD) requires two fast clock signals that
could be used to launch and capture transitions
[Eichelberger 77]. Another method involves locally
generating fast scan-enable signals for LOS testing
[Ahmed 06, Wang 04]. For the rest of the paper, we
assume that the designs considered in this work have
capabilities to apply LOS test.
The launch-on-capture (LOC) transition test launches a
transition through a logic network which is controlled by
system clock pulses [Eichelberger 91, Savir 94]. In LOC
testing, both launch and capture vectors are initiated by
system clock pulses. The concept and waveforms of the
LOC test are described in Fig. 2.
In Fig.s 1 and 2, it should be noticed that the second clock
pulse (cp2) of LOS and both clock pulses (cp1 and cp2) of
LOC are system clock pulses. In addition, the LOC test
procedure also requires the scan shift operations and
inherently contains the last scan shift clock pulse.
However, unlike LOS test, the last shift of LOC need not
be applied at fast speed.

Paper 35.3
INTERNATIONAL TEST CONFERENCE
1-4244-4203-0/08/$20.00 2008 IEEE

Therefore, if an additional system clock pulse is appended

to the LOS test and the last shift clock of the LOC test is
applied at fast speed, the test applications of both tests are
identical. This introduces the mix of these two test
methods, or hybrids of LOS and LOC: launch-on-shiftcapture (LOSC) test and launch-on-capture-shift (LOCS)
test.
The launch-on-shift-capture (launch-on-capture-shift) test
is a three-pattern test for transition faults that launches
transitions by both launch-on-shift and launch-on-capture
mechanisms. The concepts of LOSC and LOCS tests and
their signal waveforms are illustrated in Fig. 3. LOSC
(LOCS) tests consist of three vectors (V1,V2,V3). The first
vector (V1) initializes a logic value at a fault site as in
LOS. Then the second vector (V2) launches a transition
and propagates it. At the same time, V2 also initializes a
logic value at a different fault site in a way the first vector
of LOC does. Finally, the third vector (V3) performs two
things; 1) it propagates the fault effect launched by vector
pair (V1,V2), and 2) it launches a transition initialized by
V2 and propagates it.

Figure 3. The concept and waveforms of LOCS and LOSC

LOSC and LOCS are identical in terms of test application

(last shift clock pulse followed by two system clock
pulses), but differ in how they are generated. LOSC test
is made by generating LOS test first with dont-care bits
unspecified. These dont-care bits are filled with LOC
test. LOCS test is generated in the same way, but the
LOC test is generated first before LOS test is used to fill
the dont-care bits.
The dont-care bits are exploited in the context of test set
compaction [Goel 79], test data compression [Hiraide 03],
or power reduction during scan shift operations [Cho 07].
LOSC and LOCS share the same concept with the
compaction scheme; they utilize dont-care bits to detect
additional faults. However, LOSC and LOCS differ from
existing compaction methods. LOSC (LOCS) targets
additional faults either by LOC or LOS, whichever is
easier, while compaction uses only one method to test
additional faults. Therefore, in LOSC and LOCS, LOSuntestable faults can be tested by LOC and LOCuntestable faults by LOS. On the other hand, conventional
compaction techniques leave untestable faults undetected.
The rest of the paper is organized as the following.
Section 2 discusses the limitations of conventional

Paper 35.3

transition tests and previous works on the hybrids of LOS

and LOC. Section 3 describes the test generation methods.
Section 4 presents the experimental setup and results on
benchmark circuits. Section 5 discusses the benefits and
limitations. Finally, Sec. 6 concludes the paper.

2. Previous works
In this section, possible problems related to the two
transition test approaches as well as previous researches to
alleviate these problems are introduced.
2.1. Untestable faults
LOC test usually achieve lower fault coverages than LOS
test.
In many cases, it is due to functionally
unsensitizable faults that are not tested by LOC [Savir 94,
Rearick 01]. Many of these faults can be tested under
LOS since it does not launch transitions through a
functional logic network. The detection of these faults by
LOS methods is suspected to cause over-testing (rejecting
good devices by falsely testing under environments that
would not happen in functional mode). Nevertheless, it is
also shown that some of these faults are testable by LOC
when more than two clock pulses are used for fault
activation and propagation [Abraham 06, Zhang 06].
On the other hand, LOS test does not always achieve
100% fault coverage. There are also untestable faults in
LOS testing as described in [Zhang 07]. Some of these
faults are untestable due to shift-dependency, but may
actually fail the system operation if present. To reduce
the number of LOS untestable faults, scan chain
reordering or test-point insertion techniques were
developed [Li 05, Gupta 03, Wang 03]. It is also
noticeable that some of these faults may be detected under
LOC test approach [Zhang 06].
2.2. Hybrids of LOS and LOC
As discussed above, LOS-untestable faults may be tested
by LOC while LOC-untestable faults may be tested by
LOS. Naturally, there have been efforts to combine the
advantages of both testing methods [Ahmed 06, Wang 04,
Devtaprasanna 05].
In [Ahmed 06, Wang 04], circuits are partitioned into two
regions. One region is controlled by slow scan-enable
signals to be tested by LOC test. The other region is
controlled by locally generated fast scan-enable signals
and tested by LOS test.
These methods partition circuits into many regions by a
controllability measure or a developed cost function. The
quality of the partitioning determines the effectiveness of
the methods. Also, under these methods, portions of
circuits are tested solely by LOS while other parts are
tested by LOC only. Therefore, LOS-untestable faults in
LOS-tested regions and LOC-untestable faults in LOC-

INTERNATIONAL TEST CONFERENCE

tested regions are still uncovered. On the other hand,

LOSC and LOCS do not depend on partitioning of
circuits and they can detect faults by either LOC or LOS,
whichever is easier.
Another approach was to implement multiple scan-enable
signals [Devtaprasanna 05]. These scan-enable signals do
not require fast switching capability, but are controlled
separately. Hence, while some scan-enable signals are
de-asserted to perform LOC test, other scan-enable
signals are kept high, keeping flip-flops in the shift mode.
Therefore, some flip-flops perform launch and capture
while other flip-flops only launch transitions by shift
operations.
In this method, a fault can be tested either by LOS or
LOC. However, when some faults are tested by one test
method, other faults in the same scan-enable region have
to be tested by the same method in one test pattern. On
the other hand, LOSC and LOCS can test faults in
different methods simultaneously, which may increase the
efficiency of a test pattern.

3. Test pattern Generation

To generate LOSC and LOCS tests, Automatic Test
Pattern Generator (ATPG) tools for LOS and LOC test
are required. LOC ATPG can be used directly without
any modifications, but LOS ATPG requires a slight
modification.
Unlike the conventional LOS test where fault effects are
propagated only one time frame, the LOS test for LOSC
and LOCS propagates fault effects over two time frames.
However, in this paper, to generate LOS test with two
system clocks without modifications to the existing ATPG,
the netlists of the circuits were unrolled to emulate
iterative networks of the circuits. The iterative network is
a form that emulates multiple time frames of the circuit
operation [McCluskey 58]. Using the unrolled netlists,
conventional LOS ATPG could be used directly to
generate LOSC and LOCS.
The test generation flow is shown in Fig. 4 as a pseudocode. Note that the LOC test generation and fault
simulation in the procedure use regular netlists while the
LOS test generation and fault simulation use unrolled
netlists.
The generation of LOSC and LOCS consists of two
ATPG processes: the primary ATPG and the secondary
ATPG. The primary ATPG is an ATPG process that
generates test patterns without any restrictions. The
patterns generated by the primary ATPG contain dontcare bits that are not specified. For LOSC (LOCS), the

Paper 35.3

primary ATPG produces test that launches transition by

LOS (LOC) method.
Test generation flow (pseudo-code)
While ( undetected fault exists )
{
Primary LOS (LOC) ATPG
Extract care bits of LOS (LOC) pattern
Secondary LOC (LOS) ATPG
(with care bits from LOS (LOC) pattern)
Fault simulate in LOS (LOC) method
(with dont-care bits filled by LOC (LOS))
}
Figure 4. LOSC and LOCS test generation flow

The secondary ATPG is another ATPG process that

exploits the unspecified bits of the test patterns from the
primary ATPG to test additional faults. It can be regarded
as a way to fill dont-care bits of existing test pattern. To
keep the original care bits from the primary ATPG result
during the secondary ATPG process, these care bits are
extracted and used as constraints during the secondary
ATPG. If there are dont-care bits left after the secondary
ATPG process, they are filled pseudo-randomly. In
LOSC (LOCS) test, the secondary ATPG uses LOC
(LOS) method.
The resulting test pattern is fault simulated again in LOS
(LOC) method. This is necessary to identify additional
LOS (LOC) detection by the care bits from the secondary
ATPG.
The iterative network for LOS ATPG would contain twice
as many faults as in the original network. To prevent
falsely testing faults in the second time frame, only faults
that belong to the first time frame are considered in LOS
ATPG.
Table 1. Benchmark circuits

circuit

Gate count

FF count

s13207

7,951

625

11,940

s15850
s38417
s38584
b17
b18
b19

9,772
22,179
19,253
12,949
35,884
69,437

513
1,564
1,275
1,314
3,014
6,030

14,738
43,032
47,074
95,328
263,746
511,140

b20
b21

7,390
7,583

430
430

55,542
56,418

b22

11,135

613

83,664

INTERNATIONAL TEST CONFERENCE

No. of Faults

Table 2. Test pattern counts and fault coverages of test sets

circuit

LOS
length

LOSC
cov

Length

cov

length

LOCS
cov

length

cov

s13207

179

99.62%

140

99.66%

114

82.85%

98

93.22%

s13580
s38417
s38584
b17
b18
b19
b20
b21

148
257
171
1,305
4,521
9,602
1,240
1,199

99.73%
98.12%
99.80%
81.27%
84.91%
84.33%
96.12%
96.17%

137
191
208
1,264
4,404
6,400
1,446
1,475

99.87%
99.76%
99.87%
87.52%
89.29%
88.35%
96.80%
96.63%

148
293
504
1,584
5,002
8,365
1,484
1,464

71.10%
95.32%
80.97%
69.52%
67.13%
67.03%
88.25%
87.40%

131
278
384
1,579
4,910
8,223
1,490
1,329

81.12%
95.66%
87.08%
68.96%
67.71%
67.37%
88.61%
87.15%

b22

1,413

96.47%

1,692

96.77%

1,583

84.48%

1,604

84.89%

of the test sets. In each row, the shortest test length and
the highest fault coverage are bold-faced.

4. Experimental Results
We evaluated the test length and fault coverage of LOSC
and LOSC tests on some of ISCAS89 and ITC99
benchmark circuits shown in Table 1.
To attain the most efficient LOSC or LOCS test sets,
single test pattern should be generated by the primary
ATPG and filled by the secondary ATPG before the next
pattern is considered. In this way, the primary ATPG for
the next pattern would not target faults that could be
detected by the secondary ATPG for the previous pattern.
However, the commercial ATPG tool is highly optimized
for compaction. Due to the optimization, when the ATPG
tool generates one test pattern at a time and repeats until
all the faults are tested or tried, the resulting test length
was abnormally longer than a test generated at once by the
same ATPG tool. It is unfair to compare our approach
with the LOS and LOC generated at once due to the
optimization performed on the latter. Thus, we settled
with something in between the two extreme cases.
For the purpose of fair comparison, all the test sets in this
paper were generated in a group of 32 patterns, so that
both the proposed approach (LOSC and LOCS) and the
base case (LOS and LOC) do not benefit from the
optimization of the ATPG tool.
In addition, all the test patterns were generated with the
default backtracking limit (abort limit of 10) and the
default compaction option (high compaction).
4.1. LOSC and LOCS test sets
LOSC and LOCS test sets were generated as described
above. They are compared with LOS and LOC test sets in
terms of test length and fault coverage in Table 2. In this
table, columns under label length represent test length
and columns labeled as cov represent the fault coverages

Paper 35.3

LOC

Table 2 shows that LOSC tests achieved the highest fault

coverage. However, the test length of LOSC was
comparable to LOS test or shorter than LOS test in some
cases.
LOCS performs better than LOC, but worse than LOS and
LOSC. That is because the LOCS test generation
terminates when the primary LOC ATPG cannot produce
any more tests for undetected faults, without invoking the
secondary LOS ATPG even though some of these faults
could be tested by LOS.
The CPU time required to generate these test sets were not
considered in this experiment. The commercial ATPG
tool is optimized to generate pure LOS or LOC tests, but
the generation of LOSC and LOCS tests requires
invocations of both LOS and LOC ATPGs. In addition,
the implementation of LOSC and LOCS is not integrated
into the ATPG tool, but it is rather an augmented form.
Therefore, in this work, the qualities of the test sets are
compared without considering the test generation time.
4.2. Fault Coverage
LOSC and LOCS tests achieve higher fault coverage
compared to LOS and LOC respectively.
These
improvements in fault coverage are due to the
undetectable faults under one method (LOC or LOS)
being detected by the other method. Table 3 summarizes
undetected faults in each method. Column 2 shows the
total number of faults in each circuit. Column 3 and 4
represent undetected faults by LOS and LOC test
respectively. Column 5 shows the number of undetected
faults after applying both LOS and LOC. Finally, column
6 and 7 represents undetected faults of LOSC and LOCS
test respectively. In each row, the entries with the fewest
undetected faults are bold-faced.

INTERNATIONAL TEST CONFERENCE

Table 3. Undetected faults of each test method

LOS

LOC

11,940
14,738
43,032
47,074
95,328
263,746
511,140
555,42
56,418

45
38
900
94
17,437
40,231
81,175
2,176
2,167

2,047
4,255
1,926
8,929
28,726
85,672
169,142
6,484
7,067

38
21
122
63
11,641
26,029
53,981
1,752
1,802

40
20
102
63
11,871
28,766
54,439
1,783
1,871

810
2,782
1,824
6,082
29,592
85,158
166,789
6,328
7,249

83,664

2,874

12,872

2,614

2,709

12,642

b22

In most cases, the combination of LOS and LOC had the

fewest undetected faults, or the most detected faults.
Table 3 shows that some of LOS undetected faults were
detected by LOC test and the some of LOC undetected
faults by LOS test. Hence, when both LOS and LOC tests
were applied, the number of undetected faults was the
least. However, it should be noticed that LOSC detected
the comparable number of faults to the combination of
LOS and LOC.
To show the portion of LOS detected faults and LOC
detected faults in LOSC test, the numbers of faults in each
category of b17 and b18 circuits are plotted in Fig. 5 and
Fig. 6 respectively.

LOS+LOC

LOSC

test set and LOC detection is insignificant in the

beginning of the test set. However, at certain points (at
pattern number 992 in Fig. 5 and at pattern number 1,312
in Fig. 6), the number of LOC detected faults increases
while additional LOS detection is minimal.
100.00%
95.00%
90.00%
85.00%
80.00%
75.00%

Pattern Number

80,000

Figure 7. Dont-care bit percentages of test patterns (b17)

4384

4128

3872

3616

80.00%
3360

Figure 5. LOSC test - detected faults by LOS and LOC (b17)

85.00%

3104

1152 1312 1472

2848

992

2592

832

2336

672

Pattern Number

2080

512

1824

352

1568

192

1312

32

90.00%

800

20,000

95.00%

1056

loc detect
los detect

30,000

100.00%

32

40,000

544

50,000

288

60,000

% don't-care bits

Detected Faults

70,000

Pattern Number

225000
205000

Detected Faults

LOCS

32
12
8
22
4
32
0
41
6
51
2
60
8
70
4
80
0
89
6
99
2
10
88
11
84
12
64

total faults

% don't-care bits

circuit
s13207
s15850
s38417
s38584
b17
b18
b19
b20
b21

Figure 8. Dont-care bit percentages of test patterns (b18)

185000
165000
145000
125000
105000

LOC detect
LOS detect

85000
65000
45000
32

320 608 896 1184 1472 1760 2048 2336 2624 2912 3200 3488 3776 4064 4352

Pattern Number

Figure 6. LOSC test - detected faults by LOS and LOC (b18)

In Fig.s 5 and 6, it is shown that the LOS detected faults

are the majority of detected faults throughout the entire

Paper 35.3

It is well known that, in the last phase of test pattern

generation, a significant number of patterns is required to
gain the last small portion of fault coverage [McCluskey
89]. The patterns generated at the end are less efficient, or
contain many dont-care bits, which give the secondary
ATPG more freedom to produce tests for additional faults.
The percentages of dont-care bits in scan loads of the
primary ATPG (LOS) generated test patterns in LOSC are
plotted in Fig.s 7 and 8. In these figures, each column
shows the average percentage of dont-care bits of 32 test

INTERNATIONAL TEST CONFERENCE

patterns, which would be fed to the secondary ATPG to

generate additional LOC tests.

count can be decreased if they are targeted by LOC ATPG

instead of LOS ATPG.

The test patterns contain many dont-care bits (over 95%

of a scan load) starting from pattern number 992 in Fig. 7
and pattern number 1,312 in Fig. 8. Notice the points
where the percentages of dont-care bits increase and
where the LOC detection increases (Fig. 5 and Fig. 6) are
aligned.

Even though LOSC test achieved higher fault coverage

compared to LOS test, the longer test length is not
desirable. To fairly compare the test length and fault
coverage of LOSC and LOS, the fault coverage of both
tests were plotted in Fig. 9 and Fig. 10.

Table 4. Comparison on LOS of original and unrolled circuit

circuit

LOS

LOS Unroll

LOSC
Pat

fc (%)

80%
70%
60%
50%
LOSC

40%

LOS

30%
32

352

672

992

1312

Pattern Number

Figure 9. Fault coverage comparison of LOS and LOSC (b17)

Fault Coverage

The increased test length of LOSC over LOS is suspected

to be caused by the two-time-frame propagation
requirements of LOS test used in LOSC. To verify this
assumption, LOS test sets generated for original circuits
and the unrolled circuits (faults propagated over two time
frames) are compared in Table 4.

Fault Coverage

90%

4.3. Test Set Length

LOCS test were shorter and achieved higher fault
coverage than LOC test. However, the fault coverage of
LOCS test was still lower than LOS or LOSC test. On the
other hand, LOSC test improved fault coverage of LOS
test, but it sometimes resulted in longer test length.

100%
90%
80%
70%
60%
50%
40%
30%
20%

length

fc (%)

Length

fc (%)

s13207

172

99.63

217

99.61

140

99.66

s13580

152

99.74

184

99.69

137

99.87

s38417

257

98.08

293

98.24

191

99.76

s38584

173

99.80

206

99.80

208

99.87

B17

1,305

81.27

1,654

81.17

1,264

87.52

B18

4,521

84.91

5,773

83.38

4,404

89.29

Figure 10. Fault coverage comparison of LOS and LOSC (b18)

B19

9,602

84.33

11,823

82.76

6,400

88.35

B20

1,240

96.12

1,258

95.13

1,446

96.80

B21

1,199

96.17

1,218

95.42

1,434

96.69

B22

1,413

96.47

1,617

95.64

1,692

96.77

In these figures, the fault coverage of LOS is higher than

LOSC at the first portion of the test set. But, in the later
part of the test set, LOSC achieves higher fault coverage
than LOS. The cross-over points are at pattern number
992 in Fig. 9 and pattern number 1,056 in Fig. 10. These
points are the same or very close to where the number of
dont-care bits (Fig.s 7 and 8) and the LOC fault
detections are increased (Fig.s 5 and 6).

In Table 4, columns under length represent the test

lengths and columns under fc show the fault coverages.
The test lengths for the unrolled circuits were always
longer than the tests for the original circuits. However,
LOSC tests were usually shorter than LOS for unrolled
circuits and sometimes even shorter than LOS for original
circuits. This is when the additional fault detection by
LOC in LOSC test compensated the test length penalties
from the two-time-frame propagations of unrolled LOS.
The test length reduction of LOSC over unrolled LOS can
also be coming from the mixed use of LOS and LOC. As
discussed above, a significant number of patterns are used
to test hard-to-detect faults at the end of test generations.
However, hard-to-detect faults in LOS are not necessarily
hard-to-detect in LOC. When this is the case, the pattern

Paper 35.3

LOSC
LOS
32

672

1312

1952

2592

3232

3872

4512

Pattern Number

If the highest possible fault coverage is desired, LOSC

test is better than LOS test. If the test length is the
concern and the test has to be truncated, LOSC has higher
fault coverage as long as the test set is truncated after the
cross-over point (pattern number 992 of b17 LOSC test
and pattern number 1,056 of b18 LOSC test).
4.4. Launch-on-shift with Launch-on-capture top-off
We think that LOSC and LOCS tests achieved higher fault
coverages because they use both LOS and LOC methods.
Hence, it would be natural to compare LOSC tests with
combinations of LOS and LOC tests.

INTERNATIONAL TEST CONFERENCE

LOS test achieved higher fault coverage and shorter test

length than LOC test. However, like all the transition test
generations, LOS test generation becomes inefficient
when only hard-to-detect faults are left and many patterns
are required to detect these faults to improve the last
portion of the fault coverage. Therefore, it may be
beneficial to switch to LOC test at certain point and
generate top-off LOC patterns, which test hard-to-detect
faults of LOS testing using LOC test.

Secondly, the more dont-care bits in a test pattern, the

better the secondary LOC ATPG performed, detecting
more faults by the LOC method.

5. Discussions
The benefits of LOSC and LOCS tests are as the
followings. First, they target untestable faults under one
method (LOS or LOC) using the other method, improving
fault coverage. Secondly, hard-to-detect faults in one
method may be east-to-detect in the other method. Hence,
testing each fault using the easier way can improve the
efficiencies of test patterns, which may decrease test
length. Lastly, they can be implemented on top of
existing ATPG with compaction, leading to more efficient
use of dont-care bits.

To compare this idea with LOSC test sets, LOS tests were
topped-off with LOC tests at four different points. Each
group of 32 patterns were fault simulated during the LOS
test generation and when the increase of the fault coverage
by the last 32 pattern was 1) less than 1%, 2) less than
0.5%, 3) less than 0.2%, and 4) less than 0.1%, the LOS
test generation stopped and LOC test generation started on
the remaining undetected faults. The resulting test sets
are shown in Table 5.

LOSC and LOCS tests also have limitations. First, they

require fast switching scan-enable signals. However, even
without the fast SE signal, a LOCS test set has an
advantage over a conventional LOC test. The LOS fault
activation mechanism initiates transitions of logic values
at fault sites and propagates the fault effects. This is
analogous to a test for stuck-open faults when they are not
applied at-speed. Hence, LOCS would have higher stuckopen fault coverage than LOC.

In Table 5, the test with the highest fault coverage is boldfaced. LOSC test always achieved the highest fault
coverage. LOS tests topped-off with LOC tests achieved
comparable fault coverages to LOSC test sets, but with
more test patterns.
4.5. Experimental Result Summary
LOSC and LOCS showed higher fault coverage than LOS
and LOC tests respectively. LOSC test sets were
sometimes longer and sometimes shorter than LOS tests
while LOCS achieved more compact test than LOC test in
most cases.

Secondly, the LOS test in LOSC (LOCS) needs to

propagate fault effects over two time frames rather than
one time frame of the conventional LOS test, which
penalizes the test length. However, when combined with
LOC, LOSC and LOCS performed the same or the better
in terms of fault coverage and/or test length compared to
pure LOS, which justifies the use of two time frames.

Given the higher fault coverages of LOSC test set, aspects

that affect the LOSC test length were investigated. First,
when LOS fault coverage is relatively low (or more room
to improve fault coverage), LOSC test set achieved better
compaction with significant fault coverage improvement.
Table 5. LOS test topped-off with LOC test
LOS+LOC
LOS (orig)
(<1%)
circuit

In this paper, possible improvements of LOS and LOC

transition tests in terms of test length and fault coverage
were investigated. However, the quality of the test set is
not only measured by these two metrics. Other ways to

LOS+LOC
(<0.5%)

length

fc (%)

length

fc (%)

s13207

172

99.63

144

99.47

144

99.47

s13580

152

99.74

107

97.21

145

99.46

s38417

257

98.08

189

99.08

231

s38584

173

99.80

177

98.31

238

b17

1,305

81.27

1,090

83.99

b18

4,521

84.91

3,142

b19

9,602

84.33

5,396

b20

1,240

96.12

b21

1,199

96.17

b22

1,413

96.47

Paper 35.3

length

fc (%)

LOS+LOC
(<0.2%)
length

LOS+LOC
(<0.1%)

fc (%)

length

144

99.47

NA

145

99.46

99.49

231

99.49

99.63

238

99.63

238

1,330

85.83

1,563

86.90

1,680

84.42

3,518

87.21

3,823

88.20

81.26

5813

84.53

6,257

86.22

1,103

95.11

1,154

95.30

1,464

1,065

93.99

1,293

95.15

1,671

1,070

93.18

1,253

94.43

1,572

fc (%)

LOSC
length

fc (%)

NA

140

99.66

99.46

137

99.87

NA

191

99.76

99.63

208

99.87

87.11

1,264

87.52

3,990

88.47

4,404

89.29

6,382

86.53

6,400

88.35

96.11

1,830

96.62

1,446

96.80

96.30

1,795

96.54

1,434

96.69

95.60

1,867

96.57

1,692

96.77

145
NA

INTERNATIONAL TEST CONFERENCE

improve the transition test quality include applying the

concept of TARO (Transition fault propagated to All
Reachable Outputs) [Tseng 01, Park 05], N-detect [Ma
95] or employing multiple clock cycles [Zhang 06].
The idea of mixing two different tests in one test pattern
should not be limited to the hybrids of LOC and LOS.
Previous researchers have shown the importance of using
multiple test metrics to test manufactured ICs [Maxwell
93, Nigh 97, Ferhani 06]. The hybrid concept of LOSC
can be extended to the mix of different test metrics for this
purpose. As long as dont-care bits are available in test
patterns, they can be exploited to generate additional tests
for different metrics. For example, LOC and single stuckat fault test or single stuck-at test and bridge fault test can
be combined.

6. Conclusion
In this paper, Launch-on-Shift-Capture and Launch-onCapture-Shift tests are introduced. These tests exploits
dont-care bits of existing LOS (LOC) test set to detect
additional faults by LOC (LOS) launch mechanism, which
may be more efficient for some faults. Experimental
results showed that LOSC test achieved higher fault
coverage than any other test or mix of test sets.

7. Acknowledgments
We thank Rohit Kapur of Synopsys, Brion Keller of
Cadence and Samy Makar of C-Switch for their helpful
discussions and support. We thank all the members of
CRC for their help.

8. References
[Abraham 06] J. Abraham, U. Goel, A. Kumar, Multi-Cycle
Sensitizable Transition Delay Faults, Proc. VLSI Test
Symp., 2006.
[Ahmed 06] N. Ahmed, M. Tehranipoor, Improving Transition
Delay Test Using a Hybrid Method, IEEE Design & Test,
vol. 23, issue 5, pp. 402-412, 2006.
[Avramovici 92] M. Abramovici, P. S. Parikh, Warning: 100%
Fault Coverage May Be Misleasing!, Proc. Intl. Test.
Conf., pp. 662 671, 1992.
[Butler 04] Butler, K. M., et al., Minimizing Power
Consumption in Scan Testing: Pattern Generation and
DFT Techniques, Proc. Intl. Test Conf., pp. 355-364,
2004.
[Cho 07] K.Y. Cho, S. Mitra, and E. J. McCluskey, California
Scan Architecture for High Quality and Low Power
Testing, Proc. Intl Test Conf., 2007.
[Dasgupta 81] S. Dasgupta, R. G. Walther, T. W. Willams and E.
B. Eichelberger, An Enhancement to LSSD and Some
Applications of LSSD in Reliability, Availability and
Serviceability, Proc. FTCS, pp. 880-885, 1981.
[Devtaprasanna 05] N. Devtaprasanna, A. Gunda, P.
Krishnamurthy, S. M. Reddy and I. Pomeranz, A Novel
Method of Improving Transition Delay Fault Coverage

Paper 35.3

Using Multiple Scan Enable Signals, Proc. ICCD, pp.

471-474, 2005.
[Eichelverger 77] Eichelberger, E. B. and T. W. Williams, A
Logic Design Structure for LSI Testability, Proc. Design
Automation Conf., pp. 462-468, 1977.
[Eichelberger 91] Eichelberger, E. B., E. Lindbloom, J. A.
Waicukauski and T. W. Williams, Delay-Fault
Simulation, Structured Logic Testing, McCluskey (Ed.),
Prantice-Hall, Inc., Englewood Cliffs, New Jersey, 1991.
[Ferhani 06] F.-F. Ferhani and E. J. McCluskey, Classifying
Bad Chips and Ordering Test Sets, Proc. Intl Test Conf.,
pp. 1-10, 2006.
[Goel 79] P. Goel and B. C. Rosales, Test Generation &
Dynamic Compaction of Tests, Dig. Papers Test Conf.,
pp. 182-192, 1979.
[Gupta 03] P. Gupta, et. al., Layout-Aware Scan Chain
Synthesis for improved Path Delay Fault Coverage, Proc.
ICCAD, pp. 754-759, 2003.
[Hiraide 03] Hiraide, T., et al., BIST-aided Scan Test A new
Method for Test Cost Resutction, Proc. VLSI Test Symp.,
pp. 359-364, 2003.
[Li 05] W. Li, et. al., Distance Resticted Scan Chain Reordering
to Enhance Delay Fault Coverage, Proc. Intl Conf. VLSI
Design, pp. 471-478, 2005.
[Ma 95] S. C. Ma, P. Franco, and E. J. McCluskey, An
Experimental Chip to Evaluate Test Techniques
Experiment Results, Proc. Intl. Test Conf., pp. 663-672,
1995.
[Maxwell 93] P. C. Maxwell and R. C. Aitken, Test Sets and
Reject Rates: All Fault Coverages are Not Created Equal,
IEEE Design & Test, pp. 42-51, 1993.
[McCluskey 58] E. J. McCluskey, Iterative Combinational
Switching Networks General Design Considerations,
IRE Trans. Elctron. Comput., Vol. EC-7., pp. 285-291,
1958.
[McCluskey 89] E. J. McCluskey and F. Buelow, IC Quality
and Test Transparency, Trans. IEEE Industrial
Electronics, vol. 36, no. 2, May, 1989.
[Nigh 97] P. Nigh, W. Needham, K. Butler, P. Maxwell, R.
Aitken, and W. Maly, So What is an Optimal Test Mix?
A Discussion of the SEMATECH Methods Experiment,
Proc. Intl Test Conf., pp. 1037-1038, 1997.
[Park 05] I. Park, A. Al-Yamani, E. J. McCluskey, Effective
TARO pattern generation, Proc. VLSI Test Symp., pp.
161-166, 2005.
[Rearick 01] J. Rearick, Too much delay fault coverage is a bad
thing, Proc. Intl Test Conf., pp. 624-233, 2001.
[Savir 92] J. Savir, Skewed-Load Transition Test: Part I,
Calculus, Proc. Intl. Test Conf., pp 705-714, 1992.
[Savir 94] J. Savir and S. Patil, Broad-side delay test, IEEE
trans. On CAD of IC and System, vol. 13, pp. 1057-1064,
1994.
[Tseng 01] C. W. Tseng and E. J. McCluskey, Multiple-output
propagatioin transition fault test, Proc. Intl. Test Conf.,
pp. 358-366, 2001.
[Wang 03] S. Wang and S. T. Chakradhar, Scalable Scan-Path
Test Point Insertion Technique to Enhance Delay Fault
Coverage for Standard Scan Designs, Proc. Intl. Test
Conf., pp. 574-583, 2003.
[Wang 04] S. Wang, X. Liu, S. T. Chakradhar, Hybrid delay
scan: a low hardware overhead scan-based delay test
technique for high fault coverage and compact test sets,

INTERNATIONAL TEST CONFERENCE

Proc. Deaign Automation and Test in Europe, vol. 2. pp.

1296-1301, 2004
[Waicukauski 87] J. Waicukauski, et. al., Transition Fault
Simultaion, IEEE Design and Test, pp. 32-38, April 1987.
[Zhang 06] Z. Zhang, et. al., Scan Tests with Multiple Fault
Activation Cycles for Delay Faults, Proc. VLSI Test
Symp., 2006.
[Zhang 07] Z. Zhang, S.M. Reddy, I. Pomeranz, Warning:
Launch off Shift tests for Delay Faults May Contribute to
Test Escapes, Proc. Asia and South Pacific Design
Automation Conf., 2007.

Paper 35.3

INTERNATIONAL TEST CONFERENCE