ANALYSIS AND MITIGATION OF CMOS GATE LEAKAGE

Rahul M. Rao, Richard B. Brown

University of Michigan, Ann Arbor
{rmrao, brown@eecs.umich.edu}

Kevin Nowka, Jeffrey L. Burns

IBM Austin Research Laboratory
{nowka, jlburns@us.ibm.com}

ABSTRACT
Conventional leakage reduction techniques focus
primarily on sub-threshold leakage mitigation, while
neglecting the effect of gate leakage current. This work
focuses on understanding gate leakage current and
developing circuit techniques for total leakage
minimization. We present an efficient technique for
gate leakage of CMOS circuits. Input vector control
and circuit reconfiguration techniques for total leakage
minimization of static and dynamic circuits are
presented. Finally design guidelines for optimal device
size selection for stacked sleep devices in an enhanced
MTCMOS configuration are presented.
Keywords: Leakage, gate leakage, estimation, sleep-state,
transistor stacks, dynamic circuits, MTCMOS.

1. INTRODUCTION
In recent years, the aggressive scaling of device
dimensions and threshold voltage has significantly
increased sub-threshold leakage and its contribution to the
total chip power consumption. Also, gate oxide thickness
has been scaled to maintain adequate control of the
channel by the gate. This has resulted in an alarming
increase in gate leakage current due to tunneling through
the thin gate oxide. Gate leakage is expected to be a major
component of leakage in future technology generations and
has been identified as one of the most important challenges
to future device scaling [1]. Gate leakage power, which
was almost non-existent in the previous technology
generations, is expected to contribute more than 15% to
the total chip power dissipation in the current technology
generation as shown in Fig. 1.
Gate leakage is primarily being addressed from a
technology perspective, with several high-k gate dielectrics
being proposed [2]. To date, most circuit-level leakage
minimization techniques focus only on sub-threshold
leakage reduction, without considering the effects of gate
leakage. One of the approaches that addresses gate
leakage, boosted-gate MOS [3], uses multiple threshold
voltage and multiple oxide thickness devices. The use of
PMOS-dominated circuits was introduced in [4] on the
basis that PMOS devices exhibit lower leakage as
compared to identical NMOS devices. The effect of gate
leakage on circuit performance and dynamic behavior of
the floating body in SOI devices was examined in [5, 6]. In
each of these reports, extensive SPICE simulations were
performed to obtain estimates of gate leakage. This can be
extremely time-consuming, especially for large circuits. In
addition, gate leakage current causes increased power
dissipation even in the active mode of operation and hence

Fig. 1: Contribution of different components to total power

consumption for three different technology generations

any leakage minimization scheme needs to consider the

effect of gate leakage in both active and standby mode.
In this paper, we account for the contribution of gate
leakage on total leakage by considering forward and
reverse gate tunneling through both NMOS and PMOS
devices. In this paper, we propose efficient techniques for
gate leakage estimation in steady based on a switch-level
analysis of the circuit and hence can efficiently analyze
large circuits. Gate leakage in conventional sleep-state
patterns (which focus only on sub-threshold leakage) are
re-evaluated and new sleep-state assignments for transistor
stacks are proposed for total leakage minimization. We
also present circuit re-organization schemes for total
leakage reduction of dynamic circuits in sleep mode.
Finally, we look into the effect of gate leakage on the
multi-threshold CMOS (MTCMOS [7]) and enhanced
multi-threshold CMOS (EMTCMOS [8]) configurations
and present design guidelines for optimal device sizing for
maximum total leakage reduction.
The rest of the paper is organized as follows. We first
begin by a brief analysis of gate leakage current. We then
propose our approach for gate leakage estimation in
Section 3. Techniques and optimization guidelines for total
leakage minimization are presented in Section 4. The
findings of this work are summarized in Section 5. All
results presented in this paper are for a sub 0.1m SOI
process at nominal supply voltage of 1.0V, temperature of
85C and nominal process conditions.

2 GATE LEAKAGE ANALYSIS

Gate leakage current for an NMOS transistor as a
function of gate-to-source (VGS) and drain-to-source (VDS)
bias in a state-of-the-art sub 0.1m SOI process is shown
in Fig. 2. Gate leakage is an exponential function of the
electric field across the gate oxide, so gate leakage current

Fig. 2: Gate leakage of a NMOS device as a function of gateto-source and drain-to-source bias

shows an exponential dependence on the gate-to-source

(VGS) bias. At high gate bias, gate leakage current
decreases with increasing drain-to-source bias. This can be
attributed to the fact that a higher drain voltage results in a
smaller electric field across the gate oxide at the drain end
of the channel (lower VGD). At low gate bias, gate leakage
was found to increase with increasing drain bias (due to
the increase in reverse gate leakage with increasing drain
bias, i.e., VGD). Gate leakage current was found to be
almost insensitive to the body-node voltage. At high gate
bias, the channel shields the body node from the gate. At
low gate bias, the edge-tunneling currents from the sourcedrain extensions to the gate dominate [9]. Thus, the gateto-source (VGS) and gate-to-drain (VGD) bias seen by the
device determine its gate leakage.

2 GATE LEAKAGE ESTIMATION

The bias conditions seen by a device in a circuit
depend on its position in the circuit and the applied input
vector. The six possible bias conditions for an NMOS
transistor at steady state are shown in Fig. 3 with the
associated gate leakage currents for those bias conditions.
The remaining two states, namely <101> and <110> at the
gate, drain and source of the transistor, are transient states.
In all of these states, the device terminals are assumed to
be at full supply-rail voltages. We pre-characterize the gate

Fig. 3: All possible steady state bias conditions seen by a

device and the associated gate leakage currents.

Fig. 4: States of all devices in a Nand3 cell for the applied

input vector <010>

leakage of a unit - width device in each of these states and

represent it as Ig(k) [11].
It can be seen that a device exhibits gate leakage only in
four of the six possible states in which there exists a
potential difference between the gate and drain or source
terminals of the device. In other words, the gate of the
leaky device acts like a resistor connected between the VDD
and VSS lines. The gate leakage of any device in the circuit
can hence be estimated from its bias state if there exists a
conducting path from its device terminals to the supplyrails. The total gate leakage of the circuit can be computed
as the sum of the gate leakage of the individual devices.
Given an input vector, it is possible to perform a
switch-level simulation to determine the state of the
internal nodes of the circuit. Here, it is assumed that the
internal nodes attain full logic levels (i.e., are either at VDD
or VSS). Also, in a transistor stack, it is assumed that the
entire voltage drops across the uppermost OFF device.
These are fairly good assumptions, since gate leakage is an
exponential function of the terminal voltages and is
negligible if no conducting path exists from the device
terminals to the supply-rails. When a device in a NMOS
transistor stack is OFF, there exists no conducting path
from VDD to the drain terminal of devices below it and
hence these nodes can be assumed to be nearly at ground
potential. For instance, when input <010> is applied to a
Nand3 cell as shown in Fig. 3, the output is at logic high
state. The internal nodes A and B are assumed to be at 0
and the bias state of each transistor can be identified.

Table 1: Our proposed estimation technique compared with

SPICE for all patterns of a Nand3 cell.

In this case, the PMOS transistors P1 and P3 are ON with

a high VGS and high VGD and hence are in S(4) state. On
the other hand, the PMOS transistor P2 is OFF with a
zero VGS and VGD and hence is in state S(0). Similarly, the
NMOS transistors N1, N2 and N3 are assumed to be in
states S(1), S(4) and S(0), respectively. The total gate
leakage can then be computed by scaling the width of each
device by the unit-width leakage in that state and adding
the individual gate leakages. To demonstrate its accuracy,
the gate leakage estimate obtained by this method for all
possible states of a Nand3 are tabulated in Table 1 and
compared with SPICE simulation results. As seen, the
leakage estimates obtained by this method are very
accurate, with an average error of less than 1% and a
maximum error of less than 2%.

4. LEAKAGE MINIMIZATION
4.1 Transistor Stacks
Consider a three-high NMOS transistor stack (as found in
the Nand3 cell shown in Fig. 5). The sub-threshold
leakage through the transistor stack is minimized when all
of the devices in the stack are turned OFF, i.e., when a
<000> pattern is applied. Since conventional leakage
minimization techniques focus on sub-threshold leakage,
the <000> pattern is believed to be the lowest leakage
vector for a Nand3 cell. However, when such a pattern is
applied, the output is high, and all of the PMOS devices
experience high gate-to-drain and gate-to-source voltages.
This results in a high field across the gate oxide causing
gate leakage, which can be substantial due to the greater
width of PMOS devices. To reduce gate leakage, it is
necessary to maintain the terminals of most of the devices
at the same potential. This can be achieved by turning
ON all but the lowest NMOS transistor in the stack, i.e.,
by applying the input pattern <110>. Under such an input
vector, only one PMOS device (P3) exhibits gate leakage.
The gate leakage of the ON NMOS transistors (N1, N2)
is also negligible, since the internal nodes in the stack are
charged almost to the supply rail (and hence the devices
have a low VGS/VGD). The OFF transistor (N3) at the
bottom of the stack prevents sub-threshold leakage from
increasing tremendously. Fig. 6 shows the sub-threshold,

Fig. 5: Leakage currents for a Nand3cell for <000> and

<110> input patterns.

Fig. 6: Sub-threshold and gate leakage for all possible input

patterns for a Nand3 cell.

gate and total leakage for all possible input vectors for a
Nand3 cell. The total leakage for some of these vectors is
clearly dominated by the gate leakage component. Even
though sub-threshold leakage for the vector <110> is
greater than sub-threshold leakage for the vector <000>,
<110> is the minimum total leakage state for Nand3 cell.
Thus, it is necessary to reevaluate conventional leakage
minimization schemes and input vector assignments to
account for the effect of gate leakage. With gate leakage
expected to increase more rapidly than sub-threshold
leakage, we expect that turning ON all but the lowest
device in a transistor stack will be the lowest leakage state
for a transistor stack in future technology generations.

4.2 Dynamic Circuits

This section focuses on sleep-state leakage
minimization of dynamic circuits. Consider a typical 2input dynamic And cell as shown in Fig. 7. During sleep
state, the clock is held either in the pre-charge phase (low)
or the evaluate phase (high). If the clock is held in the
evaluate phase, the dynamic node will be discharged, and
the output will be at logic high. Since, in a domino chain,
the output of a dynamic cell drives other similar cells, it
can be assumed that the inputs to the dynamic cell will also
be at logic high. In such a state, all of the devices in the
pull-down n-stack and the output pull-up transistor (i.e.,
devices on the evaluate path) will exhibit gate leakage.
Since these devices are sized to reduce delay, it can result
in significant gate leakage current. The sub-threshold
leakage in this state is small, since it is primarily through

Fig. 7: Typical dynamic cell (left) and our proposed

reconfiguration circuit (right).

the devices on the pre-charge path.

On the other hand, when the clock is held in the precharge phase, the dynamic node is charged high, the output
will be at logic low and the inputs can be assumed to be at
logic low. In this case, the devices on the pre-charge path
exhibit gate leakage, while the devices on the evaluate path
contribute to the sub-threshold leakage. Though subthreshold leakage of the NMOS pull-down tree is minimal
due to stacking effect, sub-threshold leakage through the
wide output pull-up transistor can be considerable. Thus,
in either of the two states, the total leakage of the cell may
be high, although due to different mechanisms.
Conventional techniques claim that holding the clock in
the evaluate phase is the lowest leakage sleep state, but this
approach completely neglects gate leakage.
Our proposed scheme is shown in Fig. 7. The output
pull-down tree is modified to incorporate two small
devices (N1, P1) that are controlled by the sleep-state
control signal S and pre-charge and evaluate clocks are
separated. In sleep state, the pre-charge clock is held high,
while the evaluate clock is held low. The inputs to the cell
can also be assumed to be high. The activated conditional
pull-up devices (P1, P2) therefore charge the dynamic
node and the output to logic high. In this state, gate
leakage of both the evaluate and the pre-charge paths are
reduced (only the evaluate transistor exhibits reverse gate
leakage current) since most of the devices see an identical
voltage at all of their terminals. The sub-threshold leakage
of the output pull-up PMOS device is also reduced due to
the OFF device N1, resulting in significant savings in
total leakage power. Since all of the additional devices are
small, the delay degradation on the critical path is minimal
The delay degradation is also reduced due to the presence
of the two-high NMOS stack along the pre-charge path.
The additional devices can be desirably sized to obtain
requisite pre-charge times and leakage savings. With a
reduction in the size of these additional devices, the
leakage savings increases at the expense of an increase in
pre-charge time [12]. Savings of over 73% in gate leakage
and 13% in total leakage are obtained for the dynamic And
cell shown in Fig. 4 by using Scheme A with an area
penalty of less than 7% and just over 1% degradation in
delay.

Fig. 8: MTCMOS (left) and enhanced MTCMOS (right)

configurations for leakage minimization.

4.3 Enhanced MTCMOS Scheme

In this section, we present design guidelines for
optimal device size selection for total leakage
minimization using stacked sleep devices in an MTCMOS
configuration by taking into consideration the effect of
gate leakage in active and standby modes. In an enhanced
MTCMOS configuration shown in Fig. 5, sub-threshold
leakage is further reduced in sleep mode due to the added
effect of stacking of high threshold voltage transistors.
However, the devices in the footer stack need to be
appropriately sized to ensure minimal performance
penalty.
In [8], the authors presented an optimal sizing scheme for
stacked sleep devices by considering only sub-threshold
leakage. It was shown that maximum savings in subthreshold leakage are obtained if the devices in the stack
are sized as:
W
and W1 = W , where =
with
W0 =

1 + 2
(1 )
being the DIBL factor [10]. In such a scenario, the lower
device in the stack is bigger than the upper device causing
an increase in the potential of the intermediate node. This
results in an increased negative gate-to-source bias and a
reduced drain-to-source bias (i.e. reduced DIBL) for the
upper device resulting in reduced sub-threshold leakage.
However, it can be shown that for such a configuration, the
average gate leakage is always greater than that for the
MTCMOS configuration [13]. The total leakage factor,
which is the ratio of the average total leakage in the
MTCMOS configuration to the average total leakage in the
enhanced MTCMOS is always less than 1, as shown in Fig
7.
The stacked sleep devices can also be sized to maximize
he savings in gate leakage factor as
W0 = W .(1 + ) and W1 = W . (1 + ) where is a

weighted ratio of the gate leakage in the off state to the on

state which can be shown to be always greater than 1. Thus
the lower device is required to be bigger than the upper

Fig. 9: Total leakage factor as a function of the input

occurrence probability (activity time) for various enhanced
MTCMOS configurations.

device in this case. This results in a lower gate leakage in

the off state and hence increased gate leakage savings.
This condition is clearly opposite to the optimal device
width condition for sub-threshold leakage optimization and
hence the savings in gate leakage come at an expense of
reduced savings in sub-threshold leakage. Yet, it can be
seen from Fig. 9 that optimizing for gate leakage can result
in a total leakage factor greater than 1 indicating that an
enhanced MTCMOS configuration results in increased
leakage savings at identical performance as compared to
an MTCMOS configuration. Also, optimizing for gate
leakage is nearly identical to optimizing for total leakage
and this can be expected to be true in future technology
generations due to the increasing magnitude of gate
leakage current.

4.4 Test Circuits

In order to validate the above mentioned leakage
minimization schemes, test circuits have been
implemented in a sub 0.1m advanced SOI process. An 8bit Brent Khung adder has been used as a design vehicle
and has been implemented in various dynamic circuit
configurations, with MTCMOS and various enhanced
MTCMOS configurations having sleep device stack
optimized for sub-threshold and gate leakage. The
footprint of the test circuits is shown in Fig. 10.

[2]

[3]

[4]

[5]

[6]

[7]

[8]

5. CONCLUSION
In this paper, we have shown the growing importance
of gate leakage current and have clearly demonstrated the
need to consider gate leakage current in any leakage
minimization scheme. We presented an efficient technique
for gate leakage estimation that is accurate to within 5% of
SPICE simulation results. We further presented optimal
leakage reduction vectors for transistor stacks and
proposed dynamic circuit schemed that results in over 70%
reduction in gate leakage in standby mode at less than 3%
delay degradation. Finally, we presented design guidelines
for optimal device size selection for stacked sleep devices
in an enhanced MTCMOS configuration and illustrated
that optimizing for gate leakage is nearly identical to
optimizing for total leakage.

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Fig. 10: Footprint of test circuits for validation of above mentioned leakage reduction schemes in sub 0.1
m SOI process