LOW POWER FPGA DESIGN

Neville Dsouza, Melwin Poovakottu, Rubin Stephen, Bradley Quadros

Department of Electronics and Telecommunication Engineering,
DON BOSCO INSTITUTE OF TECHNOLOGY

Abstract A complete system for the

implementation of digital logic in a FieldProgrammable Gate Array (FPGA) platform is
introduced. The variety of novel power-efficient
FPGA architecture was designed and simulated in
STM 0.130 m Cmos technology. The detailed
design and circuit characteristics of the
Configurable Logic Block were determined and
evaluated in terms of energy, delay and area. A
number of circuit-level low-power techniques were
employed because power consumption was the
primary concern.
Keywords: FPGA, circuit design, CAD tools

Introduction
In the 90-nm era and beyond, the number of
transistors on a chip surmounts one billion and the
development cost and time have been increasing
rapidly. One solution for this problem is to use a
reconfigurable LSI such as an FPGA (field
programmable gate arrays), which is attractive
(NRE) cost and short time-to-market [1]. Since an
FPGA uses more transistors per function than SoC
(system-on-a-chip) to achieve programmability,
power consumption, es-pecially the leakage power
of an FPGA is larger than that of an SoC.
FPGAs have recently benefited from
technology process advances to become a
significant alternative to Application Specific
Integrated Circuits (ASICs). An important feature
that has made FPGAs, particularly attractive is that
the logic mapping and implementation flow is
similar to the ASIC design flow (from VHDL or
Verilog down to the configuration bitstream)
provided by the industrial sector. However, in order
to implement real-life applications on an

FPGA platform, embedded or discrete, increasingly

performance and power-efficient FPGA
architectures are required.
Furthermore, efficient architectures cannot be used
effectively without a complete set of tools for
implementing logic while utilizing the
advantages and features of the target device
Field-Programmable Gate Arrays (FPGAs) are prefabricated silicon devices that can be electrically
programmed to become almost any kind of digital
circuit or system. They provide a number of
compelling advantages over fixed-function
Application Specific Integrated Circuit(ASIC)
technologies such as standard cells ASICs
typically take months to fabricate and cost
hundreds of thousands to millions of dollars to
obtain the first device; FPGAs are configured in
less than a second (and can often be reconfigured if
a mistake is made) and cost anywhere from a few
dollars to a few thousand dollars. The flexible
nature of an FPGA comes at a significant cost in
area, delay, and power consumption.

1. FPGA ARCHITECURE
FPGAs, as illustrated in Figure, consist of an array
of programmable Logic blocks of potentially
different types, including general Logic, memory
and multiplier blocks, surrounded by a
programmable
Routing fabric that allows blocks to be
programmable interconnected. The array is
surrounded by programmable input/output blocks,
labelled I/O in the figure that connects the chip to
the outside world. The programmable term in
FPGA indicates ability to program

A function into the chip after silicon fabrication is

complete. This customization is made possible by
the programming technology, which is A method
that can cause a change in the behavior of the prefabricatedChip after fabrication, in the field,
where system users create designs.

LUT Inputs (K).

The LUT is used for the implementation
of logic functions. It has been demonstrated in that
a 4-input LUT lead to the lowest power
consumption for theFPGA, providing an efficient
area-delay product [1].
Cluster Size (N).
The Cluster Size corresponds to the number of
BLEs within a CLB. Taking into account mostly
the minimization of power consumption, our
design exploration proved that a cluster size of 5
BLEs leads to the minimization of power
consumption [1].

Fig.1 FPGA Architecture

Basic Architecture
Most of the today's FPGAs are categorized as
island-style FPGAs. An island-style FPGA is a two
dimensional array of logic blocks surrounded by
I/O cells on its sides. These logic blocks and I/O
cells are all interconnected using a programmable
routing architecture. In order to improve the
performance of FPGAs, most of the commercial
FPGAs also include hard blocks with fixed
functionality which offer faster, more compact
implementations of hardware functions than
synthesis on the general logic of an FPGA.
Example of such hard blocks is SRAMs and
multipliers.
Fig.1 illustrates such architecture.

Fig. 2.a Basic Logic Element

Fig.2.b Logic Cluster

Logic Blocks
Lookup-Tables (LUTs) can be used to store truth
table implementations of logic functions. By
storing the proper bits in the LUTs, various
combinational logic functions could be
implemented. To be able to implement sequential
circuits like FSMs, a register is connected to the
output of LUTs. This structures which is shown
above is called a Logic Element (LE) or Basic
Logic Element (BLE).

Previously, it is shown that 4-input LUTs give the

best Area-Delay compromise in FPGAs [1].

2. POWER CONSUMPTION
Sources of power consumption:
The three main sources of power consumption are
inrush, standby and dynamic. Current associated
with the power-up sequence of a device is referred
to as inrush current. Standby power, also known as
static power, is the power of a device when the
power lines are active and when there is no
switching activity on the I/Os. Dynamic power,
also referred to as switching power, is the power
associated with a device during normal operation.
Inrush current is device-specific. For example,
SRAM-based FPGAs have a high inrush current
because on power-up these devices are not
configured and need to actively download data
from external memory chips to configure their
programmable resources, such as routing
connections and lookup tables. Conversely, antifuse-based FPGAs do not have a high inrush
current since they do not require power-on
configuration.
Much like inrush power, standby power depends
heavily on the electrical characteristics of a
component. Due to the extensive number of SRAM
cells within SRAM FPGA interconnects, they can
consume hundreds of milliamps even at standby.
Since anti-fuse FPGAs have metal-to-metal
interconnects, they do not require the additional
transistors, and hence power, to retain
interconnects. However, for both FPGA process
types, leakage current increases as process
geometry shrinks, which exacerbates the power
problem.
As an additional dilemma, dynamic power can
easily be several times greater than standby power.
Dynamic power is proportional to the frequency of
charging and discharging of internal parasitic
capacitances of a component, such as registers and

combinatorial logic, so optimizations are generally

design-oriented.

Cutting power consumption:

The following are some techniques that can be
used to minimize power consumption within an
FPGA design:

Voltage Switching: Pavg = Cload * Vdd *

fclk

The above equation shows that the average

switching power dissipation is proportional to the
square of the power supply voltage; hence,
reduction of Vdd will significantly reduce the
power consumption [2].

3. LOW POWER IMPLEMENTATION

Gated Clock Signals :

The switching power dissipation in the clock

distribution network can be very significant. If
certain logic blocks in a system are not
immediately used during the current clock
cycle, temporarily disabling the clock signals of
these blocks will obviously save switching
power. Temporarily unused modules can have
their clocks slowed or stopped. Power savings
comes from clocks only being provided to
certain portions of the design at any given time.
Gating a clock contributes to a significant
amount of power savings because the number
of active clock buffers reduces the number of
toggling flip-flops decreases, and consequently
the fan-out of those flip-flops will be less likely
to toggle. Gating clocks requires careful
planning and partitioning of algorithms, but the
power savings can be considerable [2].
Adding latches at the inputs of large
combinatorial logic (e.g., wide bus multiplexer)

can suppress invalid switching activity, because

inputs are latched only when the outputs are
supposed to be updated. Similarly, control registers
can be implemented to enable or disable lowerlevel modules (e.g., state machines in sub
modules). Holding large buses and sub modules in
a constant state helps reduce the amount of
irrelevant switching. Gated clock at BLE level
saves upto 77% of power [1].

4. ADVANTAGES OF FPGA
An FPGA is similar to several other types of
devices which have been around for quite a while,
the difference being that an FPGA is simply much
more expandable and versatile. The devices which
FPGAs get compared to most often are CPLDs
(Complex Programmable Logic Devices), which
are similar in function but typically have way less
logic gates inside them; Customizable CPU design
is much more feasible with an FPGA. Once upon a
time, CPLDs also had the distinct advantage of
retaining their configuration when turned off;
When FPGAs first came out, they used simple
SRAM to hold their configuration, which of course
would be lost when the device lost power. Back
then, the FPGA had to be programmed from
scratch every time it was turned on, usually from a
separate serial ROM chip. But today, FPGAs come
in Flash, EPROM, and EEPROM variants, which
will retain configuration, and which can also be reprogrammed. (Fuse and anti-fuse FPGAs also
exist, which act like PROMs in that they are onetime programmable, and cannot be reprogrammed
afterward.) Despite this, however, most FPGAs
still use SRAM for reasons of simplicity (when you
need to reprogram it, it's easier to re-encode a small
ROM chip than to reprogram a large FPGA chip),
so count on having to use a separate boot ROM for
the FPGA.
Use of an FPGA is broadly divided into two main
stages: The first is "configuration mode", the mode
in which the FPGA is when you first power it up.
Configuration mode is, as you may have guessed,
where you configure the FPGA; That is, this is
when you load your code into it, dictating how the
pins behave. Once configuration is complete, the

FPGA goes into "user mode", its main mode of

operation, where the programmed circuit actually
starts functioning.

Conclusions
An effective FPGA block is designed with
implementation of low power technique, and is also
verified for different combinational logics.

ACKNOWLEDGMENT
A Project is teamwork and reflects the contribution
of many people. We would like to thank
everyone who has contributed to this effort by
sharing their time and taking interest in our work
and encouraging us all the way through.

References
1. IEEE paper on A Novel FPGA Architecture
and an Integrated Framework of CAD.
2. CMOS Digital Integrated Circuits By Sung-Mo
Kang and Yusuf Leblebici,
3. R.P. Llopis and M. Sachdev, Low power,
testable dual edge triggered ip- ops, Proc.
IEEE International Symposium on Low Power
Electronics and Design, Monterey, USA, Aug.