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What is Synthesis?
Synthesis represents the transformation of an abstract description into a
more detailed descrition. In general, the term "synthesis" is used for the
automated transformation of RT level descriptions into gate level representations.
This transformation is mainly influenced by the set of basic cells that is available
in the target technology. While simple operations like comparisons and either/or
decisions are easily mapped to boolean functions, more complex constructs like
mathematical operators are mapped to a tool specific macro cell library first.
This means that a number of adder, multiplier, etc. architectures are known
to the synthesis tool and these designs are treated as if they were designed
by the user.
followed by the architecture name. Once again, the keyword ' architecture '
may be repeated after the keyword ' end ' in VHDL'93.
Explain Various types of Modelling styles ?
The Various modelling styles are :Structural, behavioural, dataflow and mixed style.
Structural Description Method: It expresses the design as an
arrangement of interconnected components. It is basically the
representation of the schematic in VHDL Language form.
Behavioral Description Method: describes the functional behavior of a
hardware design in terms of circuits and signal responses to various stimuli.
A Behavioral Description uses a small number of processes where each process
performs a number of sequential signal assignments to multiple signals.
The hardware behavior is described algorithmically and this modelling style
is the most frequently used and the best way to model any algorithm.
The advantage of models at this level is that models for simulation can be
built quickly.
Data-Flow Description Method: is similar to a register-transfer language
This method describes the function of a design by defining the flow of
information from one input or register to another register or output.
Data-Flow Description uses a large number of concurrent signal assignment
statements. A concurrent statement executes asynchronously with respect
to other concurrent statements.
The concurrent statements used in data flow description include:- block statement (used to group one or more concurrent statements)
- concurrent procedure call- concurrent assertion statement
- concurrent signal assignment statement
measurable unit, but from a hardware design perspective one should think
of delta delay as being the smallest time unit one could measure, such as
a femtosecond(fs).
2. Inertial delay - The inertial delay causes the pulses less than specified delay
to get suppressed & will not propogate these pulses to change the output.
The inertial delay model is specified by adding an after clause to the
signal assignment statement. Inertial delay is basically a default delay,
i.e it's a component delay.
3. Transport delay - Tranport delay adds the propogation delay to the signal.
The transport delay model just delays the change in the
output by the time specified in the after clause.
Transport delay basically represents a wire delay.
e.g. q <=transport a nor b after 1ns ;
W = weak unknown
L = weak "0"
H = weak "1"
- = dont care
Type std_logic is unresolved type because of 'U','Z' etc. It is illegal to
have a multi-source signal in VHDL. So use 'bit' logic only when the signals
in the design doesn't have multi sources. If you are unsure about this then
declare the signals as std_logic or std_logic_vector,because then you will
be able to get errors in the compilation stage itself. But many of the operators
such as shift operators cannot be used on 'std_logic_vector' type.So you may
need to convert them to bit_vector before using shift operations.
One example is given below:
example of how to shift a std_logic signal : right shifting logically by 2 bits.
Here, count is std_logic_vector.
output <= To_StdLogicVector(to_bitvector(count) srl 2); to_bitvector converts Std_Logic_Vector to
bit_vector. To_StdLogicVector converts bit_vector to Std_Logic_Vec
wait-statements
The drivers are labeled s1,s2,s3, and s4. The value of the signal dbus is
computed by a bus resolution function (brf in our example). Bus resolution
functions are user-defined and are evaluated when one of the drivers of the
signal receives a new value (event). The 'resolved' value is then generated
by the bus resolution function
all kinds of the loops may contain the 'next' and 'exit' statements.
----------------------------------------------------------------------A statement that may be used in a loop to cause the next iteration.
[ label: ] next [ label2 ] [ when condition ] ;
next;
next outer_loop;
In the above example, a record type, switch_info, is declared. This example makes
use of the binary enumerated type declared previously. Note that values are
assigned to record elements by use of the field name.